Symbol: mmUVD_VCPU_CNTL
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
341
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
492
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
303
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
455
WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
379
WREG32(mmUVD_VCPU_CNTL, 1 << 9);
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
474
WREG32(mmUVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
795
WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
907
WREG32(mmUVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1036
WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1163
WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
905
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1051
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1214
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
912
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1026
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1254
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
880
UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1034
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1096
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1196
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1254
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1274
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1278
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1628
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1633
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1057
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1117
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1126
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1222
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1283
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1300
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1304
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1676
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1681
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,