sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

260

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

594

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

305

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

631

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

718

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

861

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

394

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

469

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2049

SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

424

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

516

UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1498

SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

638

WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

729

VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1491

mmUVD_VCPU_CACHE_SIZE2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

560

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

651

VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);