sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

249

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

583

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

294

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

620

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

704

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

847

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

378

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

449

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2017

SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

408

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

480

UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

483

UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1468

SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

622

WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

693

VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

696

VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1462

mmUVD_VCPU_CACHE_SIZE0),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

544

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

615

VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

618

VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);