sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

259

WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

593

WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

304

WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

630

WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

717

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

860

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

393

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

468

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2046

SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

423

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

514

UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1495

SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

637

WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

727

VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1488

mmUVD_VCPU_CACHE_OFFSET2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

559

WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

649

VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);