sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

684

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

723

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1343

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1383

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

608

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

619

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

681

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

692

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

748

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

635

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

646

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

695

UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

746

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

757

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

851

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

862

WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

912

VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

962

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

973

WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1005

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1025

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

885

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

905

WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

956

VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);