mmUVD_REG_XX_MASK
WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);