sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

128

return RREG32(mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

160

WREG32(mmUVD_RB_WPTR2,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

877

WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1126

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

126

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

165

WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1011

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1258

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1345

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1698

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1716

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

67

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1166

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1195

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1343

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1680

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1707

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1338

WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1562

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1712

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1852

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1879

WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

79

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1370

WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1611

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1770

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2089

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2116

WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

83

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),