sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

126

return RREG32(mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

157

WREG32(mmUVD_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

870

WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1119

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

124

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

162

WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1004

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1255

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1338

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1696

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1713

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1157

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1192

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1333

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1675

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1700

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

74

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1329

WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1559

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1702

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1847

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1872

WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

77

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1361

WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1608

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1760

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2084

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2109

WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),