sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

876

WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

98

return RREG32(mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1125

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

92

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1010

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1259

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1344

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1681

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

66

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1165

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1196

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1342

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1657

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

75

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1337

WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1563

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1711

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1829

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

78

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1369

WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1612

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1769

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2066

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

82

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),