sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

869

WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

96

return RREG32(mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1118

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

90

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1003

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1256

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1337

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1679

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

64

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1156

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1193

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1332

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1655

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

73

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1328

WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1560

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1701

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1827

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

76

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1360

WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1609

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1759

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

2064

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

80

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),