sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

872

WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1121

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

926

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1006

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1335

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

56

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1159

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1330

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

2059

SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1331

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1508

SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1699

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

68

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1363

WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1502

mmUVD_RB_BASE_HI),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1757

WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

72

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),