sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

427

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

62

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

76

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

390

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

76

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

90

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

446

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

74

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

88

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

111

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

142

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

863

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

106

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1111

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

140

WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1160

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1264

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1347

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1407

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1486

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1504

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

996

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1150

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1198

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1347

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1446

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1468

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

985

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1146

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1322

WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1565

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1762

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1780

WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1171

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1351

WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1614

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1775

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1824

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1851

WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));