sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

424

WREG32(mmUVD_RBC_RB_RPTR, 0x0);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

426

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

48

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

387

WREG32(mmUVD_RBC_RB_RPTR, 0x0);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

389

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

62

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

443

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

445

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

60

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

81

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

860

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

862

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1108

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1110

ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

75

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1155

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1159

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1265

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1472

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

991

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

995

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1147

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1149

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1199

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1429

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

980

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

984

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1141

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1145

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1319

WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1321

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1566

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1745

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1166

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1170

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1347

WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1350

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1615

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1774

WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1807

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);