sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

328

WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

1489

WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

735

WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

966

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1039

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1042

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1250

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1267

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1272

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1320

ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1349

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1375

ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1381

reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1383

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1409

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

2023

adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

49

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

789

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

794

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

804

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

807

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1188

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1201

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1205

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1307

ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1322

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1351

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1354

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

58

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

801

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

807

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

820

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

823

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

864

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

867

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

961

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

990

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1015

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1018

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1021

WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1122

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1151

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1182

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1555

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1568

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1572

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1642

WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1674

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1690

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1716

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1719

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1725

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

60

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

61

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1038

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1041

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1044

WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1147

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1182

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1604

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1617

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1621

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1731

ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1745

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1779

WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1782

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

65

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

715

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

721

WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

732

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

735

WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);