sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c

355

WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c

317

WREG32(mmUVD_LMI_CTRL, 0x203108);

sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c

356

WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c

767

WREG32(mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

1007

WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c

892

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1058

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1113

WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

870

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

871

WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1034

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1035

WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

896

UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1050

VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1204

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1206

WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1073

VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1239

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1240

WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |