sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1313

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1327

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1328

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1356

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1368

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1387

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1388

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

1416

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c

81

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1303

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1314

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1317

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

1361

WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c

90

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1670

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1682

WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1685

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

1724

WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c

93

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1727

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1737

WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1740

SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

1788

WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);

sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c

97

SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)