Symbol: mmSDMA0_RLC0_RB_CNTL
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
115
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
137
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
187
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
206
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
234
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
254
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
256
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
270
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
271
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
82
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
166
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
174
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
178
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
387
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
437
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
456
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
505
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
638
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
640
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
654
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
655
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
144
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
148
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
152
mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
156
mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
161
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
373
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
423
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
442
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
492
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
562
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
564
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
578
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
579
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
250
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
289
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
308
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
351
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
471
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
473
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
487
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
488
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
273
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
312
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
331
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
383
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
506
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
508
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
522
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
523
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
195
mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
199
mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
204
+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
398
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
448
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
467
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
516
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
588
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
590
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
604
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
605
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/pci/drm/amd/amdgpu/cikd.h
570
#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL)
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
110
SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
97
SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
98
SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),