CPU_IS_SH3
#define SH_HAS_UNIFIED_CACHE CPU_IS_SH3
if (CPU_IS_SH3)
CPU_IS_SH3 ? SH3_TCR_TPSC_RTC : SH4_TCR_TPSC_RTC);
(CPU_IS_SH3 ? SH3_TCR_TPSC_RTC : SH4_TCR_TPSC_RTC));
CPU_IS_SH3 ? sh3_clock_intr : sh4_clock_intr, NULL, "clock");
if (CPU_IS_SH3)
if (CPU_IS_SH3)
if (CPU_IS_SH3) {
if (CPU_IS_SH3)
if (CPU_IS_SH3)
if (CPU_IS_SH3) \
if (CPU_IS_SH3) {
if (CPU_IS_SH3) {
if (CPU_IS_SH3) {
if (CPU_IS_SH3)
if (CPU_IS_SH3)
if (CPU_IS_SH3)
__sh_switch_resume = CPU_IS_SH3 ? sh3_switch_resume : sh4_switch_resume;
CPU_IS_SH3 ? sh3_vector_tlbmiss_end - sh3_vector_tlbmiss :
if (CPU_IS_SH3)
if (CPU_IS_SH3)