Symbol: mmMP0_SMN_C2PMSG_64
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
111
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
117
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
90
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
96
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
294
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
307
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
351
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
370
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
377
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
409
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
118
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
125
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
49
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
55
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
99
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
162
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
165
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
182
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
192
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
222
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
167
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
170
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
179
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
182
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
237
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
244
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
261
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
274
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
313
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);