mmIH_RB_BASE
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);