sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3154

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3156

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3159

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3129

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3131

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3134

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3145

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3147

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3150

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],