Symbol: mmGC_EDC_CTRL
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
1100
cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
695
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
696
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
697
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
698
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
699
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
700
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
710
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
711
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
712
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
713
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
714
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c
715
{ mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },