Symbol: mmCRTC0_CRTC_TEST_PATTERN_CONTROL
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1033
dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
1045
dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, value);