sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1211

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1212

WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

341

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6617

WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6635

WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2641

WREG32(mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2643

WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK |

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

4551

WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4283

WREG32(mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4285

WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

211

SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3460

WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3462

WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

1502

{ 0x00000000, mmCP_MEC_CNTL },

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

1503

{ 0x00000000, mmCP_MEC_CNTL },

sys/dev/pci/drm/amd/pm/powerplay/inc/polaris10_pwrvirus.h

52

{ 0x50000000, mmCP_MEC_CNTL },

sys/dev/pci/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

213

cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

111

cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

192

mmCP_MEC_CNTL);

sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c

195

cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);