sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

227

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

265

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

362

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

213

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

251

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

348

reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

241

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

279

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

373

reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++)

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

415

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7049

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7112

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

297

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3713

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3772

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3824

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);