sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

234

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

220

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

184

WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

373

WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

208

WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

248

WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

391

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

6933

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7054

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);

sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

7106

WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2842

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c

2897

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4429

tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c

4479

tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

273

SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3583

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3696

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3766

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3821

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

3822

WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);