sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10476

wb_info->mcif_warmup_params.start_address.quad_part = afb->address;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10477

wb_info->mcif_warmup_params.region_size =

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10480

wb_info->mcif_warmup_params.p_vmid = 1;

sys/dev/pci/drm/amd/display/dc/dc_stream.h

102

struct mcif_warmup_params mcif_warmup_params;

sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

77

struct mcif_warmup_params *params)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

474

struct mcif_warmup_params warmup_params = {0};

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

485

if (wb_info->mcif_warmup_params.p_vmid == 0)

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

489

if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

490

wb_info->mcif_warmup_params.region_size != 0) {

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

494

warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

495

warmup_params.address_increment = wb_info->mcif_warmup_params.region_size;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

496

warmup_params.region_size = wb_info->mcif_warmup_params.region_size;

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

497

warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;

sys/dev/pci/drm/amd/display/dc/inc/hw/mcif_wb.h

78

struct mcif_warmup_params *params);

sys/dev/pci/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

77

struct mcif_warmup_params *params)