max_t
dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
pages_per_block = max_t(u32, pages_per_block,
pages_per_block = max_t(u32, 2UL << (20UL - PAGE_SHIFT),
size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks),
unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
start = max_t(unsigned long, ALIGN_DOWN(addr, size), prange->start);
u32 t_max = dte_data->max_t;
dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
u32 max_t;
min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
min_lane_width = max_t(uint8_t, 1, table_member2[0]);
max_t(u32, desired_mode->hdisplay + x, sizes->surface_width);
max_t(u32, desired_mode->vdisplay + y, sizes->surface_height);
clip->x2 = max_t(u32, clip->x2, clip_copy.x2);
clip->y2 = max_t(u32, clip->y2, clip_copy.y2);
clip->x2 = max_t(u32, clip->x2, x + width);
clip->y2 = max_t(u32, clip->y2, y + height);
wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
int num_channels = max_t(u8, 1, dram_info->num_channels);
ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
int num_channels = max_t(u8, 1, dram_info->num_channels);
ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
max_t(int, min_voltage_level,
min_slice_count = max_t(u8, min_slice_count, 2);
min_slice_count = max_t(u8, min_slice_count,
vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard);
vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300));
frames_before_su_entry = max_t(u8,
pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
wm0_lines = max_t(int, wm0_lines, wm->wm[0].lines);
max_page_size = max_t(u32, max_page_size, mr->min_page_size);
start = max_t(long, start, vm_start);
start = max_t(long, start, vm_start);
sz = max_t(u32, sz, SZ_4K);
ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
max_t(u32, stats->runtime.max_underflow, -dt);
return max_t(u32, val, 0xc0);
rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq);
sseu->eu_per_subslice = max_t(unsigned int,
sseu->eu_per_subslice = max_t(unsigned int,
sseu->eu_per_subslice = max_t(unsigned int,
drm_msleep(max_t(unsigned int, max, 1));
#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
alignment = max_t(typeof(alignment), alignment, vma->display_alignment);
size = max_t(typeof(size), size, vma->fence_size);
alignment = max_t(typeof(alignment),
guard = max_t(u32, guard, flags & PIN_OFFSET_MASK);
aligned_size = max_t(u32, ilog2(min_alignment), size);
aligned_size = max_t(u32, ilog2(min_alignment), size);
max_t(int, 2, DIV_ROUND_UP(num_online_cpus(), nengines));
sz = max_t(u32, 2 * PAGE_SIZE, sz);
align = max_t(u32, sizeof(u32), rounddown_pow_of_two(align));
size = max_t(u32, round_up(size, PAGE_SIZE), PAGE_SIZE);
target = max_t(u64, PAGE_SIZE, target);
total = max_t(u64, total, SZ_1G);
io_size = max_t(u64, io_size, SZ_256M); /* 256M seems to be the common lower limit */
size = max_t(u32, PAGE_SIZE, i915_prandom_u32_max_state(SZ_32M, &prng));
#define MAX_T(t, a, b) max_t(t, a, b)
#define clamp_t(t, x, a, b) min_t(t, max_t(t, x, a), b)
u32 t_max = dte_data->max_t;
dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
u32 max_t;
entity->priority = max_t(s32, (s32) sched_list[0]->num_rqs - 1,
middle_count = max_t(int, 4, other_data_bytes);