sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1184

uint8_t max_lane_count;

sys/dev/pci/drm/amd/display/dc/dc_dp_types.h

1228

union max_lane_count max_ln_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

1609

link->dpcd_caps.lttpr_caps.max_lane_count =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2309

if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

2310

max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

390

link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_capability.c

391

link->dpcd_caps.lttpr_caps.max_lane_count <= 4);

sys/dev/pci/drm/i915/display/intel_display_types.h

1746

int max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1794

lane_count <= limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1988

lane_count <= limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2326

pipe_config->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2518

limits->max_lane_count,

sys/dev/pci/drm/i915/display/intel_dp.c

2571

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2617

limits->min_lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

3182

int max_lane_count = 4;

sys/dev/pci/drm/i915/display/intel_dp.c

3212

hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count,

sys/dev/pci/drm/i915/display/intel_dp.c

3386

intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

409

lane_count = intel_dp->link.max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.h

28

int min_lane_count, max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1334

intel_dp->link.max_lane_count = new_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

1962

*val = intel_dp->link.max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

446

crtc_state->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

510

crtc_state->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_test.c

65

limits->max_lane_count = intel_dp->compliance.test_lane_count;

sys/dev/pci/drm/i915/display/intel_tc.c

1192

if (tc->max_lane_count == 0)

sys/dev/pci/drm/i915/display/intel_tc.c

1193

tc->max_lane_count = 4;

sys/dev/pci/drm/i915/display/intel_tc.c

1542

tc->max_lane_count);

sys/dev/pci/drm/i915/display/intel_tc.c

1701

tc->max_lane_count);

sys/dev/pci/drm/i915/display/intel_tc.c

400

tc->max_lane_count = get_max_lane_count(tc);

sys/dev/pci/drm/i915/display/intel_tc.c

410

return tc->max_lane_count;

sys/dev/pci/drm/i915/display/intel_tc.c

68

u8 max_lane_count;