lt_dbg
lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",
lt_dbg(intel_dp, dp_phy,
lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");
lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");