sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c
137
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
166
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
102
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
339
lower_32_bits(guessed_wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
343
lower_32_bits((uintptr_t)wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c
475
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1057
lower_32_bits(tba_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
1066
lower_32_bits(tma_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
264
lower_32_bits(guessed_wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
268
lower_32_bits((uint64_t)wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
416
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
484
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
901
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
250
lower_32_bits(guessed_wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
254
lower_32_bits((uint64_t)wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
402
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
470
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
642
lower_32_bits(tba_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
651
lower_32_bits(tma_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
235
lower_32_bits(guessed_wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
239
lower_32_bits((uint64_t)wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
387
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
459
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
754
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c
329
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
331
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
547
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
363
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
582
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1112
lower_32_bits(tba_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
1120
lower_32_bits(tma_addr >> 8));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
278
lower_32_bits(guessed_wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
282
lower_32_bits((uintptr_t)wptr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
427
lower_32_bits(data64));
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
495
low = lower_32_bits(queue_address >> 8);
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
832
watch_address_low = lower_32_bits(watch_address);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
324
reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
326
reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
328
reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
330
reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
418
reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
420
reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
422
reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
424
reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
426
reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
428
reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_cper.c
430
reg_data[CPER_ACA_REG_SYND_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_debugfs.c
922
config[no_regs++] = lower_32_bits(adev->cg_flags);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1151
lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1482
lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_fence.c
374
return lower_32_bits(emitted);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1166
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1325
cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
1330
lower_32_bits(context->mem_context.shared_mc_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
2910
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3471
write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
3473
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
810
cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
814
cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
sys/dev/pci/drm/amd/amdgpu/amdgpu_psp.c
822
cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
3311
con->bad_page_cnt_threshold = min(lower_32_bits(val),
sys/dev/pci/drm/amd/amdgpu/amdgpu_uvd.c
935
amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
1074
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vce.c
684
amdgpu_ib_set_value(ib, lo, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
624
result += lower_32_bits(vm->generation);
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
539
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
553
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
555
amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
625
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
751
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
764
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
767
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
798
amdgpu_ring_write(ring, lower_32_bits(wb_addr));
sys/dev/pci/drm/amd/amdgpu/amdgpu_vpe.c
840
ib.ptr[1] = lower_32_bits(wb_addr);
sys/dev/pci/drm/amd/amdgpu/atom.c
716
ctx->ctx->divmul[0] = lower_32_bits(val64);
sys/dev/pci/drm/amd/amdgpu/atom.c
838
ctx->ctx->divmul[0] = lower_32_bits(val64);
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
136
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1296
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1298
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
1318
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
231
cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
284
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
286
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
292
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
622
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
677
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
727
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
729
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
752
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
756
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
780
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
782
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/cik_sdma.c
784
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
2308
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c
254
lower_32_bits(crtc_base));
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
2279
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
202
lower_32_bits(crtc_base));
sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c
2227
lower_32_bits(amdgpu_crtc->cursor_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3718
amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3720
amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3760
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3762
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3783
amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3808
amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
3810
amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4099
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5862
WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5911
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5948
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5985
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6022
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6528
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6533
WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6539
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6567
WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6571
WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
6576
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8575
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8673
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8708
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8739
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8741
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8752
gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8793
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8795
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8854
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8931
amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8958
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8967
amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
8998
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9547
lower_32_bits(addr), upper_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1513
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2524
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2568
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2612
lower_32_bits(addr) & 0xFFFFF000);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2630
lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2708
lower_32_bits(addr2));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2752
lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
2831
lower_32_bits(addr2));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3241
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3319
lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3459
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3538
lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
359
amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
361
amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3739
WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3744
WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3750
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3778
WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3782
WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
3787
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
404
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
406
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4171
mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4173
mqd->gds_bkup_base_lo = lower_32_bits(prop->gds_bkup_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4175
mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4177
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
433
amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
4360
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
458
amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
460
amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5792
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5888
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5923
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5954
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5956
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5967
gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6014
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6016
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6055
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6119
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6125
amdgpu_ring_write(ring, lower_32_bits(shadow_va));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6127
amdgpu_ring_write(ring, lower_32_bits(gds_va));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6129
amdgpu_ring_write(ring, lower_32_bits(csa_va));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6223
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6232
amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
6263
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
632
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1321
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2405
lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2456
lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2549
lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2601
lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2735
WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2740
WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2746
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2879
lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
2886
lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
298
amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3051
mqd->shadow_base_lo = lower_32_bits(prop->shadow_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3053
mqd->fw_work_area_base_lo = lower_32_bits(prop->csa_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3055
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
3237
mqd->fence_address_lo = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
343
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
345
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
372
amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
396
amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
398
amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4347
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4432
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4451
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4480
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4482
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4493
gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4534
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4536
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4575
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
4647
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
525
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1849
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2104
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2146
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2155
WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2158
WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2190
WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2209
WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
2400
dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2139
amdgpu_ring_write(ring, lower_32_bits(seq - 1));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2152
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2183
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2569
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2573
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2611
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2626
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2627
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
2915
mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3805
WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1537
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1563
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1589
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4255
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4259
WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4263
WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4333
amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4354
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4356
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
4413
mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5991
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5992
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
5994
WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6128
amdgpu_ring_write(ring, lower_32_bits(seq - 1));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6143
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6201
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6202
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6222
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6236
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6238
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6296
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
6317
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7143
amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7160
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7165
de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7176
amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
893
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1025
amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1027
amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1249
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3413
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3418
WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3422
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
3565
lower_32_bits(ring->mqd_gpu_addr
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4219
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4700
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4728
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
4756
ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5373
WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5442
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5538
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5577
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5579
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5591
lower_32_bits(addr), upper_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5650
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5652
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5690
amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5778
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5788
amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5847
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
5868
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
942
lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
945
amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
975
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
977
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
998
amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
392
ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
399
ib->ptr[ib->length_dw++] = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1841
lower_32_bits(ring->mqd_gpu_addr
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
190
lower_32_bits(queue_mask)); /* queue mask lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
193
amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
224
amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
226
amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
247
amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
273
amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
275
amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2879
lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2911
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2913
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2925
lower_32_bits(addr), upper_32_bits(addr),
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2977
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
2979
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3005
amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
476
ib.ptr[2] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
131
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v11_5_0.c
333
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
134
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v12_0.c
338
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
303
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_0.c
47
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
391
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v1_2.c
55
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
127
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_0.c
323
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
130
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v2_1.c
335
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
126
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0.c
330
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
129
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/gfxhub_v3_0_3.c
335
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/gmc_v10_0.c
398
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/gmc_v11_0.c
390
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/gmc_v12_0.c
426
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/gmc_v9_0.c
1009
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
297
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
269
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/ih_v7_0.c
269
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
172
WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
240
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
264
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
318
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
330
amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
393
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
539
WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v1_0.c
66
val = lower_32_bits(ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
365
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
450
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
451
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
453
WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
518
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
579
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
591
amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_0.c
650
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
369
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
478
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
479
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v2_5.c
481
WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
385
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
469
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
470
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v3_0.c
472
WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
421
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
476
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
505
WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
629
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
630
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0.c
632
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
292
MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
319
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
592
reg_offset, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
721
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
722
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
726
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
797
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
852
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
864
amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_3.c
929
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
466
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
551
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
645
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
646
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
648
WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
389
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
466
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
555
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
556
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
558
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
429
reg_offset, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
490
MMSCH_V5_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
517
WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
647
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
648
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_1.c
653
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
47
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
50
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v6_0.c
82
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
47
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
50
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
sys/dev/pci/drm/amd/amdgpu/lsdma_v7_0.c
82
WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1038
lower_32_bits(ucode_addr));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1044
lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1053
lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1127
mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
1148
mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
527
lower_32_bits(input->trail_fence_data);
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
951
lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE));
sys/dev/pci/drm/amd/amdgpu/mes_v11_0.c
975
lower_32_bits(ucode_addr));
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1097
lower_32_bits(adev->mes.event_log_gpu_addr +
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1117
lower_32_bits(ucode_addr));
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1167
lower_32_bits(ucode_addr));
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1206
lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1215
lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1287
mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
1308
mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
237
if (r < 1 || !(lower_32_bits(*status_ptr))) {
sys/dev/pci/drm/amd/amdgpu/mes_v12_0.c
559
lower_32_bits(input->trail_fence_data);
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
239
lower_32_bits(pt_base >> 12));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
327
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_0.c
61
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
337
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_7.c
60
hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
435
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v1_8.c
68
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
197
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_0.c
407
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
128
hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v2_3.c
323
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
144
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0.c
361
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
153
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_1.c
355
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
137
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_0_2.c
353
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
244
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
448
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v3_3.c
477
lower_32_bits(pt_base >> 12));
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
136
lower_32_bits(page_table_base));
sys/dev/pci/drm/amd/amdgpu/mmhub_v4_1_0.c
354
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
384
lower_32_bits(adev->vm_manager.max_pfn - 1));
sys/dev/pci/drm/amd/amdgpu/mmhub_v9_4.c
65
lower_32_bits(value));
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
293
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/nbif_v6_3_1.c
177
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
176
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v4_3.c
172
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v6_1.c
123
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_11.c
164
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_2.c
177
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_4.c
225
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_7.c
134
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/nbio_v7_9.c
255
lower_32_bits(adev->doorbell.base));
sys/dev/pci/drm/amd/amdgpu/psp_v10_0.c
79
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
330
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0.c
359
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
107
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v11_0_8.c
78
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v12_0.c
151
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
421
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
450
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
780
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
815
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
239
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v13_0_4.c
268
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
286
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
315
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v14_0.c
651
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
205
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/psp_v3_1.c
226
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1191
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1193
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1213
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
255
sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
260
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
313
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
315
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
321
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
447
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
554
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
609
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
663
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
665
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
692
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
716
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
718
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
720
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1633
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1635
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
1655
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
431
sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
436
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
489
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
491
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
497
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
688
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
710
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
828
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
883
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
936
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
938
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
961
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
965
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
989
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
991
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c
993
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1111
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1143
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1196
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1229
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1486
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1541
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1596
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1598
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1622
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1626
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1651
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1653
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
1655
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2571
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2573
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
2593
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
711
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
723
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
727
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
778
lower_32_bits(wptr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
815
sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
820
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
894
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
896
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
904
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1082
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1137
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1192
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1194
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1218
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1222
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1247
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1249
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
1251
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2272
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2274
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
2294
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
278
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
290
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
294
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
345
lower_32_bits(wptr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
382
sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
387
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
462
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
464
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
472
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
706
lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
730
WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
732
WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
760
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
818
WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
820
WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
833
lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v4_4_2.c
867
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1041
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1105
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1164
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1166
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1190
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1194
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1219
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1221
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
1223
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
2021
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
2023
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
2043
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
309
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
382
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
395
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
400
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
446
sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
451
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
454
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
532
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
534
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
543
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
717
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
719
WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
730
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
745
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
762
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
972
m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
979
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
983
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1004
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1063
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1065
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1089
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1093
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1118
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1120
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1122
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
1200
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
149
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
2025
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
2027
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
2047
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
222
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
236
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
245
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
249
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
294
sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
299
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
302
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
382
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
384
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
393
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
566
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
568
WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
580
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
595
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
609
WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
872
m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
879
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
883
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c
941
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1010
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1069
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1071
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1095
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1099
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1124
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1126
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1128
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1203
lower_32_bits(pd_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
150
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1839
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1841
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
1861
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
216
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
229
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
234
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
280
sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
285
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
288
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
364
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
366
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
375
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
510
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
512
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
523
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
531
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
547
WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
868
m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
872
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
876
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
894
m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
897
m->sdmax_rlcx_f32_dbg0 = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/sdma_v6_0.c
947
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1027
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1088
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1090
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1115
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1119
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1144
ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1146
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1148
ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
150
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1782
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1784
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
1813
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
218
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
231
lower_32_bits(ring->wptr << 2),
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
237
lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
284
sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
289
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
292
amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
368
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
370
amdgpu_ring_write(ring, lower_32_bits(seq));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
379
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
502
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
504
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
515
lower_32_bits(wptr_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
523
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
543
WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
723
lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
888
m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
892
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
896
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
911
m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
914
m->sdmax_rlcx_mcu_dbg0 = lower_32_bits(prop->fence_address);
sys/dev/pci/drm/amd/amdgpu/sdma_v7_0.c
964
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
169
WREG32(mmDMA_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
230
amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
283
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
330
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
331
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
354
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
357
ib->ptr[ib->length_dw++] = lower_32_bits(value);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
397
ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
sys/dev/pci/drm/amd/amdgpu/si_dma.c
437
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/si_dma.c
788
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
789
ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
811
ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
sys/dev/pci/drm/amd/amdgpu/si_dma.c
87
while ((lower_32_bits(ring->wptr) & 7) != 5)
sys/dev/pci/drm/amd/amdgpu/si_ih.c
85
WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
138
WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
103
WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
108
WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
114
lower_32_bits(adev->umsch_mm.data_start_addr));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
124
WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
147
WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, lower_32_bits(umsch->log_gpu_addr));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
228
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
90
lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
sys/dev/pci/drm/amd/amdgpu/umsch_mm_v4_0.c
95
lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
427
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v3_1.c
76
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
390
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v4_2.c
90
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
287
lower_32_bits(adev->uvd.inst->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
438
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
446
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
564
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v5_0.c
88
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1035
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1061
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1098
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
1127
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
142
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
158
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
161
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
613
lower_32_bits(adev->uvd.inst->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
855
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
863
WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
869
WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
870
WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
876
WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v6_0.c
877
WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1103
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1112
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1118
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1119
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1125
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1126
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1335
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1363
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
140
WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1413
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1456
lower_32_bits(pd_addr), 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
156
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
157
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
163
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
166
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
696
lower_32_bits(adev->uvd.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
707
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
714
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
744
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
838
lower_32_bits(adev->uvd.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
850
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
857
lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
244
WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
245
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
251
WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
252
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
94
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v2_0.c
96
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
153
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
155
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
157
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
281
WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
282
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
288
WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
289
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
295
WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
296
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
868
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
891
amdgpu_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
109
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
110
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
116
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
119
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
122
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
164
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
235
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
343
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
344
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
351
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
352
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
359
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
360
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
719
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vce_v4_0.c
760
lower_32_bits(pd_addr), 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
51
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_sw_ring.c
75
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1003
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1004
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1010
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1011
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1150
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1161
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1337
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1338
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1344
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1345
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1399
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1502
lower_32_bits(ring->wptr) | 0x80000000);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1504
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1607
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1646
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1714
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1717
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1766
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
1791
lower_32_bits(pd_addr), 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
370
lower_32_bits(adev->vcn.inst->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
382
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
390
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
441
lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
453
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
463
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
986
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v1_0.c
997
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1142
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1151
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1156
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1157
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1165
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1166
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1332
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1333
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1342
WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1343
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1462
lower_32_bits(ring->wptr) | 0x80000000);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1465
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1466
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1468
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1586
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1622
data1 = lower_32_bits(pd_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1697
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1698
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1700
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1704
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1705
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1707
WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1758
amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1782
lower_32_bits(pd_addr), 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
1905
WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2005
lower_32_bits(adev->vcn.inst->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2023
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2038
lower_32_bits(adev->vcn.inst->gpu_addr + offset +
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2057
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
2071
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
400
lower_32_bits(adev->vcn.inst->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
412
lower_32_bits(adev->vcn.inst->gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
420
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
428
lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
468
lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
489
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
509
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
521
lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
975
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
986
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1136
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1147
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1314
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1323
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1328
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1329
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1337
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1338
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1366
WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1456
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1473
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1487
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1506
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1519
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1701
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1702
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1711
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1712
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1777
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1778
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1780
WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1869
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1870
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1872
WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1876
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1877
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1879
WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
615
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
626
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
634
lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
642
lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
681
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
702
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
722
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
734
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1161
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1172
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1176
fw_shared->rb.wptr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1342
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1352
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1353
fw_shared->rb.wptr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1360
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1361
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1369
WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1370
WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1451
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1468
lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1483
lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1500
lower_32_bits(rb_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1514
lower_32_bits(rb_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1549
WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1759
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1760
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1769
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1770
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1842
fw_shared->rb.wptr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1844
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1848
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1849
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1851
WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2106
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2107
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2109
WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2113
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2114
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
2116
WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
537
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
548
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
556
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
564
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
603
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
624
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
644
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
656
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1406
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1423
lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1438
lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1464
rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1469
rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1476
rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1483
lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1511
WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1793
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1794
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1796
WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
467
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
477
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
485
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
493
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
542
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
563
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
583
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
595
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1058
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1074
regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1086
regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1105
rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1112
lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1132
WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1323
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1566
lower_32_bits(pd_addr), 0xffffffff);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1591
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1592
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1595
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
477
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
489
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
498
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
510
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
564
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
585
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
605
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
619
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
956
lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1457
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1458
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1460
WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
418
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
428
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
436
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
444
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
496
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
517
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
538
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
552
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1181
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1182
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
1184
WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
382
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
392
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
400
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
408
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
458
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
479
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
499
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
511
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1296
*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1297
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1300
lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
441
lower_32_bits(adev->vcn.inst[inst].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
452
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
460
lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
468
lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
520
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
541
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
561
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
575
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
752
WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
850
lower_32_bits(adev->vcn.inst[i].gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
866
regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
878
regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
897
rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
904
lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
924
WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
237
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
273
WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
232
lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
sys/dev/pci/drm/amd/amdgpu/vpe_v6_1.c
245
WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
1815
sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
sys/dev/pci/drm/amd/amdkfd/kfd_crat.c
2001
sub_type_hdr->length_low = lower_32_bits(size);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
116
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
192
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
194
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
236
m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
238
m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
352
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_cik.c
354
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
114
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
135
lower_32_bits(q->ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
178
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
181
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
183
m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
204
lower_32_bits(q->eop_ring_buffer_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
376
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v10.c
378
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
161
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
189
lower_32_bits(q->ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
231
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
234
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
236
m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
257
lower_32_bits(q->eop_ring_buffer_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
435
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
437
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v11.c
439
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
128
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
152
lower_32_bits(q->ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
194
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
197
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
199
m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
220
lower_32_bits(q->eop_ring_buffer_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
336
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
338
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v12.c
340
m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
191
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
216
lower_32_bits(q->ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
255
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
258
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
260
m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
288
lower_32_bits(q->eop_ring_buffer_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
506
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
508
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_v9.c
708
lower_32_bits(xcc_ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
116
m->cp_mqd_base_addr_lo = lower_32_bits(addr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
130
m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
132
m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
142
lower_32_bits(q->ctx_save_restore_area_address);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
184
m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
187
m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
189
m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
215
lower_32_bits(q->eop_ring_buffer_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
370
m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_mqd_manager_vi.c
372
m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
131
packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
133
packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
137
packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
141
lower_32_bits(vm_page_table_base_addr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
185
packet->ordinal2 = lower_32_bits(ib);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
212
packet->gws_mask_lo = lower_32_bits(res->gws_mask);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
215
packet->queue_mask_lo = lower_32_bits(res->queue_mask);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
289
lower_32_bits(q->gart_mqd_addr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
295
lower_32_bits((uint64_t)q->properties.write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
464
packet->addr_lo = lower_32_bits((uint64_t)fence_address);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
466
packet->data_lo = lower_32_bits((uint64_t)fence_value);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
67
packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
74
packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
78
packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_v9.c
82
lower_32_bits(vm_page_table_base_addr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
109
packet->ordinal2 = lower_32_bits(ib);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
134
packet->gws_mask_lo = lower_32_bits(res->gws_mask);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
137
packet->queue_mask_lo = lower_32_bits(res->queue_mask);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
187
lower_32_bits(q->gart_mqd_addr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
193
lower_32_bits((uint64_t)q->properties.write_ptr);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
265
packet->addr_lo = lower_32_bits((uint64_t)fence_address);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
267
packet->data_lo = lower_32_bits((uint64_t)fence_value);
sys/dev/pci/drm/amd/amdkfd/kfd_packet_manager_vi.c
70
packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1111
buf[5] = lower_32_bits(local_mem_size);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1519
page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1523
page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1526
page_table_base.low_part = lower_32_bits(pt_base);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
9611
attributes.address.low_part = lower_32_bits(address);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
1379
attributes.address.low_part = lower_32_bits(address);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
350
address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
870
address->grph.addr.low_part = lower_32_bits(addr);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
894
lower_32_bits(luma_addr);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
898
lower_32_bits(chroma_addr);
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
210
lower_32_bits((unsigned long)cpu_ptr),
sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
212
lower_32_bits(gpu_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
135
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c
175
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
269
entry->image_addr_low = lower_32_bits(info.mc_addr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
311
lower_32_bits(smu_data->smu_buffer.mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
383
lower_32_bits(smu_data->header_buffer.mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
206
reg_data = lower_32_bits(info.mc_addr) &
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
349
task->addr.low = lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
386
task->addr.low = lower_32_bits(smu8_smu->driver_buffer[i].mc_addr);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
620
lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
650
lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/smu8_smumgr.c
687
lower_32_bits(smu8_smu->toc_buffer.mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
101
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
172
lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c
56
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
111
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
206
lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c
60
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
186
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
236
lower_32_bits(priv->smu_tables.entry[table_id].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
269
lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
299
lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
389
lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr),
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c
410
lower_32_bits(priv->smu_tables.entry[TABLE_PPTABLE].mc_addr),
sys/dev/pci/drm/amd/pm/swsmu/smu11/navi10_ppt.c
2899
lower_32_bits(dummy_read_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
640
address_low = (uint32_t)lower_32_bits(address);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
657
address_low = (uint32_t)lower_32_bits(address);
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
700
lower_32_bits(driver_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
720
lower_32_bits(tool_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu12/smu_v12_0.c
281
lower_32_bits(driver_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
701
address_low = (uint32_t)lower_32_bits(address);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
732
lower_32_bits(driver_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
752
lower_32_bits(tool_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
686
address_low = (uint32_t)lower_32_bits(address);
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
717
lower_32_bits(driver_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu14/smu_v14_0.c
737
lower_32_bits(tool_table->mc_address),
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
752
lower_32_bits(feature_mask),
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
763
lower_32_bits(feature_mask),
sys/dev/pci/drm/amd/pm/swsmu/smu_cmn.c
820
upper_32_bits(feature_mask), lower_32_bits(feature_mask));
sys/dev/pci/drm/i915/display/intel_dsb.c
446
intel_dsb_emit(dsb, lower_32_bits(window),
sys/dev/pci/drm/i915/display/intel_dsb.c
606
intel_dsb_emit(dsb, lower_32_bits(head_tail),
sys/dev/pci/drm/i915/display/intel_vrr.c
498
lower_32_bits(crtc_state->cmrr.cmrr_m));
sys/dev/pci/drm/i915/display/intel_vrr.c
502
lower_32_bits(crtc_state->cmrr.cmrr_n));
sys/dev/pci/drm/i915/display/skl_universal_plane.c
1569
lower_32_bits(plane_state->ccval));
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
1394
lower_32_bits(target_addr),
sys/dev/pci/drm/i915/gem/i915_gem_execbuffer.c
3438
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
195
*cs++ = lower_32_bits(i915_vma_offset(dst->vma));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
199
*cs++ = lower_32_bits(i915_vma_offset(src->vma));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
241
*cs++ = lower_32_bits(i915_vma_offset(dst->vma));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_client_blt.c
246
*cs++ = lower_32_bits(i915_vma_offset(src->vma));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_coherency.c
224
*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1504
upper_32_bits(offset), lower_32_bits(offset));
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1532
*cmd++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1639
*cmd++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
1874
lower_32_bits(offset),
sys/dev/pci/drm/i915/gem/selftests/i915_gem_context.c
927
*cmd++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gem/selftests/igt_gem_utils.c
71
*cmd++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
507
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
564
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
589
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
106
vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
sys/dev/pci/drm/i915/gt/gen8_ppgtt.c
119
lower_32_bits(daddr));
sys/dev/pci/drm/i915/gt/intel_context_sseu.c
31
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2127
upper_32_bits(addr), lower_32_bits(addr));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2130
upper_32_bits(addr), lower_32_bits(addr));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2138
upper_32_bits(addr), lower_32_bits(addr));
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2235
vma_res ? lower_32_bits(vma_res->start) : ~0u);
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1730
return __gen12_csb_parse(XEHP_CSB_CTX_VALID(lower_32_bits(csb)), /* cxt to */
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1733
GEN12_CTX_SWITCH_DETAIL(lower_32_bits(csb)));
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1738
return __gen12_csb_parse(GEN12_CSB_CTX_VALID(lower_32_bits(csb)), /* cxt to */
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1740
lower_32_bits(csb) & GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE,
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1906
head, upper_32_bits(csb), lower_32_bits(csb));
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
1984
lower_32_bits(rq->fence.seqno),
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
2761
*cs++ = lower_32_bits(pd_daddr);
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
727
writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
sys/dev/pci/drm/i915/gt/intel_execlists_submission.c
731
writel(lower_32_bits(desc), execlists->submit_reg);
sys/dev/pci/drm/i915/gt/intel_ggtt.c
428
*cs++ = lower_32_bits(pte | addr);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
108
intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
sys/dev/pci/drm/i915/gt/intel_gt.c
340
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
sys/dev/pci/drm/i915/gt/intel_gtt.c
628
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
sys/dev/pci/drm/i915/gt/intel_gtt.c
664
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
sys/dev/pci/drm/i915/gt/intel_gtt.h
629
u64 v__ = lower_32_bits(v); \
sys/dev/pci/drm/i915/gt/intel_lrc.c
1423
*cs++ = lower_32_bits(i915_vma_offset(ce->vm->rsvd.vma));
sys/dev/pci/drm/i915/gt/intel_lrc_reg.h
37
(reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \
sys/dev/pci/drm/i915/gt/intel_lrc_reg.h
44
(reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \
sys/dev/pci/drm/i915/gt/intel_migrate.c
412
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/intel_migrate.c
445
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/intel_migrate.c
451
*cs++ = lower_32_bits(encode | it->dma);
sys/dev/pci/drm/i915/gt/intel_renderstate.c
68
s = lower_32_bits(r);
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
57
addr = lower_32_bits(phys);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2744
*cs++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_execlists.c
2752
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3103
*cs++ = lower_32_bits(addr);
sys/dev/pci/drm/i915/gt/selftest_execlists.c
3110
*cs++ = lower_32_bits(i915_vma_offset(result));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
174
*batch++ = lower_32_bits(hws_address(hws, rq));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
184
*batch++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
189
*batch++ = lower_32_bits(hws_address(hws, rq));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
198
*batch++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
202
*batch++ = lower_32_bits(hws_address(hws, rq));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
211
*batch++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
214
*batch++ = lower_32_bits(hws_address(hws, rq));
sys/dev/pci/drm/i915/gt/selftest_hangcheck.c
223
*batch++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1040
*cs++ = lower_32_bits(i915_vma_offset(scratch) + x);
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1108
*cs++ = lower_32_bits(i915_vma_offset(b_before));
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1124
*cs++ = lower_32_bits(i915_vma_offset(b_after));
sys/dev/pci/drm/i915/gt/selftest_lrc.c
1246
*cs++ = lower_32_bits(i915_vma_offset(batch));
sys/dev/pci/drm/i915/gt/selftest_rps.c
126
*cs++ = lower_32_bits(i915_vma_offset(vma) + end * sizeof(*cs));
sys/dev/pci/drm/i915/gt/selftest_rps.c
132
*cs++ = lower_32_bits(i915_vma_offset(vma) + loop * sizeof(*cs));
sys/dev/pci/drm/i915/gt/selftest_timeline.c
1218
lower_32_bits(this->fence.seqno));
sys/dev/pci/drm/i915/gt/selftest_timeline.c
1305
lower_32_bits(this->fence.seqno));
sys/dev/pci/drm/i915/gt/selftest_tlb.c
112
*cs++ = lower_32_bits(addr);
sys/dev/pci/drm/i915/gt/selftest_tlb.c
119
*cs++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
574
*cs++ = lower_32_bits(addr);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
587
*cs++ = lower_32_bits(addr + sizeof(u32) * idx);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
600
*cs++ = lower_32_bits(addr + sizeof(u32) * idx);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
609
*cs++ = lower_32_bits(addr);
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
877
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_fw.c
273
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
127
*cmd++ = lower_32_bits(pkt->addr_in);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
130
*cmd++ = lower_32_bits(pkt->addr_out);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
31
*cs++ = lower_32_bits(pkt->addr_in);
sys/dev/pci/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
34
*cs++ = lower_32_bits(pkt->addr_out);
sys/dev/pci/drm/i915/gt/uc/intel_guc.c
866
FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),
sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c
40
lower_32_bits(ggtt_offset),
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1185
u32 gt_stamp_last = lower_32_bits(guc->timestamp.gt_stamp);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1187
if (new_start == lower_32_bits(*prev_start))
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1307
gt_stamp_lo = lower_32_bits(gpm_ts);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
1310
if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2515
action[len++] = lower_32_bits(child->lrc.lrca);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2887
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2908
info->wq_desc_lo = lower_32_bits(wq_desc_offset);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
2910
info->wq_base_lo = lower_32_bits(wq_base_offset);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5676
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5721
*cs++ = lower_32_bits(offset);
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1039
return lower_32_bits(node->start + offset);
sys/dev/pci/drm/i915/gt/uc/intel_uc_fw.c
1104
intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
sys/dev/pci/drm/i915/gvt/aperture_gm.c
155
intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value));
sys/dev/pci/drm/i915/gvt/cmd_parser.c
882
*cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
sys/dev/pci/drm/i915/gvt/handlers.c
1949
vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
sys/dev/pci/drm/i915/i915_cmd_parser.c
1388
target_cmd_offset = lower_32_bits(jump_offset);
sys/dev/pci/drm/i915/i915_gpu_error.c
588
upper_32_bits(start), lower_32_bits(start),
sys/dev/pci/drm/i915/i915_gpu_error.c
589
upper_32_bits(end), lower_32_bits(end));
sys/dev/pci/drm/i915/i915_gpu_error.c
599
lower_32_bits(ee->faddr));
sys/dev/pci/drm/i915/i915_gpu_error.c
657
lower_32_bits(vma->gtt_offset));
sys/dev/pci/drm/i915/i915_perf.c
2111
*cs++ = lower_32_bits(delay_ticks);
sys/dev/pci/drm/i915/i915_vma.h
184
return lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/selftests/i915_request.c
1147
*cmd++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/selftests/i915_request.c
1151
*cmd++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/selftests/i915_request.c
1154
*cmd++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/selftests/igt_spinner.c
165
*batch++ = lower_32_bits(hws_address(hws, rq));
sys/dev/pci/drm/i915/selftests/igt_spinner.c
194
*batch++ = lower_32_bits(i915_vma_offset(vma));
sys/dev/pci/drm/i915/soc/intel_gmch.c
109
lower_32_bits(i915->gmch.mch_res.start));
sys/dev/pci/drm/include/drm/drm_fixed.h
71
return lower_32_bits(tmp);
sys/dev/pci/drm/radeon/cik.c
3620
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/cik.c
3682
radeon_ring_write(ring, lower_32_bits(src_offset));
sys/dev/pci/drm/radeon/cik.c
3684
radeon_ring_write(ring, lower_32_bits(dst_offset));
sys/dev/pci/drm/radeon/cik.c
6619
WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
sys/dev/pci/drm/radeon/cik_sdma.c
207
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/cik_sdma.c
613
radeon_ring_write(ring, lower_32_bits(src_offset));
sys/dev/pci/drm/radeon/cik_sdma.c
615
radeon_ring_write(ring, lower_32_bits(dst_offset));
sys/dev/pci/drm/radeon/cik_sdma.c
669
radeon_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/radeon/cik_sdma.c
727
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/radeon/cik_sdma.c
816
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/radeon/cik_sdma.c
818
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/radeon/evergreen.c
4287
dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
sys/dev/pci/drm/radeon/ni.c
1393
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/ni_dma.c
328
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/radeon/ni_dma.c
329
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/radeon/r100.c
3866
WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/r100.c
713
gtt[i] = cpu_to_le32(lower_32_bits(entry));
sys/dev/pci/drm/radeon/r300.c
108
addr = (lower_32_bits(addr) >> 8) |
sys/dev/pci/drm/radeon/r300.c
1339
WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/r520.c
155
WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/r600.c
2888
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/r600.c
2938
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/r600.c
3003
radeon_ring_write(ring, lower_32_bits(src_offset));
sys/dev/pci/drm/radeon/r600.c
3005
radeon_ring_write(ring, lower_32_bits(dst_offset));
sys/dev/pci/drm/radeon/r600_dma.c
254
radeon_ring_write(ring, lower_32_bits(gpu_addr));
sys/dev/pci/drm/radeon/r600_dma.c
296
radeon_ring_write(ring, lower_32_bits(fence->seq));
sys/dev/pci/drm/radeon/r600_dma.c
359
ib.ptr[1] = lower_32_bits(gpu_addr);
sys/dev/pci/drm/radeon/radeon_cursor.c
102
lower_32_bits(radeon_crtc->cursor_addr));
sys/dev/pci/drm/radeon/radeon_cursor.c
118
lower_32_bits(radeon_crtc->cursor_addr));
sys/dev/pci/drm/radeon/radeon_fence.c
97
seq = lower_32_bits(atomic64_read(&drv->last_seq));
sys/dev/pci/drm/radeon/rs400.c
223
entry = (lower_32_bits(addr) & LINUX_PAGE_MASK) |
sys/dev/pci/drm/radeon/rs400.c
238
gtt[i] = cpu_to_le32(lower_32_bits(entry));
sys/dev/pci/drm/radeon/rv515.c
462
WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
sys/dev/pci/drm/radeon/si.c
3371
radeon_ring_write(ring, lower_32_bits(addr));
sys/dev/pci/drm/radeon/si_dma.c
263
radeon_ring_write(ring, lower_32_bits(dst_offset));
sys/dev/pci/drm/radeon/si_dma.c
264
radeon_ring_write(ring, lower_32_bits(src_offset));
sys/dev/pci/drm/radeon/si_dma.c
80
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
sys/dev/pci/drm/radeon/si_dma.c
81
ib->ptr[ib->length_dw++] = lower_32_bits(src);
sys/dev/pci/drm/radeon/uvd_v2_2.c
48
radeon_ring_write(ring, lower_32_bits(addr));
