sys/dev/ic/mpireg.h

1413

u_int8_t link_config;

sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

551

&otg_master->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3917

&pipe_ctx->link_config.dp_link_settings))

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3921

&pipe_ctx->link_config.dp_tunnel_settings);

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

3924

&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/core/dc_resource.c

5492

if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1302

&pipe_ctx->link_config.dp_link_settings);

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1304

dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1305

dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1308

&pipe_ctx->link_config.dp_link_settings));

sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1544

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1204

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

889

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

494

&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1385

&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1503

struct dc_link_settings *link_settings = &pipe_ctx->link_config.dp_link_settings;

sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1506

if (pipe_ctx->link_config.dp_tunnel_settings.should_enable_dp_tunneling == false)

sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

815

dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

470

struct link_config link_config;

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

110

link->dc->link_srv->dp_get_encoding_format(&pipes[i]->link_config.dp_link_settings),

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

92

pipes[i]->link_config.dp_link_settings = *link_setting;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2044

&pipe_ctx->link_config.dp_link_settings;

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2222

&pipe_ctx->link_config.dp_link_settings);

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2382

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

sys/dev/pci/drm/amd/display/dc/link/link_dpms.c

2638

if (pipe_ctx->link_config.dp_tunnel_settings.should_use_dp_bw_allocation)

sys/dev/pci/drm/amd/display/dc/link/link_validation.c

378

dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings;

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

280

pipes[i]->link_config.dp_link_settings.lane_count =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

282

pipes[i]->link_config.dp_link_settings.link_rate =

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

284

pipes[i]->link_config.dp_link_settings.link_spread =

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

714

u8 link_config[2];

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

716

link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

717

link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

719

drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

751

u8 link_config[] = { link_bw, lane_count };

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

753

drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

754

ARRAY_SIZE(link_config));

sys/dev/pci/mpiireg.h

1251

u_int8_t link_config;