bin/csh/func.c

1017

} limits[] = {

bin/csh/func.c

1033

static struct limits *findlim(Char *);

bin/csh/func.c

1034

static rlim_t getval(struct limits *, Char **);

bin/csh/func.c

1036

static void plim(struct limits *, Char);

bin/csh/func.c

1037

static int setlim(struct limits *, Char, rlim_t);

bin/csh/func.c

1039

static struct limits *

bin/csh/func.c

1042

struct limits *lp, *res;

bin/csh/func.c

1045

for (lp = limits; lp->limconst >= 0; lp++)

bin/csh/func.c

1061

struct limits *lp;

bin/csh/func.c

1071

for (lp = limits; lp->limconst >= 0; lp++)

bin/csh/func.c

1086

getval(struct limits *lp, Char **v)

bin/csh/func.c

1165

plim(struct limits *lp, Char hard)

bin/csh/func.c

1188

struct limits *lp;

bin/csh/func.c

1198

for (lp = limits; lp->limconst >= 0; lp++)

bin/csh/func.c

1213

setlim(struct limits *lp, Char hard, rlim_t limit)

bin/ksh/c_ulimit.c

115

for (l = limits; l->name; l++) {

bin/ksh/c_ulimit.c

121

l = &limits[1];

bin/ksh/c_ulimit.c

135

set_ulimit(const struct limits *l, const char *v, int how)

bin/ksh/c_ulimit.c

177

print_ulimit(const struct limits *l, int how)

bin/ksh/c_ulimit.c

40

static void print_ulimit(const struct limits *, int);

bin/ksh/c_ulimit.c

41

static int set_ulimit(const struct limits *, const char *, int);

bin/ksh/c_ulimit.c

46

static const struct limits limits[] = {

bin/ksh/c_ulimit.c

61

const struct limits *l;

bin/ksh/c_ulimit.c

98

for (l = limits; l->name && l->option != optc; l++)

lib/libkvm/kvm_proc2.c

127

struct plimit limits, *limp;

lib/libkvm/kvm_proc2.c

284

limp = &limits;

lib/libkvm/kvm_proc2.c

286

KREAD(kd, (u_long)process.ps_limit, &limits))

sys/dev/pci/drm/amd/include/pptable.h

674

ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits;

sys/dev/pci/drm/amd/include/pptable.h

692

ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

385

ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

395

1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)));

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

399

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

406

limits->numEntries;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

407

entry = &limits->entries[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

409

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

446

ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

452

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

459

limits->numEntries;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

460

entry = &limits->entries[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

461

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

477

ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits =

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

482

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

489

limits->numEntries;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

490

entry = &limits->entries[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

491

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

531

ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits =

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

536

u32 size = limits->numEntries *

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

543

limits->numEntries;

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

544

entry = &limits->entries[0];

sys/dev/pci/drm/amd/pm/legacy-dpm/legacy_dpm.c

545

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4407

const struct amdgpu_phase_shedding_limits_table *limits)

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4411

if ((table == NULL) || (limits == NULL))

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4426

if (limits->count != (num_levels - 1))

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4722

const struct amdgpu_phase_shedding_limits_table *limits,

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4728

for (i = 0; i < limits->count; i++) {

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4729

if ((voltage <= limits->entries[i].voltage) &&

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4730

(sclk <= limits->entries[i].sclk) &&

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

4731

(mclk <= limits->entries[i].mclk))

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

344

struct phm_clock_and_voltage_limits *limits,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

351

limits->sclk = le32_to_cpu(limitable->entries[0].ulSCLKLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

352

limits->mclk = le32_to_cpu(limitable->entries[0].ulMCLKLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

353

limits->vddc = le16_to_cpu(limitable->entries[0].usVddcLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

354

limits->vddci = le16_to_cpu(limitable->entries[0].usVddciLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c

355

limits->vddgfx = le16_to_cpu(limitable->entries[0].usVddgfxLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

427

struct phm_clock_and_voltage_limits *limits,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

430

limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) |

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

432

limits->mclk = ((unsigned long)table->entries[0].ucMclkHigh << 16) |

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

434

limits->vddc = (unsigned long)le16_to_cpu(table->entries[0].usVddc);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/processpptables.c

435

limits->vddci = (unsigned long)le16_to_cpu(table->entries[0].usVddci);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1531

const struct phm_clock_and_voltage_limits *limits =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1534

info->engine_max_clock = limits->sclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1535

info->memory_max_clock = limits->mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1538

if (limits->vddc >= table->entries[i].v) {

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1692

const struct phm_clock_and_voltage_limits *limits =

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

1705

clocks->memory_max_clock = limits->mclk;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

828

struct phm_clock_and_voltage_limits *limits,

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

835

limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

836

limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

837

limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

838

limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

839

limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c

840

limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);

sys/dev/pci/drm/i915/display/intel_display.c

4615

const struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_display.c

4646

crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);

sys/dev/pci/drm/i915/display/intel_display.c

4647

crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];

sys/dev/pci/drm/i915/display/intel_display.c

6241

struct intel_link_bw_limits *limits,

sys/dev/pci/drm/i915/display/intel_display.c

6279

ret = intel_modeset_pipe_config(state, crtc, limits);

sys/dev/pci/drm/i915/display/intel_dp.c

1775

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

1780

for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

1781

bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

1789

if (link_rate < limits->min_rate ||

sys/dev/pci/drm/i915/display/intel_dp.c

1790

link_rate > limits->max_rate)

sys/dev/pci/drm/i915/display/intel_dp.c

1793

for (lane_count = limits->min_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1794

lane_count <= limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1974

const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp.c

1984

if (link_rate < limits->min_rate || link_rate > limits->max_rate)

sys/dev/pci/drm/i915/display/intel_dp.c

1987

for (lane_count = limits->min_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

1988

lane_count <= limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2162

const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp.c

2179

max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

2188

min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

2198

limits,

sys/dev/pci/drm/i915/display/intel_dp.c

2222

bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp.c

2225

return pipe_bpp >= limits->pipe.min_bpp &&

sys/dev/pci/drm/i915/display/intel_dp.c

2226

pipe_bpp <= limits->pipe.max_bpp;

sys/dev/pci/drm/i915/display/intel_dp.c

2231

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

2241

if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {

sys/dev/pci/drm/i915/display/intel_dp.c

2257

const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp.c

2266

forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2270

limits, forced_bpp, timeslots);

sys/dev/pci/drm/i915/display/intel_dp.c

2284

if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)

sys/dev/pci/drm/i915/display/intel_dp.c

2288

limits, pipe_bpp, timeslots);

sys/dev/pci/drm/i915/display/intel_dp.c

2301

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

2310

forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2315

int max_bpc = limits->pipe.max_bpp / 3;

sys/dev/pci/drm/i915/display/intel_dp.c

2319

if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {

sys/dev/pci/drm/i915/display/intel_dp.c

2325

pipe_config->port_clock = limits->max_rate;

sys/dev/pci/drm/i915/display/intel_dp.c

2326

pipe_config->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2328

dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

2330

dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);

sys/dev/pci/drm/i915/display/intel_dp.c

2366

const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp.c

2390

conn_state, limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2393

conn_state, limits, timeslots);

sys/dev/pci/drm/i915/display/intel_dp.c

2472

struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

2482

fxp_q4_from_int(limits->pipe.max_bpp));

sys/dev/pci/drm/i915/display/intel_dp.c

2487

if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))

sys/dev/pci/drm/i915/display/intel_dp.c

2490

limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

2498

limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);

sys/dev/pci/drm/i915/display/intel_dp.c

2503

limits->pipe.max_bpp / 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2510

limits->link.max_bpp_x16 = max_link_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp.c

2518

limits->max_lane_count,

sys/dev/pci/drm/i915/display/intel_dp.c

2519

limits->max_rate,

sys/dev/pci/drm/i915/display/intel_dp.c

2520

limits->pipe.max_bpp,

sys/dev/pci/drm/i915/display/intel_dp.c

2521

FXP_Q4_ARGS(limits->link.max_bpp_x16));

sys/dev/pci/drm/i915/display/intel_dp.c

2528

struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

2531

const struct link_config_limits orig_limits = *limits;

sys/dev/pci/drm/i915/display/intel_dp.c

2535

limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2536

limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3);

sys/dev/pci/drm/i915/display/intel_dp.c

2538

if (limits->pipe.min_bpp <= 0 ||

sys/dev/pci/drm/i915/display/intel_dp.c

2539

limits->pipe.min_bpp > limits->pipe.max_bpp) {

sys/dev/pci/drm/i915/display/intel_dp.c

2558

struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp.c

2565

limits->min_rate = intel_dp_min_link_rate(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2566

limits->max_rate = intel_dp_max_link_rate(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2568

limits->min_rate = min(limits->min_rate, limits->max_rate);

sys/dev/pci/drm/i915/display/intel_dp.c

2570

limits->min_lane_count = intel_dp_min_lane_count(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2571

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

sys/dev/pci/drm/i915/display/intel_dp.c

2573

limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);

sys/dev/pci/drm/i915/display/intel_dp.c

2583

limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);

sys/dev/pci/drm/i915/display/intel_dp.c

2585

limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,

sys/dev/pci/drm/i915/display/intel_dp.c

2591

limits->pipe.max_bpp >= 30)

sys/dev/pci/drm/i915/display/intel_dp.c

2592

limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30);

sys/dev/pci/drm/i915/display/intel_dp.c

2597

limits->pipe.min_bpp, limits->pipe.max_bpp,

sys/dev/pci/drm/i915/display/intel_dp.c

2602

if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits))

sys/dev/pci/drm/i915/display/intel_dp.c

2617

limits->min_lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp.c

2618

limits->min_rate = limits->max_rate;

sys/dev/pci/drm/i915/display/intel_dp.c

2621

intel_dp_test_compute_config(intel_dp, crtc_state, limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2627

limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2667

struct link_config_limits limits;

sys/dev/pci/drm/i915/display/intel_dp.c

2688

&limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2696

conn_state, &limits);

sys/dev/pci/drm/i915/display/intel_dp.c

2722

&limits))

sys/dev/pci/drm/i915/display/intel_dp.c

2726

conn_state, &limits, 64);

sys/dev/pci/drm/i915/display/intel_dp.h

200

struct link_config_limits *limits);

sys/dev/pci/drm/i915/display/intel_dp.h

78

const struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

444

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

446

crtc_state->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

447

crtc_state->port_clock = limits->max_rate;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

454

limits->link.min_bpp_x16,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

455

limits->link.max_bpp_x16,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

462

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

472

max_bpp = limits->pipe.max_bpp;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

473

min_bpp = limits->pipe.min_bpp;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

495

min_compressed_bpp_x16 = limits->link.min_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

496

max_compressed_bpp_x16 = limits->link.max_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

510

crtc_state->lane_count = limits->max_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

511

crtc_state->port_clock = limits->max_rate;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

529

const struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

540

if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

556

struct link_config_limits *limits,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

561

int min_bpp_x16 = limits->link.min_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

563

if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

580

if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

583

limits->link.min_bpp_x16 = fxp_q4_from_int(24);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

588

drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

590

if (limits->max_rate < 540000)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

592

else if (limits->max_rate < 810000)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

595

if (limits->link.min_bpp_x16 >= min_bpp_x16)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

604

if (limits->link.max_bpp_x16 < min_bpp_x16)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

607

limits->link.min_bpp_x16 = min_bpp_x16;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

617

struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

624

limits))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

630

limits,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

646

struct link_config_limits limits;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

672

pipe_config, false, &limits);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

676

conn_state, &limits);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

699

&limits))

sys/dev/pci/drm/i915/display/intel_dp_mst.c

715

conn_state, &limits);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

720

conn_state, &limits,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

816

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

841

limits->force_fec_pipes |= mst_pipe_mask;

sys/dev/pci/drm/i915/display/intel_dp_mst.c

852

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

864

ret = intel_link_bw_reduce_bpp(state, limits,

sys/dev/pci/drm/i915/display/intel_dp_mst.c

889

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_mst.c

897

ret = intel_dp_mst_check_fec_change(state, mgr, limits);

sys/dev/pci/drm/i915/display/intel_dp_mst.c

902

limits);

sys/dev/pci/drm/i915/display/intel_dp_mst.h

28

struct intel_link_bw_limits *limits);

sys/dev/pci/drm/i915/display/intel_dp_test.c

33

struct link_config_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_test.c

41

limits->pipe.min_bpp = bpp;

sys/dev/pci/drm/i915/display/intel_dp_test.c

42

limits->pipe.max_bpp = bpp;

sys/dev/pci/drm/i915/display/intel_dp_test.c

61

limits->min_rate = intel_dp->compliance.test_link_rate;

sys/dev/pci/drm/i915/display/intel_dp_test.c

62

limits->max_rate = intel_dp->compliance.test_link_rate;

sys/dev/pci/drm/i915/display/intel_dp_test.c

64

limits->min_lane_count = intel_dp->compliance.test_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_test.c

65

limits->max_lane_count = intel_dp->compliance.test_lane_count;

sys/dev/pci/drm/i915/display/intel_dp_test.h

18

struct link_config_limits *limits);

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

667

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.c

677

err = intel_link_bw_reduce_bpp(state, limits,

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

107

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_dp_tunnel.h

49

struct intel_link_bw_limits *limits);

sys/dev/pci/drm/i915/display/intel_fdi.c

330

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_fdi.c

341

ret = intel_link_bw_reduce_bpp(state, limits,

sys/dev/pci/drm/i915/display/intel_fdi.c

367

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_fdi.c

381

ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);

sys/dev/pci/drm/i915/display/intel_fdi.h

26

struct intel_link_bw_limits *limits);

sys/dev/pci/drm/i915/display/intel_link_bw.c

100

struct intel_link_bw_limits *limits,

sys/dev/pci/drm/i915/display/intel_link_bw.c

114

if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))

sys/dev/pci/drm/i915/display/intel_link_bw.c

146

limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1;

sys/dev/pci/drm/i915/display/intel_link_bw.c

153

struct intel_link_bw_limits *limits,

sys/dev/pci/drm/i915/display/intel_link_bw.c

160

ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, false);

sys/dev/pci/drm/i915/display/intel_link_bw.c

162

ret = __intel_link_bw_reduce_bpp(state, limits, pipe_mask, reason, true);

sys/dev/pci/drm/i915/display/intel_link_bw.c

240

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_link_bw.c

245

ret = intel_dp_mst_atomic_check_link(state, limits);

sys/dev/pci/drm/i915/display/intel_link_bw.c

249

ret = intel_dp_tunnel_atomic_check_link(state, limits);

sys/dev/pci/drm/i915/display/intel_link_bw.c

253

ret = intel_fdi_atomic_check_link(state, limits);

sys/dev/pci/drm/i915/display/intel_link_bw.c

53

struct intel_link_bw_limits *limits)

sys/dev/pci/drm/i915/display/intel_link_bw.c

58

limits->force_fec_pipes = 0;

sys/dev/pci/drm/i915/display/intel_link_bw.c

59

limits->bpp_limit_reached_pipes = 0;

sys/dev/pci/drm/i915/display/intel_link_bw.c

67

limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16;

sys/dev/pci/drm/i915/display/intel_link_bw.c

69

limits->force_fec_pipes |= BIT(pipe);

sys/dev/pci/drm/i915/display/intel_link_bw.c

71

limits->max_bpp_x16[pipe] = INT_MAX;

sys/dev/pci/drm/i915/display/intel_link_bw.c

75

limits->max_bpp_x16[pipe] = min(limits->max_bpp_x16[pipe], forced_bpp_x16);

sys/dev/pci/drm/i915/display/intel_link_bw.h

25

struct intel_link_bw_limits *limits);

sys/dev/pci/drm/i915/display/intel_link_bw.h

27

struct intel_link_bw_limits *limits,

sys/dev/pci/drm/i915/gt/intel_rps.c

658

u32 limits;

sys/dev/pci/drm/i915/gt/intel_rps.c

669

limits = rps->max_freq_softlimit << 23;

sys/dev/pci/drm/i915/gt/intel_rps.c

671

limits |= rps->min_freq_softlimit << 14;

sys/dev/pci/drm/i915/gt/intel_rps.c

673

limits = rps->max_freq_softlimit << 24;

sys/dev/pci/drm/i915/gt/intel_rps.c

675

limits |= rps->min_freq_softlimit << 16;

sys/dev/pci/drm/i915/gt/intel_rps.c

678

return limits;

sys/dev/pci/drm/radeon/ci_dpm.c

2336

const struct radeon_phase_shedding_limits_table *limits,

sys/dev/pci/drm/radeon/ci_dpm.c

2344

for (i = 0; i < limits->count; i++) {

sys/dev/pci/drm/radeon/ci_dpm.c

2345

if (sclk < limits->entries[i].sclk) {

sys/dev/pci/drm/radeon/ci_dpm.c

2353

const struct radeon_phase_shedding_limits_table *limits,

sys/dev/pci/drm/radeon/ci_dpm.c

2361

for (i = 0; i < limits->count; i++) {

sys/dev/pci/drm/radeon/ci_dpm.c

2362

if (mclk < limits->entries[i].mclk) {

sys/dev/pci/drm/radeon/pptable.h

626

ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits;

sys/dev/pci/drm/radeon/pptable.h

644

ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits;

sys/dev/pci/drm/radeon/r600_dpm.c

1075

ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =

sys/dev/pci/drm/radeon/r600_dpm.c

1085

1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record)));

sys/dev/pci/drm/radeon/r600_dpm.c

1089

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1098

limits->numEntries;

sys/dev/pci/drm/radeon/r600_dpm.c

1099

entry = &limits->entries[0];

sys/dev/pci/drm/radeon/r600_dpm.c

1101

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/radeon/r600_dpm.c

1137

ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =

sys/dev/pci/drm/radeon/r600_dpm.c

1143

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1152

limits->numEntries;

sys/dev/pci/drm/radeon/r600_dpm.c

1153

entry = &limits->entries[0];

sys/dev/pci/drm/radeon/r600_dpm.c

1154

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/radeon/r600_dpm.c

1170

ATOM_PPLIB_SAMClk_Voltage_Limit_Table *limits =

sys/dev/pci/drm/radeon/r600_dpm.c

1175

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1184

limits->numEntries;

sys/dev/pci/drm/radeon/r600_dpm.c

1185

entry = &limits->entries[0];

sys/dev/pci/drm/radeon/r600_dpm.c

1186

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/radeon/r600_dpm.c

1228

ATOM_PPLIB_ACPClk_Voltage_Limit_Table *limits =

sys/dev/pci/drm/radeon/r600_dpm.c

1233

u32 size = limits->numEntries *

sys/dev/pci/drm/radeon/r600_dpm.c

1242

limits->numEntries;

sys/dev/pci/drm/radeon/r600_dpm.c

1243

entry = &limits->entries[0];

sys/dev/pci/drm/radeon/r600_dpm.c

1244

for (i = 0; i < limits->numEntries; i++) {

sys/dev/pci/drm/radeon/si_dpm.c

3837

const struct radeon_phase_shedding_limits_table *limits)

sys/dev/pci/drm/radeon/si_dpm.c

3841

if ((table == NULL) || (limits == NULL))

sys/dev/pci/drm/radeon/si_dpm.c

3856

if (limits->count != (num_levels - 1))

sys/dev/pci/drm/radeon/si_dpm.c

4152

const struct radeon_phase_shedding_limits_table *limits,

sys/dev/pci/drm/radeon/si_dpm.c

4158

for (i = 0; i < limits->count; i++) {

sys/dev/pci/drm/radeon/si_dpm.c

4159

if ((voltage <= limits->entries[i].voltage) &&

sys/dev/pci/drm/radeon/si_dpm.c

4160

(sclk <= limits->entries[i].sclk) &&

sys/dev/pci/drm/radeon/si_dpm.c

4161

(mclk <= limits->entries[i].mclk))

sys/dev/pci/if_iwn.c

4408

calib->ofdm_x1 = sc->limits->min_ofdm_x1;

sys/dev/pci/if_iwn.c

4409

calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;

sys/dev/pci/if_iwn.c

4410

calib->ofdm_x4 = sc->limits->min_ofdm_x4;

sys/dev/pci/if_iwn.c

4411

calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;

sys/dev/pci/if_iwn.c

4413

calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;

sys/dev/pci/if_iwn.c

4414

calib->energy_cck = sc->limits->energy_cck;

sys/dev/pci/if_iwn.c

4603

const struct iwn_sensitivity_limits *limits = sc->limits;

sys/dev/pci/if_iwn.c

4626

inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);

sys/dev/pci/if_iwn.c

4627

inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);

sys/dev/pci/if_iwn.c

4628

inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);

sys/dev/pci/if_iwn.c

4629

inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);

sys/dev/pci/if_iwn.c

4634

dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);

sys/dev/pci/if_iwn.c

4635

dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);

sys/dev/pci/if_iwn.c

4636

dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);

sys/dev/pci/if_iwn.c

4637

dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);

sys/dev/pci/if_iwn.c

4693

inc(calib->cck_x4, 3, limits->max_cck_x4);

sys/dev/pci/if_iwn.c

4695

inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);

sys/dev/pci/if_iwn.c

4706

inc(calib->energy_cck, 2, limits->min_energy_cck);

sys/dev/pci/if_iwn.c

4707

dec(calib->cck_x4, 3, limits->min_cck_x4);

sys/dev/pci/if_iwn.c

4708

dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);

sys/dev/pci/if_iwn.c

4744

cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);

sys/dev/pci/if_iwn.c

614

sc->limits = &iwn4965_sensitivity_limits;

sys/dev/pci/if_iwn.c

657

sc->limits = &iwn5000_sensitivity_limits;

sys/dev/pci/if_iwn.c

664

sc->limits = &iwn5150_sensitivity_limits;

sys/dev/pci/if_iwn.c

669

sc->limits = &iwn5000_sensitivity_limits;

sys/dev/pci/if_iwn.c

673

sc->limits = &iwn1000_sensitivity_limits;

sys/dev/pci/if_iwn.c

677

sc->limits = &iwn6000_sensitivity_limits;

sys/dev/pci/if_iwn.c

688

sc->limits = &iwn6000_sensitivity_limits;

sys/dev/pci/if_iwn.c

692

sc->limits = &iwn6000_sensitivity_limits;

sys/dev/pci/if_iwn.c

701

sc->limits = &iwn2000_sensitivity_limits;

sys/dev/pci/if_iwn.c

706

sc->limits = &iwn2000_sensitivity_limits;

sys/dev/pci/if_iwn.c

710

sc->limits = &iwn2000_sensitivity_limits;

sys/dev/pci/if_iwn.c

715

sc->limits = &iwn2000_sensitivity_limits;

sys/dev/pci/if_iwnvar.h

224

*limits;

usr.bin/ssh/sftp-client.c

545

struct sftp_limits limits;

usr.bin/ssh/sftp-client.c

546

if (sftp_get_limits(ret, &limits) != 0)

usr.bin/ssh/sftp-client.c

551

ret->download_buflen = MINIMUM(limits.read_length,

usr.bin/ssh/sftp-client.c

553

ret->upload_buflen = MINIMUM(limits.write_length,

usr.bin/ssh/sftp-client.c

559

(unsigned long long)limits.write_length,

usr.bin/ssh/sftp-client.c

560

(unsigned long long)limits.read_length,

usr.bin/ssh/sftp-client.c

597

sftp_get_limits(struct sftp_conn *conn, struct sftp_limits *limits)

usr.bin/ssh/sftp-client.c

638

memset(limits, 0, sizeof(*limits));

usr.bin/ssh/sftp-client.c

639

if ((r = sshbuf_get_u64(msg, &limits->packet_length)) != 0 ||

usr.bin/ssh/sftp-client.c

640

(r = sshbuf_get_u64(msg, &limits->read_length)) != 0 ||

usr.bin/ssh/sftp-client.c

641

(r = sshbuf_get_u64(msg, &limits->write_length)) != 0 ||

usr.bin/ssh/sftp-client.c

642

(r = sshbuf_get_u64(msg, &limits->open_handles)) != 0)

usr.sbin/sensorsd/sensorsd.c

234

TAILQ_INIT(&sdlim->limits);

usr.sbin/sensorsd/sensorsd.c

250

TAILQ_INSERT_TAIL(&sdlim->limits, limit, entries);

usr.sbin/sensorsd/sensorsd.c

263

while ((limit = TAILQ_FIRST(&sdlim->limits)) != NULL) {

usr.sbin/sensorsd/sensorsd.c

264

TAILQ_REMOVE(&sdlim->limits, limit, entries);

usr.sbin/sensorsd/sensorsd.c

359

TAILQ_FOREACH(limit, &sdlim->limits, entries) {

usr.sbin/sensorsd/sensorsd.c

444

TAILQ_FOREACH(limit, &sdlim->limits, entries) {

usr.sbin/sensorsd/sensorsd.c

738

TAILQ_FOREACH(p, &sdlim->limits, entries) {

usr.sbin/sensorsd/sensorsd.c

76

TAILQ_HEAD(, limits_t) limits;

usr.sbin/smtpd/config.c

109

limit_mta_set_defaults(limits);

usr.sbin/smtpd/config.c

111

dict_xset(conf->sc_limits_dict, "default", limits);

usr.sbin/smtpd/config.c

149

free(limits);

usr.sbin/smtpd/config.c

36

struct mta_limits *limits = NULL;

usr.sbin/smtpd/config.c

83

limits = calloc(1, sizeof(*limits));

usr.sbin/smtpd/config.c

97

limits == NULL)

usr.sbin/smtpd/limit.c

100

limits->task_lowat = value;

usr.sbin/smtpd/limit.c

102

limits->task_release = value;

usr.sbin/smtpd/limit.c

24

limit_mta_set_defaults(struct mta_limits *limits)

usr.sbin/smtpd/limit.c

26

limits->maxconn_per_host = 10;

usr.sbin/smtpd/limit.c

27

limits->maxconn_per_route = 5;

usr.sbin/smtpd/limit.c

28

limits->maxconn_per_source = 100;

usr.sbin/smtpd/limit.c

29

limits->maxconn_per_connector = 20;

usr.sbin/smtpd/limit.c

30

limits->maxconn_per_relay = 100;

usr.sbin/smtpd/limit.c

31

limits->maxconn_per_domain = 100;

usr.sbin/smtpd/limit.c

33

limits->conndelay_host = 0;

usr.sbin/smtpd/limit.c

34

limits->conndelay_route = 5;

usr.sbin/smtpd/limit.c

35

limits->conndelay_source = 0;

usr.sbin/smtpd/limit.c

36

limits->conndelay_connector = 0;

usr.sbin/smtpd/limit.c

37

limits->conndelay_relay = 2;

usr.sbin/smtpd/limit.c

38

limits->conndelay_domain = 0;

usr.sbin/smtpd/limit.c

40

limits->discdelay_route = 3;

usr.sbin/smtpd/limit.c

42

limits->max_mail_per_session = 100;

usr.sbin/smtpd/limit.c

43

limits->sessdelay_transaction = 0;

usr.sbin/smtpd/limit.c

44

limits->sessdelay_keepalive = 10;

usr.sbin/smtpd/limit.c

46

limits->max_failures_per_session = 25;

usr.sbin/smtpd/limit.c

48

limits->family = AF_UNSPEC;

usr.sbin/smtpd/limit.c

50

limits->task_hiwat = 50;

usr.sbin/smtpd/limit.c

51

limits->task_lowat = 30;

usr.sbin/smtpd/limit.c

52

limits->task_release = 10;

usr.sbin/smtpd/limit.c

56

limit_mta_set(struct mta_limits *limits, const char *key, int64_t value)

usr.sbin/smtpd/limit.c

59

limits->maxconn_per_host = value;

usr.sbin/smtpd/limit.c

61

limits->maxconn_per_route = value;

usr.sbin/smtpd/limit.c

63

limits->maxconn_per_source = value;

usr.sbin/smtpd/limit.c

65

limits->maxconn_per_connector = value;

usr.sbin/smtpd/limit.c

67

limits->maxconn_per_relay = value;

usr.sbin/smtpd/limit.c

69

limits->maxconn_per_domain = value;

usr.sbin/smtpd/limit.c

72

limits->conndelay_host = value;

usr.sbin/smtpd/limit.c

74

limits->conndelay_route = value;

usr.sbin/smtpd/limit.c

76

limits->conndelay_source = value;

usr.sbin/smtpd/limit.c

78

limits->conndelay_connector = value;

usr.sbin/smtpd/limit.c

80

limits->conndelay_relay = value;

usr.sbin/smtpd/limit.c

82

limits->conndelay_domain = value;

usr.sbin/smtpd/limit.c

85

limits->discdelay_route = value;

usr.sbin/smtpd/limit.c

88

limits->max_mail_per_session = value;

usr.sbin/smtpd/limit.c

90

limits->sessdelay_transaction = value;

usr.sbin/smtpd/limit.c

92

limits->sessdelay_keepalive = value;

usr.sbin/smtpd/limit.c

95

limits->max_failures_per_session = value;

usr.sbin/smtpd/limit.c

98

limits->task_hiwat = value;

usr.sbin/smtpd/mta.c

1229

struct mta_limits *l = c->relay->limits;

usr.sbin/smtpd/mta.c

1230

int limits;

usr.sbin/smtpd/mta.c

1268

limits = 0;

usr.sbin/smtpd/mta.c

1279

limits |= CONNECTOR_LIMIT_DOMAIN;

usr.sbin/smtpd/mta.c

1290

limits |= CONNECTOR_LIMIT_SOURCE;

usr.sbin/smtpd/mta.c

1301

limits |= CONNECTOR_LIMIT_CONN;

usr.sbin/smtpd/mta.c

1312

limits |= CONNECTOR_LIMIT_RELAY;

usr.sbin/smtpd/mta.c

1316

if (!limits && nextconn <= now)

usr.sbin/smtpd/mta.c

1317

route = mta_find_route(c, now, &limits, &nextconn, &mx);

usr.sbin/smtpd/mta.c

1330

else if (limits) {

usr.sbin/smtpd/mta.c

1490

if (r->limits == NULL)

usr.sbin/smtpd/mta.c

1592

mta_find_route(struct mta_connector *c, time_t now, int *limits,

usr.sbin/smtpd/mta.c

1596

struct mta_limits *l = c->relay->limits;

usr.sbin/smtpd/mta.c

1753

*limits |= CONNECTOR_LIMIT_ROUTE;

usr.sbin/smtpd/mta.c

1757

*limits |= CONNECTOR_LIMIT_HOST;

usr.sbin/smtpd/mta.c

662

if (relay->ntask == (size_t)relay->limits->task_lowat) {

usr.sbin/smtpd/mta.c

671

m_add_int(p_queue, relay->limits->task_release);

usr.sbin/smtpd/mta.c

745

if (relay->limits &&

usr.sbin/smtpd/mta.c

746

relay->ntask >= (size_t)relay->limits->task_hiwat) {

usr.sbin/smtpd/mta.c

949

relay->limits = dict_get(env->sc_limits_dict, relay->domain->name);

usr.sbin/smtpd/mta.c

950

if (relay->limits == NULL)

usr.sbin/smtpd/mta.c

951

relay->limits = dict_get(env->sc_limits_dict, "default");

usr.sbin/smtpd/mta.c

953

if (max_seen_conndelay_route < relay->limits->conndelay_route)

usr.sbin/smtpd/mta.c

954

max_seen_conndelay_route = relay->limits->conndelay_route;

usr.sbin/smtpd/mta.c

955

if (max_seen_discdelay_route < relay->limits->discdelay_route)

usr.sbin/smtpd/mta.c

956

max_seen_discdelay_route = relay->limits->discdelay_route;

usr.sbin/smtpd/mta_session.c

1076

if (s->relay->limits->max_failures_per_session &&

usr.sbin/smtpd/mta_session.c

1077

s->failures == s->relay->limits->max_failures_per_session) {

usr.sbin/smtpd/mta_session.c

1160

if (s->relay->limits->sessdelay_transaction) {

usr.sbin/smtpd/mta_session.c

1162

(long long)s->relay->limits->sessdelay_transaction);

usr.sbin/smtpd/mta_session.c

1163

s->hangon = s->relay->limits->sessdelay_transaction -1;

usr.sbin/smtpd/mta_session.c

1166

s->relay->limits->sessdelay_transaction, s);

usr.sbin/smtpd/mta_session.c

1180

if (s->relay->limits->sessdelay_transaction) {

usr.sbin/smtpd/mta_session.c

1182

(long long)s->relay->limits->sessdelay_transaction);

usr.sbin/smtpd/mta_session.c

1183

s->hangon = s->relay->limits->sessdelay_transaction -1;

usr.sbin/smtpd/mta_session.c

1186

s->relay->limits->sessdelay_transaction, s);

usr.sbin/smtpd/mta_session.c

715

if (s->msgcount >= s->relay->limits->max_mail_per_session) {

usr.sbin/smtpd/mta_session.c

739

s->hangon >= s->relay->limits->sessdelay_keepalive) {

usr.sbin/smtpd/mta_session.c

745

(long long)(s->relay->limits->sessdelay_keepalive -

usr.sbin/smtpd/parse.y

2094

limits->family = AF_INET;

usr.sbin/smtpd/parse.y

2097

limits->family = AF_INET6;

usr.sbin/smtpd/parse.y

2100

if (!limit_mta_set(limits, $1, $2)) {

usr.sbin/smtpd/parse.y

377

limits = dict_get(conf->sc_limits_dict, $5);

usr.sbin/smtpd/parse.y

378

if (limits == NULL) {

usr.sbin/smtpd/parse.y

379

limits = xcalloc(1, sizeof(*limits));

usr.sbin/smtpd/parse.y

380

dict_xset(conf->sc_limits_dict, $5, limits);

usr.sbin/smtpd/parse.y

382

memmove(limits, d, sizeof(*limits));

usr.sbin/smtpd/parse.y

387

limits = dict_get(conf->sc_limits_dict, "default");

usr.sbin/smtpd/parse.y

90

struct mta_limits *limits;

usr.sbin/smtpd/smtpd.h

802

struct mta_limits *limits;