bin/chio/parse.y
156
kw_cmp(const void *k, const void *e)
bin/chio/parse.y
158
return (strcmp(k, ((const struct keywords *)e)->k_name));
bin/csh/misc.c
244
int k = dup(i);
bin/csh/misc.c
246
if (k < 0)
bin/csh/misc.c
248
if (j == -1 && k > 2)
bin/csh/misc.c
249
return (k);
bin/csh/misc.c
250
if (k != j) {
bin/csh/misc.c
251
j = renum(k, j);
bin/csh/misc.c
252
(void) close(k);
bin/csh/misc.c
255
return (k);
bin/ed/ed.h
81
#define INC_MOD(l, k) ((l) + 1 > (k) ? 0 : (l) + 1)
bin/ed/ed.h
82
#define DEC_MOD(l, k) ((l) - 1 < 0 ? (k) : (l) - 1)
bin/ed/sub.c
241
int k = 0;
bin/ed/sub.c
248
k = rm[0].rm_eo;
bin/ed/sub.c
249
REALLOC(rbuf, rbufsz, off + k - j, ERR);
bin/ed/sub.c
250
while (j < k)
bin/ed/sub.c
255
k = rm[n].rm_eo;
bin/ed/sub.c
256
REALLOC(rbuf, rbufsz, off + k - j, ERR);
bin/ed/sub.c
257
while (j < k)
bin/ksh/emacs.c
1296
struct kb_entry *k;
bin/ksh/emacs.c
1298
TAILQ_FOREACH(k, &kblist, entry) {
bin/ksh/emacs.c
1299
if (len > k->len)
bin/ksh/emacs.c
1302
if (memcmp(k->seq, s, len) == 0)
bin/ksh/emacs.c
1310
kb_del(struct kb_entry *k)
bin/ksh/emacs.c
1312
TAILQ_REMOVE(&kblist, k, entry);
bin/ksh/emacs.c
1313
free(k->args);
bin/ksh/emacs.c
1314
afree(k, AEDIT);
bin/ksh/emacs.c
1321
struct kb_entry *k;
bin/ksh/emacs.c
1339
k = alloc(sizeof *k + count + 1, AEDIT);
bin/ksh/emacs.c
1340
k->seq = (unsigned char *)(k + 1);
bin/ksh/emacs.c
1341
k->len = count;
bin/ksh/emacs.c
1342
k->ftab = xf;
bin/ksh/emacs.c
1343
k->args = args ? strdup(args) : NULL;
bin/ksh/emacs.c
1345
strlcpy(k->seq, str, count + 1);
bin/ksh/emacs.c
1347
TAILQ_INSERT_TAIL(&kblist, k, entry);
bin/ksh/emacs.c
1349
return (k);
bin/ksh/emacs.c
1374
kb_print(struct kb_entry *k)
bin/ksh/emacs.c
1376
if (!(k->ftab->xf_flags & XF_NOBIND))
bin/ksh/emacs.c
1378
kb_decode(k->seq), k->ftab->xf_name);
bin/ksh/emacs.c
1379
else if (k->args) {
bin/ksh/emacs.c
1380
shprintf("%s = ", kb_decode(k->seq));
bin/ksh/emacs.c
1381
shprintf("'%s'\n", kb_decode(k->args));
bin/ksh/emacs.c
1391
struct kb_entry *k, *kb;
bin/ksh/emacs.c
1413
TAILQ_FOREACH(k, &kblist, entry)
bin/ksh/emacs.c
1414
kb_print(k);
bin/ksh/emacs.c
1421
TAILQ_FOREACH(k, &kblist, entry)
bin/ksh/emacs.c
1422
if (!strcmp(k->seq, in)) {
bin/ksh/emacs.c
1423
kb_print(k);
bin/ksh/emacs.c
1432
TAILQ_FOREACH_SAFE(k, &kblist, entry, kb)
bin/ksh/emacs.c
1433
if (!strcmp(k->seq, in)) {
bin/ksh/emacs.c
1434
kb_del(k);
bin/ksh/emacs.c
1443
TAILQ_FOREACH_SAFE(k, &kblist, entry, kb)
bin/ksh/emacs.c
1444
if (!strcmp(k->seq, in)) {
bin/ksh/emacs.c
1445
kb_del(k);
bin/ksh/emacs.c
1458
TAILQ_FOREACH_SAFE(k, &kblist, entry, kb)
bin/ksh/emacs.c
1459
if (!strcmp(k->seq, in)) {
bin/ksh/emacs.c
1460
kb_del(k);
bin/ksh/emacs.c
277
struct kb_entry *k, *kmatch = NULL;
bin/ksh/emacs.c
335
TAILQ_FOREACH(k, &kblist, entry) {
bin/ksh/emacs.c
336
if (at > k->len)
bin/ksh/emacs.c
339
if (memcmp(k->seq, line, at) == 0) {
bin/ksh/emacs.c
342
if (k->len == at)
bin/ksh/emacs.c
343
kmatch = k;
bin/ksh/emacs.c
865
struct kb_entry *k;
bin/ksh/emacs.c
870
TAILQ_FOREACH(k, &kblist, entry)
bin/ksh/emacs.c
871
if (!strcmp(k->seq, line))
bin/ksh/emacs.c
872
return (k->ftab->xf_func);
bin/ps/ps.c
449
#define VSIZE(k) ((k)->p_vm_dsize + (k)->p_vm_ssize + (k)->p_vm_tsize)
games/adventure/done.c
120
k = cval[i] + 1 - sc;
games/adventure/done.c
122
printf(" %d more point", k);
games/adventure/done.c
123
if (k == 1)
games/adventure/done.c
159
k = oldlc2;
games/adventure/done.c
161
k = 1;
games/adventure/done.c
162
drop(i, k);
games/adventure/done.c
55
k = 12;
games/adventure/done.c
57
k = 14;
games/adventure/done.c
59
k = 16;
games/adventure/done.c
63
scor += k - 2;
games/adventure/done.c
64
mxscor += k;
games/adventure/hdr.h
69
extern int loc, newloc, oldloc, oldlc2, wzdark, gaveup, kq, k, k2;
games/adventure/init.c
110
keys = vocab(DECR(k,e,y,s,\0), 1, 0);
games/adventure/init.c
120
snake = vocab(DECR(s,n,a,k,e), 1, 0);
games/adventure/init.c
127
knife = vocab(DECR(k,n,i,f,e), 1, 0);
games/adventure/init.c
157
back = vocab(DECR(b,a,c,k,\0),0, 0);
games/adventure/init.c
158
look = vocab(DECR(l,o,o,k,\0),0, 0);
games/adventure/init.c
167
lock = vocab(DECR(l,o,c,k,\0),2, 0);
games/adventure/main.c
133
k = null;
games/adventure/main.c
174
k = 1;
games/adventure/main.c
204
l2009: k = 54; /* 2009 */
games/adventure/main.c
205
l2010: spk = k;
games/adventure/main.c
285
l19999: k = 43;
games/adventure/main.c
287
k = 70;
games/adventure/main.c
312
k = i % 1000;
games/adventure/main.c
336
l4000: verb = k;
games/adventure/main.c
424
k = vocab(wd1, 3, 0);
games/adventure/main.c
426
if (foobar == 1 - k)
games/adventure/main.c
431
l8252: foobar = k;
games/adventure/main.c
432
if (k != 4)
games/adventure/main.c
439
k = 2;
games/adventure/main.c
441
k = 1;
games/adventure/main.c
443
k = 0;
games/adventure/main.c
445
pspeak(eggs, k);
games/adventure/main.c
52
int loc, newloc, oldloc, oldlc2, wzdark, gaveup, kq, k, k2;
games/adventure/main.c
585
k = null;
games/adventure/main.c
621
|| k == liqloc(loc))
games/adventure/main.c
693
obj = k;
games/adventure/main.c
694
if (fixed[k] != loc && !here(k))
games/adventure/main.c
702
l5100: if (k != grate)
games/adventure/main.c
705
k = dprssn;
games/adventure/main.c
707
k = entrnc;
games/adventure/main.c
708
if (k != grate)
games/adventure/main.c
710
l5110: if (k != dwarf)
games/adventure/main.c
715
l5120: if ((liq() == k && here(bottle)) || k == liqloc(loc))
games/adventure/save.c
72
{&k, sizeof(k)},
games/adventure/subr.c
203
k = 0;
games/adventure/subr.c
211
k = 1;
games/adventure/subr.c
213
if (tally == tally2 + 1 && k == 0 && place[chest] == 0
games/adventure/subr.c
265
k = 6;
games/adventure/subr.c
267
rspeak(k + stick);
games/adventure/subr.c
276
k = 52;
games/adventure/subr.c
288
if (k == null)
games/adventure/subr.c
290
if (k == cave) { /* 40 */
games/adventure/subr.c
297
if (k == look) { /* 30 */
games/adventure/subr.c
304
if (k == back) { /* 20 */
games/adventure/subr.c
315
if (tkk->tverb == 1 || tkk->tverb == k)
games/adventure/subr.c
324
k = newloc % 100; /* k used for prob */
games/adventure/subr.c
343
if (toting(k) || (newloc > 200 && at(k)))
games/adventure/subr.c
347
if (prop[k] != (newloc / 100) - 3)
games/adventure/subr.c
365
if (forced(k = oldloc))
games/adventure/subr.c
366
k = oldlc2; /* k = location */
games/adventure/subr.c
370
if (k == loc) {
games/adventure/subr.c
376
if (ll == k) {
games/adventure/subr.c
377
k = tkk->tverb; /* k back to verb */
games/adventure/subr.c
383
if (forced(ll) && k == j->tloc)
games/adventure/subr.c
389
k = tkk->tverb;
games/adventure/subr.c
456
if (k >= 43 && k <= 50)
games/adventure/subr.c
458
if (k == 29 || k == 30)
games/adventure/subr.c
460
if (k == 7 || k == 36 || k == 37)
games/adventure/subr.c
462
if (k == 11 || k == 19)
games/adventure/subr.c
466
if (k == 62 || k == 65)
games/adventure/subr.c
468
if (k == 17)
games/adventure/subr.c
600
k = liq();
games/adventure/subr.c
601
if (obj == bottle && k != 0)
games/adventure/subr.c
602
place[k] = -1;
games/adventure/subr.c
610
k = liq();
games/adventure/subr.c
611
if (k == obj)
games/adventure/subr.c
613
if (obj == bottle && k != 0)
games/adventure/subr.c
614
place[k] = 0;
games/adventure/subr.c
680
k = 0; /* 9046 */
games/adventure/subr.c
682
k = 1;
games/adventure/subr.c
683
spk = 124 + k;
games/adventure/subr.c
685
spk = 120 + k;
games/adventure/subr.c
687
spk = 122 + k;
games/adventure/subr.c
739
k = 130;
games/adventure/subr.c
745
k = 34 + prop[grate]; /* 9043 */
games/adventure/subr.c
749
k = k + 2 * prop[grate];
games/adventure/subr.c
823
k = (plac[dragon] + fixd[dragon]) / 2;
games/adventure/subr.c
826
move(dragon, k);
games/adventure/subr.c
827
move(rug, k);
games/adventure/subr.c
830
move(obj, k);
games/adventure/subr.c
831
loc = k;
games/adventure/subr.c
832
k = null;
games/adventure/subr.c
869
k = null;
games/adventure/subr.c
973
k = liq();
games/adventure/subr.c
975
place[k] = -1;
games/adventure/subr.c
976
if (k == oil)
games/backgammon/backgammon/extra.c
194
int i, j, k;
games/backgammon/backgammon/extra.c
207
for (k = 1; k < 7 && k < j; k++)
games/backgammon/backgammon/extra.c
208
if (j - k < 7)
games/backgammon/backgammon/extra.c
209
odds(k, j - k, 1);
games/backgammon/common_source/fancy.c
126
int k; /* index */
games/backgammon/common_source/fancy.c
139
for (k = 0; k < 15; k += 5) /* print men */
games/backgammon/common_source/fancy.c
140
if (n > j + k)
games/backgammon/common_source/fancy.c
41
int i, j, k, l;
games/backgammon/common_source/fancy.c
54
k = (l == 1 ? 1 : 15);
games/backgammon/common_source/fancy.c
55
mvaddch(k, i, '|');
games/backgammon/common_source/fancy.c
57
mvaddch(k += l, i, '|');
games/backgammon/common_source/odds.c
73
int j, k, b;
games/backgammon/common_source/odds.c
93
for (k = 1; k < diff; k++)
games/backgammon/common_source/odds.c
94
if (k < 7 && diff - k < 7 &&
games/backgammon/common_source/odds.c
95
(board[i + a * k] * a >= 0 ||
games/backgammon/common_source/odds.c
96
board[i + a * (diff - k)] >= 0))
games/backgammon/common_source/odds.c
97
odds(k, diff - k, addon);
games/backgammon/teachgammon/tutor.c
40
int i, j, k;
games/backgammon/teachgammon/tutor.c
67
k = 0;
games/backgammon/teachgammon/tutor.c
69
k += (board[j] > 0 ? board[j] : 0);
games/backgammon/teachgammon/tutor.c
70
*inopp = k;
games/backgammon/teachgammon/tutor.c
72
k += (board[j] > 0 ? board[j] : 0);
games/backgammon/teachgammon/tutor.c
73
*offopp = k - 30; /* -15 at start */
games/backgammon/teachgammon/tutor.c
82
getyx(stdscr, j, k);
games/cribbage/cards.c
43
int i, j, k;
games/cribbage/cards.c
45
k = 0;
games/cribbage/cards.c
48
d[k].suit = j;
games/cribbage/cards.c
49
d[k++].rank = i;
games/cribbage/cards.c
60
int j, k;
games/cribbage/cards.c
64
k = arc4random_uniform(j); /* random 0 <= k < j */
games/cribbage/cards.c
66
d[j - 1] = d[k];
games/cribbage/cards.c
67
d[k] = c;
games/cribbage/crib.c
441
int i, j, k;
games/cribbage/crib.c
484
k = 0;
games/cribbage/crib.c
488
if (l > k) {
games/cribbage/crib.c
489
k = l;
games/cribbage/crib.c
499
if (k > 0) {
games/cribbage/crib.c
501
"I get %d points playing ", k);
games/cribbage/crib.c
507
if (chkscr(&cscore, k))
games/cribbage/score.c
101
int i, k;
games/cribbage/score.c
110
k = hand[0].suit;
games/cribbage/score.c
112
flag = (flag && (hand[i].suit == k));
games/cribbage/score.c
125
if (starter.suit == k) {
games/cribbage/score.c
283
int k, lo, hi;
games/cribbage/score.c
305
k = -1;
games/cribbage/score.c
318
k = hi - lo + 1;
games/cribbage/score.c
320
if (k >= 3)
games/cribbage/score.c
321
return (scr + k);
games/cribbage/support.c
236
int i, j, k;
games/cribbage/support.c
254
for (k = 0; k < FULLHAND; k++)
games/cribbage/support.c
255
h[k] = chand[k];
games/cribbage/support.c
258
for (k = 0; k < nc; k++) {
games/cribbage/support.c
260
scorehand(h, d[k], CINHAND, TRUE, FALSE);
games/cribbage/support.c
262
sums[ns] += adjust(cb, d[k]);
games/cribbage/support.c
264
sums[ns] -= adjust(cb, d[k]);
games/cribbage/support.c
273
for (k = 0; k < FULLHAND; k++)
games/cribbage/support.c
274
h[k] = chand[k];
games/grdc/grdc.c
212
for (k = 0; k < 6; k++)
games/grdc/grdc.c
213
old[k] = 0;
games/grdc/grdc.c
219
} else for (k = 0; k < 6; k++) {
games/grdc/grdc.c
223
new[5] = (new[5] & ~mask) | (next[k] & mask);
games/grdc/grdc.c
225
new[k] = (new[k] & ~mask) | (next[k] & mask);
games/grdc/grdc.c
226
next[k] = 0;
games/grdc/grdc.c
248
if (scrol && k <= 4) {
games/grdc/grdc.c
252
- (4 - k) * scroldelay;
games/grdc/grdc.c
72
int i, j, s, k, rv;
games/mille/print.c
46
int i, j, k, temp;
games/mille/print.c
48
for (k = 0; k < 2; k++) {
games/mille/print.c
49
pp = &Player[k];
games/mille/print.c
50
temp = k * COMP_STRT + CARD_STRT;
games/mille/print.c
68
temp = k * 40;
games/sail/dr_3.c
100
for (k = 0; stillmoving(k); k++) {
games/sail/dr_3.c
107
if (!sp->file->movebuf[k])
games/sail/dr_3.c
108
sp->file->movebuf[k+1] = '\0';
games/sail/dr_3.c
110
step(sp->file->movebuf[k], sp, &moved[n]);
games/sail/dr_3.c
143
sp->file->movebuf[k + 1] = 0;
games/sail/dr_3.c
144
sq->file->movebuf[k + 1] = 0;
games/sail/dr_3.c
182
stillmoving(int k)
games/sail/dr_3.c
187
if (sp->file->movebuf[k])
games/sail/dr_3.c
46
int k, l; /* r8, r7 */
games/sail/dr_4.c
40
int k;
games/sail/dr_4.c
43
if ((k = grappled2(from, to)) == 0)
games/sail/dr_4.c
46
while (--k >= 0) {
games/sail/pl_5.c
201
int k, j, men;
games/sail/pl_5.c
205
for (k = 0; k < 3; k++)
games/sail/pl_5.c
206
temp[k] = crew[k];
games/sail/pl_5.c
213
for (k = 0; k < 3 && buf > '0'; k++) {
games/sail/pl_5.c
214
men += crew[k]
games/sail/pl_5.c
215
* (k == 0 ? 100 : (k == 1 ? 10 : 1));
games/sail/pl_5.c
216
crew[k] = 0;
games/sail/pl_5.c
226
for (k=0; k < NBP; k++)
games/sail/pl_5.c
227
if (temp[k] && !crew[k])
games/sail/pl_5.c
228
(void) waddch(slot_w, k + '1');
games/sail/pl_5.c
230
(void) wmove(slot_w, 2, 1 + k);
games/sail/pl_5.c
235
for (k=0; k < NBP; k++)
games/sail/pl_5.c
236
if (temp[k] && !crew[k])
games/sail/pl_5.c
237
(void) waddch(slot_w, k + '1');
games/sail/pl_5.c
239
(void) wmove(slot_w, 0, 1 + k);
games/snake/snake.c
245
int k;
games/snake/snake.c
335
for (k = 1; k <= repeat; k++) {
games/snake/snake.c
345
if ((fast) || (k == 1))
games/snake/snake.c
348
if ((fast) || (k == repeat) ||
games/snake/snake.c
360
if ((fast) || (k == 1))
games/snake/snake.c
363
if ((fast) || (k == repeat) ||
games/snake/snake.c
376
if ((fast) || (k == 1))
games/snake/snake.c
379
if ((fast) || (k == repeat) ||
games/snake/snake.c
394
if ((fast) || (k == 1))
games/snake/snake.c
397
if ((fast) || (k == repeat) ||
games/snake/snake.c
406
if (k < repeat)
games/snake/snake.c
767
int j, k;
games/snake/snake.c
774
for (k = 0; k < j; k++) {
games/snake/snake.c
778
for (k = 0; k < j; k++) {
games/snake/snake.c
783
for (k = 0; k < j; k++) {
games/snake/snake.c
787
for (k = 0; k < j; k++) {
games/tetris/scores.c
259
int i, j, k, nrnames;
games/tetris/scores.c
308
for (k = i; k < num; k++)
games/tetris/scores.c
309
hs[k] = hs[k + 1];
games/trek/capture.c
102
killk(k->x, k->y);
games/trek/capture.c
54
struct kling *k;
games/trek/capture.c
76
k = selectklingon();
games/trek/capture.c
81
k->srndreq++;
games/trek/capture.c
84
x /= k->power * Etc.nkling;
games/trek/capture.c
94
printf("Klingon at %d,%d surrenders\n", k->x, k->y);
games/trek/events.c
372
k = &Etc.klingon[Etc.nkling++];
games/trek/events.c
373
k->x = ix;
games/trek/events.c
374
k->y = iy;
games/trek/events.c
375
k->power = Param.klingpwr;
games/trek/events.c
376
k->srndreq = 0;
games/trek/events.c
54
struct kling *k;
games/trek/klmove.c
107
nextx = k->x;
games/trek/klmove.c
108
nexty = k->y;
games/trek/klmove.c
134
k->x, k->y, qx, qy);
games/trek/klmove.c
142
Sect[k->x][k->y] = EMPTY;
games/trek/klmove.c
145
*k = Etc.klingon[Etc.nkling];
games/trek/klmove.c
147
k = 0;
games/trek/klmove.c
169
if (k && (k->x != nextx || k->y != nexty))
games/trek/klmove.c
173
k->x, k->y, nextx, nexty);
games/trek/klmove.c
174
Sect[k->x][k->y] = EMPTY;
games/trek/klmove.c
175
Sect[k->x = nextx][k->y = nexty] = KLINGON;
games/trek/klmove.c
64
struct kling *k;
games/trek/klmove.c
80
k = &Etc.klingon[n];
games/trek/klmove.c
83
i = 100.0 * k->power / Param.klingpwr;
games/trek/klmove.c
88
motion *= k->avgdist * Param.movefac[2 * Move.newquad + fl];
games/trek/klmove.c
90
dx = Ship.sectx - k->x + ranf(3) - 1;
games/trek/klmove.c
91
dy = Ship.secty - k->y + ranf(3) - 1;
games/trek/phaser.c
226
k = &Etc.klingon[i];
games/trek/phaser.c
228
distfactor = k->dist;
games/trek/phaser.c
231
distfactor = k->power;
games/trek/phaser.c
234
dx = Ship.sectx - k->x;
games/trek/phaser.c
235
dy = k->y - Ship.secty;
games/trek/phaser.c
306
k = Etc.klingon;
games/trek/phaser.c
343
anglefactor = k->dist;
games/trek/phaser.c
346
dx = Ship.sectx - k->x;
games/trek/phaser.c
347
dy = k->y - Ship.secty;
games/trek/phaser.c
352
k++;
games/trek/phaser.c
356
k->power -= hit;
games/trek/phaser.c
359
printf(" at %d,%d", k->x, k->y);
games/trek/phaser.c
362
if (k->power <= 0)
games/trek/phaser.c
364
killk(k->x, k->y);
games/trek/phaser.c
367
k++;
games/trek/phaser.c
89
struct kling *k;
games/trek/torped.c
103
k = ungetc(getchar(), stdin);
games/trek/torped.c
104
if (k >= '0' && k <= '9')
games/trek/torped.c
171
for (k = 0; k < Etc.nkling; k++)
games/trek/torped.c
173
if (Etc.klingon[k].x != ix || Etc.klingon[k].y != iy)
games/trek/torped.c
175
Etc.klingon[k].power -= 500 + ranf(501);
games/trek/torped.c
176
if (Etc.klingon[k].power > 0)
games/trek/torped.c
68
int k;
games/wump/wump.c
567
int i, j, k, link;
games/wump/wump.c
615
for (k = 0; k < j; k++)
games/wump/wump.c
616
if (cave[i].tunnel[k] == link)
games/wump/wump.c
624
for (k = 0; k < link_num; ++k) {
games/wump/wump.c
626
if (cave[link].tunnel[k] == i)
games/wump/wump.c
627
k = link_num;
games/wump/wump.c
630
if (cave[link].tunnel[k] == -1) {
games/wump/wump.c
631
cave[link].tunnel[k] = i;
games/wump/wump.c
632
k = link_num;
lib/libagentx/agentx.c
2794
size_t i, j, k;
lib/libagentx/agentx.c
2953
for (k = 0; k < data->avb_ostring.aos_slen; k++, j++) {
lib/libagentx/agentx.c
2957
data->avb_ostring.aos_string[k] = 0xff;
lib/libagentx/agentx.c
2959
data->avb_ostring.aos_string[k] = '\0';
lib/libagentx/agentx.c
2961
data->avb_ostring.aos_string[k] =
lib/libagentx/agentx.c
2964
data->avb_ostring.aos_string[k] = '\0';
lib/libagentx/agentx.c
2988
for (k = 0; k < data->avb_oid.aoi_idlen; k++, j++) {
lib/libagentx/agentx.c
2990
data->avb_oid.aoi_id[k] = UINT32_MAX;
lib/libagentx/agentx.c
2992
data->avb_oid.aoi_id[k] = 0;
lib/libagentx/agentx.c
2994
data->avb_oid.aoi_id[k] =
lib/libagentx/agentx.c
3009
for (k = 0; k < 4; k++, j++) {
lib/libagentx/agentx.c
3013
ipbytes[k] = 255;
lib/libagentx/agentx.c
3015
ipbytes[k] = 0;
lib/libagentx/agentx.c
3017
ipbytes[k] = oid->aoi_id[j];
lib/libc/arch/sparc64/fpu/fpu_explode.c
257
__fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l)
lib/libc/arch/sparc64/fpu/fpu_explode.c
269
f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
lib/libc/arch/sparc64/fpu/fpu_explode.c
270
f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
lib/libc/arch/sparc64/fpu/fpu_explode.c
272
frac |= j | k | l;
lib/libc/crypt/bcrypt.c
163
for (k = 0; k < rounds; k++) {
lib/libc/crypt/bcrypt.c
174
for (k = 0; k < 64; k++)
lib/libc/crypt/bcrypt.c
96
u_int32_t rounds, i, k;
lib/libc/crypt/blowfish.c
415
u_int16_t k;
lib/libc/crypt/blowfish.c
438
for (k = 0; k < 256; k += 2) {
lib/libc/crypt/blowfish.c
441
c->S[i][k] = datal;
lib/libc/crypt/blowfish.c
442
c->S[i][k + 1] = datar;
lib/libc/crypt/blowfish.c
455
u_int16_t k;
lib/libc/crypt/blowfish.c
480
for (k = 0; k < 256; k += 2) {
lib/libc/crypt/blowfish.c
485
c->S[i][k] = datal;
lib/libc/crypt/blowfish.c
486
c->S[i][k + 1] = datar;
lib/libc/crypt/blowfish.c
494
blf_key(blf_ctx *c, const u_int8_t *k, u_int16_t len)
lib/libc/crypt/blowfish.c
500
Blowfish_expand0state(c, k, len);
lib/libc/crypt/chacha_private.h
55
chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)
lib/libc/crypt/chacha_private.h
59
x->input[4] = U8TO32_LITTLE(k + 0);
lib/libc/crypt/chacha_private.h
60
x->input[5] = U8TO32_LITTLE(k + 4);
lib/libc/crypt/chacha_private.h
61
x->input[6] = U8TO32_LITTLE(k + 8);
lib/libc/crypt/chacha_private.h
62
x->input[7] = U8TO32_LITTLE(k + 12);
lib/libc/crypt/chacha_private.h
64
k += 16;
lib/libc/crypt/chacha_private.h
69
x->input[8] = U8TO32_LITTLE(k + 0);
lib/libc/crypt/chacha_private.h
70
x->input[9] = U8TO32_LITTLE(k + 4);
lib/libc/crypt/chacha_private.h
71
x->input[10] = U8TO32_LITTLE(k + 8);
lib/libc/crypt/chacha_private.h
72
x->input[11] = U8TO32_LITTLE(k + 12);
lib/libc/db/hash/hash.c
848
__call_hash(HTAB *hashp, char *k, int len)
lib/libc/db/hash/hash.c
852
n = hashp->hash(k, len);
lib/libc/db/hash/hash_func.c
44
u_int8_t *k;
lib/libc/db/hash/hash_func.c
46
#define HASH4a h = (h << 5) - h + *k++;
lib/libc/db/hash/hash_func.c
47
#define HASH4b h = (h << 5) + h + *k++;
lib/libc/db/hash/hash_func.c
51
k = (u_int8_t *)key;
lib/libc/gdtoa/dmisc.c
100
b->maxwds = 1 << (b->k = *(int*)b);
lib/libc/gdtoa/dmisc.c
45
int j, k, *r;
lib/libc/gdtoa/dmisc.c
48
for(k = 0;
lib/libc/gdtoa/dmisc.c
51
k++;
lib/libc/gdtoa/dmisc.c
52
r = (int*)Balloc(k);
lib/libc/gdtoa/dmisc.c
59
*r = k;
lib/libc/gdtoa/dtoa.c
119
j, j1, k, k0, k_check, leftright, m2, m5, s2, s5,
lib/libc/gdtoa/dtoa.c
259
k = (int)ds;
lib/libc/gdtoa/dtoa.c
260
if (ds < 0. && ds != k)
lib/libc/gdtoa/dtoa.c
261
k--; /* want k = floor(ds) */
lib/libc/gdtoa/dtoa.c
263
if (k >= 0 && k <= Ten_pmax) {
lib/libc/gdtoa/dtoa.c
264
if (dval(&d) < tens[k])
lib/libc/gdtoa/dtoa.c
265
k--;
lib/libc/gdtoa/dtoa.c
277
if (k >= 0) {
lib/libc/gdtoa/dtoa.c
279
s5 = k;
lib/libc/gdtoa/dtoa.c
280
s2 += k;
lib/libc/gdtoa/dtoa.c
283
b2 -= k;
lib/libc/gdtoa/dtoa.c
284
b5 = -k;
lib/libc/gdtoa/dtoa.c
323
i = ndigits + k + 1;
lib/libc/gdtoa/dtoa.c
344
k0 = k;
lib/libc/gdtoa/dtoa.c
347
if (k > 0) {
lib/libc/gdtoa/dtoa.c
348
ds = tens[k&0xf];
lib/libc/gdtoa/dtoa.c
349
j = k >> 4;
lib/libc/gdtoa/dtoa.c
363
else if (( j1 = -k )!=0) {
lib/libc/gdtoa/dtoa.c
375
k--;
lib/libc/gdtoa/dtoa.c
436
k = k0;
lib/libc/gdtoa/dtoa.c
442
if (be >= 0 && k <= Int_max) {
lib/libc/gdtoa/dtoa.c
444
ds = tens[k];
lib/libc/gdtoa/dtoa.c
486
k++;
lib/libc/gdtoa/dtoa.c
614
k--;
lib/libc/gdtoa/dtoa.c
633
k = -1 - ndigits;
lib/libc/gdtoa/dtoa.c
638
k++;
lib/libc/gdtoa/dtoa.c
654
mhi = Balloc(mhi->k);
lib/libc/gdtoa/dtoa.c
801
k++;
lib/libc/gdtoa/dtoa.c
835
*decpt = k + 1;
lib/libc/gdtoa/gdtoa.c
159
int j, j1, k, k0, k_check, kind, leftright, m2, m5, nbits;
lib/libc/gdtoa/gdtoa.c
248
k = (int)ds;
lib/libc/gdtoa/gdtoa.c
249
if (ds < 0. && ds != k)
lib/libc/gdtoa/gdtoa.c
250
k--; /* want k = floor(ds) */
lib/libc/gdtoa/gdtoa.c
260
if (k >= 0 && k <= Ten_pmax) {
lib/libc/gdtoa/gdtoa.c
261
if (dval(&d) < tens[k])
lib/libc/gdtoa/gdtoa.c
262
k--;
lib/libc/gdtoa/gdtoa.c
274
if (k >= 0) {
lib/libc/gdtoa/gdtoa.c
276
s5 = k;
lib/libc/gdtoa/gdtoa.c
277
s2 += k;
lib/libc/gdtoa/gdtoa.c
280
b2 -= k;
lib/libc/gdtoa/gdtoa.c
281
b5 = -k;
lib/libc/gdtoa/gdtoa.c
314
i = ndigits + k + 1;
lib/libc/gdtoa/gdtoa.c
335
&& k == 0
lib/libc/gdtoa/gdtoa.c
347
k0 = k;
lib/libc/gdtoa/gdtoa.c
350
if (k > 0) {
lib/libc/gdtoa/gdtoa.c
351
ds = tens[k&0xf];
lib/libc/gdtoa/gdtoa.c
352
j = k >> 4;
lib/libc/gdtoa/gdtoa.c
367
if ( (j1 = -k) !=0) {
lib/libc/gdtoa/gdtoa.c
380
k--;
lib/libc/gdtoa/gdtoa.c
41
int i, k;
lib/libc/gdtoa/gdtoa.c
444
k = k0;
lib/libc/gdtoa/gdtoa.c
450
if (be >= 0 && k <= Int_max) {
lib/libc/gdtoa/gdtoa.c
452
ds = tens[k];
lib/libc/gdtoa/gdtoa.c
46
k = 0;
lib/libc/gdtoa/gdtoa.c
49
k++;
lib/libc/gdtoa/gdtoa.c
490
k++;
lib/libc/gdtoa/gdtoa.c
52
if (!k)
lib/libc/gdtoa/gdtoa.c
53
k = 1;
lib/libc/gdtoa/gdtoa.c
55
b = Balloc(k);
lib/libc/gdtoa/gdtoa.c
612
k--;
lib/libc/gdtoa/gdtoa.c
631
k = -1 - ndigits;
lib/libc/gdtoa/gdtoa.c
638
k++;
lib/libc/gdtoa/gdtoa.c
654
mhi = Balloc(mhi->k);
lib/libc/gdtoa/gdtoa.c
801
k++;
lib/libc/gdtoa/gdtoa.c
824
*decpt = k + 1;
lib/libc/gdtoa/gdtoaimp.h
475
int k, maxwds, sign, wds;
lib/libc/gdtoa/gethex.c
190
for(j = n, k = 0; j >>= 1; ++k);
lib/libc/gdtoa/gethex.c
191
*bp = b = Balloc(k);
lib/libc/gdtoa/gethex.c
203
for(k = 0; n > (1 << (kshift-2)) - 1; n >>= 1)
lib/libc/gdtoa/gethex.c
204
k++;
lib/libc/gdtoa/gethex.c
205
b = Balloc(k);
lib/libc/gdtoa/gethex.c
242
k = n - 1;
lib/libc/gdtoa/gethex.c
243
if (x[k>>kshift] & 1 << (k & kmask)) {
lib/libc/gdtoa/gethex.c
245
if (k > 0 && any_on(b,k))
lib/libc/gdtoa/gethex.c
304
k = n - 1;
lib/libc/gdtoa/gethex.c
307
else if (k > 0)
lib/libc/gdtoa/gethex.c
308
lostbits = any_on(b,k);
lib/libc/gdtoa/gethex.c
309
if (x[k>>kshift] & 1 << (k & kmask))
lib/libc/gdtoa/gethex.c
332
k = b->wds;
lib/libc/gdtoa/gethex.c
342
else if (b->wds > k
lib/libc/gdtoa/gethex.c
344
&& hi0bits(x[k-1]) < 32-n)) {
lib/libc/gdtoa/gethex.c
48
int big, esign, havedig, irv, j, k, n, n0, nbits, up, zret;
lib/libc/gdtoa/gmisc.c
36
rshift(b, k) Bigint *b; int k;
lib/libc/gdtoa/gmisc.c
38
rshift(Bigint *b, int k)
lib/libc/gdtoa/gmisc.c
45
n = k >> kshift;
lib/libc/gdtoa/gmisc.c
49
if (k &= kmask) {
lib/libc/gdtoa/gmisc.c
50
n = ULbits - k;
lib/libc/gdtoa/gmisc.c
51
y = *x++ >> k;
lib/libc/gdtoa/gmisc.c
54
y = *x++ >> k;
lib/libc/gdtoa/misc.c
103
if (v->k > Kmax)
lib/libc/gdtoa/misc.c
111
v->next = freelist[v->k];
lib/libc/gdtoa/misc.c
112
freelist[v->k] = v;
lib/libc/gdtoa/misc.c
126
int k;
lib/libc/gdtoa/misc.c
139
k = 0;
lib/libc/gdtoa/misc.c
141
k = 16;
lib/libc/gdtoa/misc.c
145
k += 8;
lib/libc/gdtoa/misc.c
149
k += 4;
lib/libc/gdtoa/misc.c
153
k += 2;
lib/libc/gdtoa/misc.c
157
k++;
lib/libc/gdtoa/misc.c
163
return k;
lib/libc/gdtoa/misc.c
212
b1 = Balloc(b->k+1);
lib/libc/gdtoa/misc.c
233
int k = 0;
lib/libc/gdtoa/misc.c
236
k = 16;
lib/libc/gdtoa/misc.c
240
k += 8;
lib/libc/gdtoa/misc.c
244
k += 4;
lib/libc/gdtoa/misc.c
248
k += 2;
lib/libc/gdtoa/misc.c
252
k++;
lib/libc/gdtoa/misc.c
256
return k;
lib/libc/gdtoa/misc.c
286
int k, wa, wb, wc;
lib/libc/gdtoa/misc.c
303
k = a->k;
lib/libc/gdtoa/misc.c
308
k++;
lib/libc/gdtoa/misc.c
309
c = Balloc(k);
lib/libc/gdtoa/misc.c
394
(b, k) Bigint *b; int k;
lib/libc/gdtoa/misc.c
396
(Bigint *b, int k)
lib/libc/gdtoa/misc.c
403
if ( (i = k & 3) !=0) {
lib/libc/gdtoa/misc.c
409
if (!(k >>= 2))
lib/libc/gdtoa/misc.c
430
if (k & 1) {
lib/libc/gdtoa/misc.c
437
if (!(k >>= 1))
lib/libc/gdtoa/misc.c
464
(b, k) Bigint *b; int k;
lib/libc/gdtoa/misc.c
466
(Bigint *b, int k)
lib/libc/gdtoa/misc.c
473
n = k >> kshift;
lib/libc/gdtoa/misc.c
474
k1 = b->k;
lib/libc/gdtoa/misc.c
486
if (k &= kmask) {
lib/libc/gdtoa/misc.c
488
k1 = 32 - k;
lib/libc/gdtoa/misc.c
491
*x1++ = *x << k | z;
lib/libc/gdtoa/misc.c
498
k1 = 16 - k;
lib/libc/gdtoa/misc.c
50
(k) int k;
lib/libc/gdtoa/misc.c
501
*x1++ = *x << k & 0xffff | z;
lib/libc/gdtoa/misc.c
52
(int k)
lib/libc/gdtoa/misc.c
588
c = Balloc(a->k);
lib/libc/gdtoa/misc.c
64
if (k <= Kmax && (rv = freelist[k]) !=0) {
lib/libc/gdtoa/misc.c
65
freelist[k] = rv->next;
lib/libc/gdtoa/misc.c
658
int k;
lib/libc/gdtoa/misc.c
673
k = hi0bits(y);
lib/libc/gdtoa/misc.c
674
*e = 32 - k;
lib/libc/gdtoa/misc.c
676
if (k < Ebits) {
lib/libc/gdtoa/misc.c
677
d0 = Exp_1 | y >> (Ebits - k);
lib/libc/gdtoa/misc.c
679
d1 = y << ((32-Ebits) + k) | w >> (Ebits - k);
lib/libc/gdtoa/misc.c
68
x = 1 << k;
lib/libc/gdtoa/misc.c
683
if (k -= Ebits) {
lib/libc/gdtoa/misc.c
684
d0 = Exp_1 | y << k | z >> (32 - k);
lib/libc/gdtoa/misc.c
686
d1 = z << k | y >> (32 - k);
lib/libc/gdtoa/misc.c
693
if (k < Ebits + 16) {
lib/libc/gdtoa/misc.c
695
d0 = Exp_1 | y << k - Ebits | z >> Ebits + 16 - k;
lib/libc/gdtoa/misc.c
698
d1 = z << k + 16 - Ebits | w << k - Ebits | y >> 16 + Ebits - k;
lib/libc/gdtoa/misc.c
703
k -= Ebits + 16;
lib/libc/gdtoa/misc.c
704
d0 = Exp_1 | y << k + 16 | z << k | w >> 16 - k;
lib/libc/gdtoa/misc.c
706
d1 = w << k + 16 | y << k;
lib/libc/gdtoa/misc.c
731
int de, k;
lib/libc/gdtoa/misc.c
76
if (k <= Kmax && pmem_next - private_mem + len <= PRIVATE_mem) {
lib/libc/gdtoa/misc.c
767
if ( (k = lo0bits(&y)) !=0) {
lib/libc/gdtoa/misc.c
768
x[0] = y | z << (32 - k);
lib/libc/gdtoa/misc.c
769
z >>= k;
lib/libc/gdtoa/misc.c
779
k = lo0bits(&z);
lib/libc/gdtoa/misc.c
785
k += 32;
lib/libc/gdtoa/misc.c
789
if ( (k = lo0bits(&y)) !=0)
lib/libc/gdtoa/misc.c
790
if (k >= 16) {
lib/libc/gdtoa/misc.c
791
x[0] = y | z << 32 - k & 0xffff;
lib/libc/gdtoa/misc.c
792
x[1] = z >> k - 16 & 0xffff;
lib/libc/gdtoa/misc.c
793
x[2] = z >> k;
lib/libc/gdtoa/misc.c
798
x[1] = y >> 16 | z << 16 - k & 0xffff;
lib/libc/gdtoa/misc.c
799
x[2] = z >> k & 0xffff;
lib/libc/gdtoa/misc.c
800
x[3] = z >> k+16;
lib/libc/gdtoa/misc.c
816
k = lo0bits(&z);
lib/libc/gdtoa/misc.c
817
if (k >= 16) {
lib/libc/gdtoa/misc.c
826
k += 32;
lib/libc/gdtoa/misc.c
836
*e = (de - Bias - (P-1) << 2) + k;
lib/libc/gdtoa/misc.c
837
*bits = 4*P + 8 - k - hi0bits(word0(&d) & Frac_mask);
lib/libc/gdtoa/misc.c
839
*e = de - Bias - (P-1) + k;
lib/libc/gdtoa/misc.c
840
*bits = P - k;
lib/libc/gdtoa/misc.c
845
*e = de - Bias - (P-1) + 1 + k;
lib/libc/gdtoa/misc.c
86
rv->k = k;
lib/libc/gdtoa/smisc.c
100
dval(&da) *= 1 << k;
lib/libc/gdtoa/smisc.c
103
k = -k;
lib/libc/gdtoa/smisc.c
104
word0(&db) += (k >> 2)*Exp_msk1;
lib/libc/gdtoa/smisc.c
105
if (k &= 3)
lib/libc/gdtoa/smisc.c
106
dval(&db) *= 1 << k;
lib/libc/gdtoa/smisc.c
109
if (k > 0)
lib/libc/gdtoa/smisc.c
110
word0(&da) += k*Exp_msk1;
lib/libc/gdtoa/smisc.c
112
k = -k;
lib/libc/gdtoa/smisc.c
113
word0(&db) += k*Exp_msk1;
lib/libc/gdtoa/smisc.c
175
any_on(b, k) Bigint *b; int k;
lib/libc/gdtoa/smisc.c
177
any_on(Bigint *b, int k)
lib/libc/gdtoa/smisc.c
185
n = k >> kshift;
lib/libc/gdtoa/smisc.c
188
else if (n < nwds && (k &= kmask)) {
lib/libc/gdtoa/smisc.c
190
x1 >>= k;
lib/libc/gdtoa/smisc.c
191
x1 <<= k;
lib/libc/gdtoa/smisc.c
43
int i, k;
lib/libc/gdtoa/smisc.c
47
for(k = 0, y = 1; x > y; y <<= 1, k++) ;
lib/libc/gdtoa/smisc.c
49
b = Balloc(k);
lib/libc/gdtoa/smisc.c
55
b = Balloc(k+1);
lib/libc/gdtoa/smisc.c
91
int k, ka, kb;
lib/libc/gdtoa/smisc.c
95
k = ka - kb + ULbits*(a->wds - b->wds);
lib/libc/gdtoa/smisc.c
97
if (k > 0) {
lib/libc/gdtoa/smisc.c
98
word0(&da) += (k >> 2)*Exp_msk1;
lib/libc/gdtoa/smisc.c
99
if (k &= 3)
lib/libc/gdtoa/strtod.c
346
k = nd < DBL_DIG + 1 ? nd : DBL_DIG + 1;
lib/libc/gdtoa/strtod.c
348
if (k > 9) {
lib/libc/gdtoa/strtod.c
350
if (k > DBL_DIG)
lib/libc/gdtoa/strtod.c
353
dval(&rv) = tens[k - 9] * dval(&rv) + z;
lib/libc/gdtoa/strtod.c
427
e1 += nd - k;
lib/libc/gdtoa/strtod.c
432
if (k <= DBL_DIG)
lib/libc/gdtoa/strtod.c
578
bd = Balloc(bd0->k);
lib/libc/gdtoa/strtod.c
94
e, e1, esign, i, j, k, nd, nd0, nf, nz, nz0, sign;
lib/libc/gdtoa/strtodg.c
1006
k = rvb0->wds - 1;
lib/libc/gdtoa/strtodg.c
1009
else if (rvb->wds <= k
lib/libc/gdtoa/strtodg.c
1010
|| hi0bits( rvb->x[k]) >
lib/libc/gdtoa/strtodg.c
1011
hi0bits(rvb0->x[k])) {
lib/libc/gdtoa/strtodg.c
1031
k = rvb->wds - 1;
lib/libc/gdtoa/strtodg.c
1032
if (k >= rvb0->wds
lib/libc/gdtoa/strtodg.c
1033
|| hi0bits(rvb->x[k]) < hi0bits(rvb0->x[k])) {
lib/libc/gdtoa/strtodg.c
152
int k;
lib/libc/gdtoa/strtodg.c
155
k = (n + ((1 << kshift) - 1)) >> kshift;
lib/libc/gdtoa/strtodg.c
156
if (b->k < k) {
lib/libc/gdtoa/strtodg.c
158
b = Balloc(k);
lib/libc/gdtoa/strtodg.c
162
k = n >> kshift;
lib/libc/gdtoa/strtodg.c
164
k++;
lib/libc/gdtoa/strtodg.c
165
b->wds = k;
lib/libc/gdtoa/strtodg.c
167
xe = x + k;
lib/libc/gdtoa/strtodg.c
186
int bdif, e, j, k, k1, nb, rv;
lib/libc/gdtoa/strtodg.c
221
k = bdif - 1;
lib/libc/gdtoa/strtodg.c
222
if (k < 0)
lib/libc/gdtoa/strtodg.c
224
if (!k) {
lib/libc/gdtoa/strtodg.c
231
if (b->x[k>>kshift] & ((ULong)1 << (k & kmask)))
lib/libc/gdtoa/strtodg.c
268
k = fpi->emin - e;
lib/libc/gdtoa/strtodg.c
270
if (k > nb || fpi->sudden_underflow) {
lib/libc/gdtoa/strtodg.c
275
k1 = k - 1;
lib/libc/gdtoa/strtodg.c
282
rshift(b, k);
lib/libc/gdtoa/strtodg.c
348
int j, k, nbits, nd, nd0, nf, nz, nz0, rd, rvbits, rve, rve1, sign;
lib/libc/gdtoa/strtodg.c
570
k = nd < DBL_DIG + 1 ? nd : DBL_DIG + 1;
lib/libc/gdtoa/strtodg.c
572
if (k > 9)
lib/libc/gdtoa/strtodg.c
573
dval(&rv) = tens[k - 9] * dval(&rv) + z;
lib/libc/gdtoa/strtodg.c
644
e1 += nd - k;
lib/libc/gdtoa/strtodg.c
753
bd = Balloc(bd0->k);
lib/libc/gdtoa/strtodg.c
757
bb = Balloc(rvb->k);
lib/libc/gdtoa/strtodg.c
82
b1 = Balloc(b->k+1);
lib/libc/gdtoa/strtof.c
44
int k;
lib/libc/gdtoa/strtof.c
52
k = strtodg(s, sp, fpi, &exp, bits);
lib/libc/gdtoa/strtof.c
53
switch(k & STRTOG_Retmask) {
lib/libc/gdtoa/strtof.c
78
if (k & STRTOG_Neg)
lib/libc/gdtoa/strtorQ.c
109
int k;
lib/libc/gdtoa/strtorQ.c
117
k = strtodg(s, sp, fpi, &exp, bits);
lib/libc/gdtoa/strtorQ.c
118
ULtoQ((ULong*)L, bits, exp, k);
lib/libc/gdtoa/strtorQ.c
119
return k;
lib/libc/gdtoa/strtorQ.c
54
ULtoQ(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k;
lib/libc/gdtoa/strtorQ.c
56
ULtoQ(ULong *L, ULong *bits, Long exp, int k)
lib/libc/gdtoa/strtorQ.c
59
switch(k & STRTOG_Retmask) {
lib/libc/gdtoa/strtorQ.c
94
if (k & STRTOG_Neg)
lib/libc/gdtoa/strtord.c
36
ULtod(L, bits, exp, k) ULong *L; ULong *bits; Long exp; int k;
lib/libc/gdtoa/strtord.c
38
ULtod(ULong *L, ULong *bits, Long exp, int k)
lib/libc/gdtoa/strtord.c
41
switch(k & STRTOG_Retmask) {
lib/libc/gdtoa/strtord.c
70
if (k & STRTOG_Neg)
lib/libc/gdtoa/strtord.c
85
int k;
lib/libc/gdtoa/strtord.c
93
k = strtodg(s, sp, fpi, &exp, bits);
lib/libc/gdtoa/strtord.c
94
ULtod((ULong*)d, bits, exp, k);
lib/libc/gdtoa/strtord.c
95
return k;
lib/libc/gdtoa/strtorx.c
112
int k;
lib/libc/gdtoa/strtorx.c
120
k = strtodg(s, sp, fpi, &exp, bits);
lib/libc/gdtoa/strtorx.c
121
ULtox((UShort*)L, bits, exp, k);
lib/libc/gdtoa/strtorx.c
122
return k;
lib/libc/gdtoa/strtorx.c
56
ULtox(L, bits, exp, k) UShort *L; ULong *bits; Long exp; int k;
lib/libc/gdtoa/strtorx.c
58
ULtox(UShort *L, ULong *bits, Long exp, int k)
lib/libc/gdtoa/strtorx.c
61
switch(k & STRTOG_Retmask) {
lib/libc/gdtoa/strtorx.c
97
if (k & STRTOG_Neg)
lib/libc/gdtoa/sum.c
50
c = Balloc(a->k);
lib/libc/gdtoa/sum.c
92
b = Balloc(c->k + 1);
lib/libc/gen/glob.c
895
Char c, k;
lib/libc/gen/glob.c
919
if ((k = *name++) == EOS)
lib/libc/gen/glob.c
927
cclasses[idx].isctype(k))
lib/libc/gen/glob.c
932
if (c <= k && k <= pat[1])
lib/libc/gen/glob.c
935
} else if (c == k)
lib/libc/gen/ldexp.c
101
k = (hx&0x7ff00000)>>20; /* extract exponent */
lib/libc/gen/ldexp.c
102
if (k==0) { /* 0 or subnormal x */
lib/libc/gen/ldexp.c
106
k = ((hx&0x7ff00000)>>20) - 54;
lib/libc/gen/ldexp.c
109
if (k==0x7ff) return x+x; /* NaN or Inf */
lib/libc/gen/ldexp.c
110
k = k+n;
lib/libc/gen/ldexp.c
111
if (k > 0x7fe) return huge*_copysign(huge,x); /* overflow */
lib/libc/gen/ldexp.c
112
if (k > 0) /* normal result */
lib/libc/gen/ldexp.c
113
{SET_HIGH_WORD(x,(hx&0x800fffff)|(k<<20)); return x;}
lib/libc/gen/ldexp.c
114
if (k <= -54) {
lib/libc/gen/ldexp.c
119
k += 54; /* subnormal result */
lib/libc/gen/ldexp.c
120
SET_HIGH_WORD(x,(hx&0x800fffff)|(k<<20));
lib/libc/gen/ldexp.c
99
int32_t k,hx,lx;
lib/libc/stdlib/heapsort.c
103
#define SELECT(par_i, child_i, nmemb, par, child, size, k, count, tmp1, tmp2) { \
lib/libc/stdlib/heapsort.c
118
if (child_i == 1 || compar(k, par) < 0) { \
lib/libc/stdlib/heapsort.c
119
COPY(child, k, count, size, tmp1, tmp2); \
lib/libc/stdlib/heapsort.c
139
char *base, *k, *p, *t;
lib/libc/stdlib/heapsort.c
149
if ((k = malloc(size)) == NULL)
lib/libc/stdlib/heapsort.c
167
COPY(k, base + nmemb * size, cnt, size, tmp1, tmp2);
lib/libc/stdlib/heapsort.c
170
SELECT(i, j, nmemb, t, p, size, k, cnt, tmp1, tmp2);
lib/libc/stdlib/heapsort.c
172
free(k);
lib/libc/stdlib/malloc.c
1151
u_int i, j, k, r, bucket, listnum;
lib/libc/stdlib/malloc.c
1187
k = ffs(*lp >> j) + j;
lib/libc/stdlib/malloc.c
1192
k = ffs(*lp);
lib/libc/stdlib/malloc.c
1200
*lp ^= 1 << --k;
lib/libc/stdlib/malloc.c
1207
k += i * MALLOC_BITS;
lib/libc/stdlib/malloc.c
1210
bp->bits[bp->offset + k] = size;
lib/libc/stdlib/malloc.c
1214
STATS_SETFN(r, k, d->caller);
lib/libc/stdlib/malloc.c
1217
p = (char *)bp->page + k * B2ALLOC(bucket);
lib/libc/stdlib/malloc.c
195
#define STATS_SETFN(x,k,y) ((x)->f[k] = (y))
lib/libc/stdlib/malloc.c
203
#define STATS_SETFN(x,k,y) /* nothing */
lib/libc/string/memmem.c
101
ip = -1; jp = 0; k = p = 1;
lib/libc/string/memmem.c
102
while (jp+k<l) {
lib/libc/string/memmem.c
103
if (n[ip+k] == n[jp+k]) {
lib/libc/string/memmem.c
104
if (k == p) {
lib/libc/string/memmem.c
106
k = 1;
lib/libc/string/memmem.c
107
} else k++;
lib/libc/string/memmem.c
108
} else if (n[ip+k] < n[jp+k]) {
lib/libc/string/memmem.c
109
jp += k;
lib/libc/string/memmem.c
110
k = 1;
lib/libc/string/memmem.c
114
k = p = 1;
lib/libc/string/memmem.c
134
k = l-shift[h[l-1]];
lib/libc/string/memmem.c
135
if (k) {
lib/libc/string/memmem.c
136
if (k < mem) k = mem;
lib/libc/string/memmem.c
137
h += k;
lib/libc/string/memmem.c
148
for (k=MAX(ms+1,mem); k<l && n[k] == h[k]; k++);
lib/libc/string/memmem.c
149
if (k < l) {
lib/libc/string/memmem.c
150
h += k-ms;
lib/libc/string/memmem.c
155
for (k=ms+1; k>mem && n[k-1] == h[k-1]; k--);
lib/libc/string/memmem.c
156
if (k <= mem) return (char *)h;
lib/libc/string/memmem.c
163
memmem(const void *h0, size_t k, const void *n0, size_t l)
lib/libc/string/memmem.c
171
if (k<l) return 0;
lib/libc/string/memmem.c
174
h = memchr(h0, *n, k);
lib/libc/string/memmem.c
176
k -= h - (const unsigned char *)h0;
lib/libc/string/memmem.c
177
if (k<l) return 0;
lib/libc/string/memmem.c
178
if (l==2) return twobyte_memmem(h, k, n);
lib/libc/string/memmem.c
179
if (l==3) return threebyte_memmem(h, k, n);
lib/libc/string/memmem.c
180
if (l==4) return fourbyte_memmem(h, k, n);
lib/libc/string/memmem.c
182
return twoway_memmem(h, h+k, n, l);
lib/libc/string/memmem.c
30
twobyte_memmem(const unsigned char *h, size_t k, const unsigned char *n)
lib/libc/string/memmem.c
33
for (h+=2, k-=2; k; k--, hw = hw<<8 | *h++)
lib/libc/string/memmem.c
39
threebyte_memmem(const unsigned char *h, size_t k, const unsigned char *n)
lib/libc/string/memmem.c
43
for (h+=3, k-=3; k; k--, hw = (hw|*h++)<<8)
lib/libc/string/memmem.c
49
fourbyte_memmem(const unsigned char *h, size_t k, const unsigned char *n)
lib/libc/string/memmem.c
53
for (h+=4, k-=4; k; k--, hw = hw<<8 | *h++)
lib/libc/string/memmem.c
72
size_t i, ip, jp, k, p, ms, p0, mem, mem0;
lib/libc/string/memmem.c
81
ip = -1; jp = 0; k = p = 1;
lib/libc/string/memmem.c
82
while (jp+k<l) {
lib/libc/string/memmem.c
83
if (n[ip+k] == n[jp+k]) {
lib/libc/string/memmem.c
84
if (k == p) {
lib/libc/string/memmem.c
86
k = 1;
lib/libc/string/memmem.c
87
} else k++;
lib/libc/string/memmem.c
88
} else if (n[ip+k] > n[jp+k]) {
lib/libc/string/memmem.c
89
jp += k;
lib/libc/string/memmem.c
90
k = 1;
lib/libc/string/memmem.c
94
k = p = 1;
lib/libc/string/strstr.c
100
while (jp+k<l) {
lib/libc/string/strstr.c
101
if (n[ip+k] == n[jp+k]) {
lib/libc/string/strstr.c
102
if (k == p) {
lib/libc/string/strstr.c
104
k = 1;
lib/libc/string/strstr.c
105
} else k++;
lib/libc/string/strstr.c
106
} else if (n[ip+k] < n[jp+k]) {
lib/libc/string/strstr.c
107
jp += k;
lib/libc/string/strstr.c
108
k = 1;
lib/libc/string/strstr.c
112
k = p = 1;
lib/libc/string/strstr.c
143
k = l-shift[h[l-1]];
lib/libc/string/strstr.c
144
if (k) {
lib/libc/string/strstr.c
145
if (k < mem) k = mem;
lib/libc/string/strstr.c
146
h += k;
lib/libc/string/strstr.c
157
for (k=MAX(ms+1,mem); n[k] && n[k] == h[k]; k++);
lib/libc/string/strstr.c
158
if (n[k]) {
lib/libc/string/strstr.c
159
h += k-ms;
lib/libc/string/strstr.c
164
for (k=ms+1; k>mem && n[k-1] == h[k-1]; k--);
lib/libc/string/strstr.c
165
if (k <= mem) return (char *)h;
lib/libc/string/strstr.c
69
size_t l, ip, jp, k, p, ms, p0, mem, mem0;
lib/libc/string/strstr.c
79
ip = -1; jp = 0; k = p = 1;
lib/libc/string/strstr.c
80
while (jp+k<l) {
lib/libc/string/strstr.c
81
if (n[ip+k] == n[jp+k]) {
lib/libc/string/strstr.c
82
if (k == p) {
lib/libc/string/strstr.c
84
k = 1;
lib/libc/string/strstr.c
85
} else k++;
lib/libc/string/strstr.c
86
} else if (n[ip+k] > n[jp+k]) {
lib/libc/string/strstr.c
87
jp += k;
lib/libc/string/strstr.c
88
k = 1;
lib/libc/string/strstr.c
92
k = p = 1;
lib/libc/string/strstr.c
99
ip = -1; jp = 0; k = p = 1;
lib/libc/thread/rthread_libc.c
107
ret = pthread_getspecific(tt->k);
lib/libc/thread/rthread_libc.c
113
if (pthread_setspecific(tt->k, ret) == 0) {
lib/libc/thread/rthread_libc.c
18
pthread_key_t k; /* a key for private data */
lib/libc/thread/rthread_libc.c
45
result |= pthread_key_create(&tt->k, dt ? dt :
lib/libcrypto/asn1/a_enum.c
271
int i, j,k, m,n, again, bufsize;
lib/libcrypto/asn1/a_enum.c
309
k = 0;
lib/libcrypto/asn1/a_enum.c
324
for (j = 0; j < i; j++, k += 2) {
lib/libcrypto/asn1/a_enum.c
326
m = bufp[k + n];
lib/libcrypto/asn1/a_int.c
443
int i, j,k, m,n, again, bufsize;
lib/libcrypto/asn1/a_int.c
480
k = 0;
lib/libcrypto/asn1/a_int.c
494
for (j = 0; j < i; j++, k += 2) {
lib/libcrypto/asn1/a_int.c
496
m = bufp[k + n];
lib/libcrypto/asn1/a_string.c
364
int i, j, k, m, n, again, bufsize;
lib/libcrypto/asn1/a_string.c
400
k = 0;
lib/libcrypto/asn1/a_string.c
415
for (j = 0; j < i; j++, k += 2) {
lib/libcrypto/asn1/a_string.c
417
m = bufp[k + n];
lib/libcrypto/bn/bn_bpsw.c
123
bn_lucas(BIGNUM *U, BIGNUM *V, const BIGNUM *k, const BIGNUM *D,
lib/libcrypto/bn/bn_bpsw.c
139
for (i = BN_num_bits(k) - 2; i >= 0; i--) {
lib/libcrypto/bn/bn_bpsw.c
140
digit = BN_is_bit_set(k, i);
lib/libcrypto/bn/bn_bpsw.c
162
BIGNUM *k, *U, *V;
lib/libcrypto/bn/bn_bpsw.c
168
if ((k = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_bpsw.c
183
if (!BN_rshift(k, n, s))
lib/libcrypto/bn/bn_bpsw.c
185
if (!BN_set_bit(k, 0))
lib/libcrypto/bn/bn_bpsw.c
193
if (!bn_lucas(U, V, k, D, n, ctx))
lib/libcrypto/bn/bn_bpsw.c
322
const BIGNUM *k, int s, const BIGNUM *base, BN_CTX *ctx, BN_MONT_CTX *mctx)
lib/libcrypto/bn/bn_bpsw.c
337
if (!BN_mod_exp_mont_ct(power, base, k, n, ctx, mctx))
lib/libcrypto/bn/bn_bpsw.c
388
BIGNUM *base, *k, *n_minus_one;
lib/libcrypto/bn/bn_bpsw.c
397
if ((k = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_bpsw.c
422
if (!BN_rshift(k, n_minus_one, s))
lib/libcrypto/bn/bn_bpsw.c
439
if (!bn_fermat(is_pseudoprime, n, n_minus_one, k, s, base, ctx, mctx))
lib/libcrypto/bn/bn_bpsw.c
453
if (!bn_fermat(is_pseudoprime, n, n_minus_one, k, s, base, ctx,
lib/libcrypto/bn/bn_kron.c
114
k = 1;
lib/libcrypto/bn/bn_kron.c
116
k = tab[BN_lsw(a) & 7];
lib/libcrypto/bn/bn_kron.c
126
k = -k;
lib/libcrypto/bn/bn_kron.c
143
ret = BN_is_one(b) ? k : 0;
lib/libcrypto/bn/bn_kron.c
156
k *= tab[BN_lsw(b) & 7];
lib/libcrypto/bn/bn_kron.c
171
k = -k;
lib/libcrypto/bn/bn_kron.c
71
int k, v;
lib/libcrypto/bn/bn_lib.c
415
int i, j, k;
lib/libcrypto/bn/bn_lib.c
425
for (k = a->top; k < i + 1; k++)
lib/libcrypto/bn/bn_lib.c
426
a->d[k] = 0;
lib/libcrypto/bn/bn_mod_sqrt.c
314
BIGNUM *k;
lib/libcrypto/bn/bn_mod_sqrt.c
319
if ((k = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/bn/bn_mod_sqrt.c
323
if (!BN_rshift1(k, q))
lib/libcrypto/bn/bn_mod_sqrt.c
327
if (!BN_mod_exp_ct(x, a, k, p, ctx))
lib/libcrypto/bn/s2n_bignum.h
100
extern uint64_t bignum_bitfield (uint64_t k, const uint64_t *x, uint64_t n, uint64_t l);
lib/libcrypto/bn/s2n_bignum.h
104
extern uint64_t bignum_bitsize (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
108
extern uint64_t bignum_cdiv (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, uint64_t m);
lib/libcrypto/bn/s2n_bignum.h
112
extern void bignum_cdiv_exact (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, uint64_t m);
lib/libcrypto/bn/s2n_bignum.h
116
extern uint64_t bignum_cld (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
120
extern uint64_t bignum_clz (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
124
extern uint64_t bignum_cmadd (uint64_t k, uint64_t *z, uint64_t c, uint64_t n, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
128
extern uint64_t bignum_cmnegadd (uint64_t k, uint64_t *z, uint64_t c, uint64_t n, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
132
extern uint64_t bignum_cmod (uint64_t k, const uint64_t *x, uint64_t m);
lib/libcrypto/bn/s2n_bignum.h
136
extern uint64_t bignum_cmul (uint64_t k, uint64_t *z, uint64_t c, uint64_t n, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
174
extern void bignum_copy (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
212
extern uint64_t bignum_ctd (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
216
extern uint64_t bignum_ctz (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
242
extern void bignum_demont (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
268
extern uint64_t bignum_digit (uint64_t k, const uint64_t *x, uint64_t n);
lib/libcrypto/bn/s2n_bignum.h
272
extern uint64_t bignum_digitsize (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
276
extern uint64_t bignum_divmod10 (uint64_t k, uint64_t *z);
lib/libcrypto/bn/s2n_bignum.h
304
extern uint64_t bignum_emontredc (uint64_t k, uint64_t *z, const uint64_t *m, uint64_t w);
lib/libcrypto/bn/s2n_bignum.h
308
extern uint64_t bignum_emontredc_8n (uint64_t k, uint64_t *z, const uint64_t *m, uint64_t w);
lib/libcrypto/bn/s2n_bignum.h
311
extern uint64_t bignum_emontredc_8n_cdiff (uint64_t k, uint64_t *z, const uint64_t *m,
lib/libcrypto/bn/s2n_bignum.h
320
extern uint64_t bignum_even (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
397
extern uint64_t bignum_iszero (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
433
extern uint64_t bignum_madd (uint64_t k, uint64_t *z, uint64_t m, const uint64_t *x, uint64_t n, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
446
extern void bignum_mod_n25519 (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
454
extern void bignum_mod_n256 (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
455
extern void bignum_mod_n256_alt (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
467
extern void bignum_mod_n384 (uint64_t z[S2N_BIGNUM_STATIC 6], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
468
extern void bignum_mod_n384_alt (uint64_t z[S2N_BIGNUM_STATIC 6], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
481
extern void bignum_mod_nsm2 (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
482
extern void bignum_mod_nsm2_alt (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
494
extern void bignum_mod_p256 (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
495
extern void bignum_mod_p256_alt (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
507
extern void bignum_mod_p384 (uint64_t z[S2N_BIGNUM_STATIC 6], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
508
extern void bignum_mod_p384_alt (uint64_t z[S2N_BIGNUM_STATIC 6], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
520
extern void bignum_mod_sm2 (uint64_t z[S2N_BIGNUM_STATIC 4], uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
528
extern void bignum_modadd (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *y, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
532
extern void bignum_moddouble (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
536
extern void bignum_modexp(uint64_t k,uint64_t *z, const uint64_t *a,const uint64_t *p,const uint64_t *m,uint64_t *t);
lib/libcrypto/bn/s2n_bignum.h
540
extern void bignum_modifier (uint64_t k, uint64_t *z, const uint64_t *m, uint64_t *t);
lib/libcrypto/bn/s2n_bignum.h
544
extern void bignum_modinv (uint64_t k, uint64_t *z, const uint64_t *a, const uint64_t *b, uint64_t *t);
lib/libcrypto/bn/s2n_bignum.h
548
extern void bignum_modoptneg (uint64_t k, uint64_t *z, uint64_t p, const uint64_t *x, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
552
extern void bignum_modsub (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *y, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
556
extern void bignum_montifier (uint64_t k, uint64_t *z, const uint64_t *m, uint64_t *t);
lib/libcrypto/bn/s2n_bignum.h
572
extern void bignum_montmul (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *y, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
601
extern void bignum_montredc (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, const uint64_t *m, uint64_t p);
lib/libcrypto/bn/s2n_bignum.h
605
extern void bignum_montsqr (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
634
extern void bignum_mul (uint64_t k, uint64_t *z, uint64_t m, const uint64_t *x, uint64_t n, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
668
extern uint64_t bignum_muladd10 (uint64_t k, uint64_t *z, uint64_t d);
lib/libcrypto/bn/s2n_bignum.h
672
extern void bignum_mux (uint64_t p, uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
684
extern void bignum_mux16 (uint64_t k, uint64_t *z, const uint64_t *xs, uint64_t i);
lib/libcrypto/bn/s2n_bignum.h
712
extern void bignum_negmodinv (uint64_t k, uint64_t *z, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
716
extern uint64_t bignum_nonzero (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
728
extern uint64_t bignum_normalize (uint64_t k, uint64_t *z);
lib/libcrypto/bn/s2n_bignum.h
732
extern uint64_t bignum_odd (uint64_t k, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
736
extern void bignum_of_word (uint64_t k, uint64_t *z, uint64_t n);
lib/libcrypto/bn/s2n_bignum.h
740
extern uint64_t bignum_optadd (uint64_t k, uint64_t *z, const uint64_t *x, uint64_t p, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
744
extern uint64_t bignum_optneg (uint64_t k, uint64_t *z, uint64_t p, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
76
extern void bignum_amontifier (uint64_t k, uint64_t *z, const uint64_t *m, uint64_t *t);
lib/libcrypto/bn/s2n_bignum.h
772
extern uint64_t bignum_optsub (uint64_t k, uint64_t *z, const uint64_t *x, uint64_t p, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
776
extern uint64_t bignum_optsubadd (uint64_t k, uint64_t *z, const uint64_t *x, uint64_t p, const uint64_t *y);
lib/libcrypto/bn/s2n_bignum.h
780
extern void bignum_pow2 (uint64_t k, uint64_t *z, uint64_t n);
lib/libcrypto/bn/s2n_bignum.h
784
extern uint64_t bignum_shl_small (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, uint64_t c);
lib/libcrypto/bn/s2n_bignum.h
788
extern uint64_t bignum_shr_small (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, uint64_t c);
lib/libcrypto/bn/s2n_bignum.h
792
extern void bignum_sqr (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x);
lib/libcrypto/bn/s2n_bignum.h
80
extern void bignum_amontmul (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *y, const uint64_t *m);
lib/libcrypto/bn/s2n_bignum.h
84
extern void bignum_amontredc (uint64_t k, uint64_t *z, uint64_t n, const uint64_t *x, const uint64_t *m, uint64_t p);
lib/libcrypto/bn/s2n_bignum.h
88
extern void bignum_amontsqr (uint64_t k, uint64_t *z, const uint64_t *x, const uint64_t *m);
lib/libcrypto/camellia/camellia.c
362
Camellia_Ekeygen(int keyBitLength, const u8 *rawKey, KEY_TABLE_TYPE k)
lib/libcrypto/camellia/camellia.c
366
k[0] = s0 = GETU32(rawKey);
lib/libcrypto/camellia/camellia.c
367
k[1] = s1 = GETU32(rawKey + 4);
lib/libcrypto/camellia/camellia.c
368
k[2] = s2 = GETU32(rawKey + 8);
lib/libcrypto/camellia/camellia.c
369
k[3] = s3 = GETU32(rawKey + 12);
lib/libcrypto/camellia/camellia.c
372
k[8] = s0 = GETU32(rawKey + 16);
lib/libcrypto/camellia/camellia.c
373
k[9] = s1 = GETU32(rawKey + 20);
lib/libcrypto/camellia/camellia.c
375
k[10] = s2 = ~s0;
lib/libcrypto/camellia/camellia.c
376
k[11] = s3 = ~s1;
lib/libcrypto/camellia/camellia.c
378
k[10] = s2 = GETU32(rawKey + 24);
lib/libcrypto/camellia/camellia.c
379
k[11] = s3 = GETU32(rawKey + 28);
lib/libcrypto/camellia/camellia.c
381
s0 ^= k[0], s1 ^= k[1], s2 ^= k[2], s3 ^= k[3];
lib/libcrypto/camellia/camellia.c
388
s0 ^= k[0], s1 ^= k[1], s2 ^= k[2], s3 ^= k[3];
lib/libcrypto/camellia/camellia.c
394
k[ 4] = s0, k[ 5] = s1, k[ 6] = s2, k[ 7] = s3;
lib/libcrypto/camellia/camellia.c
396
k[12] = s0, k[13] = s1, k[14] = s2, k[15] = s3;
lib/libcrypto/camellia/camellia.c
398
k[16] = s0, k[17] = s1, k[18] = s2, k[19] = s3;
lib/libcrypto/camellia/camellia.c
400
k[24] = s0, k[25] = s1;
lib/libcrypto/camellia/camellia.c
402
k[28] = s0, k[29] = s1, k[30] = s2, k[31] = s3;
lib/libcrypto/camellia/camellia.c
404
k[40] = s1, k[41] = s2, k[42] = s3, k[43] = s0;
lib/libcrypto/camellia/camellia.c
406
k[48] = s1, k[49] = s2, k[50] = s3, k[51] = s0;
lib/libcrypto/camellia/camellia.c
408
s0 = k[ 0], s1 = k[ 1], s2 = k[ 2], s3 = k[ 3];
lib/libcrypto/camellia/camellia.c
410
k[ 8] = s0, k[ 9] = s1, k[10] = s2, k[11] = s3;
lib/libcrypto/camellia/camellia.c
412
k[20] = s0, k[21] = s1, k[22] = s2, k[23] = s3;
lib/libcrypto/camellia/camellia.c
414
k[26] = s2, k[27] = s3;
lib/libcrypto/camellia/camellia.c
416
k[32] = s0, k[33] = s1, k[34] = s2, k[35] = s3;
lib/libcrypto/camellia/camellia.c
418
k[36] = s0, k[37] = s1, k[38] = s2, k[39] = s3;
lib/libcrypto/camellia/camellia.c
420
k[44] = s0, k[45] = s1, k[46] = s2, k[47] = s3;
lib/libcrypto/camellia/camellia.c
424
k[12] = s0, k[13] = s1, k[14] = s2, k[15] = s3;
lib/libcrypto/camellia/camellia.c
425
s0 ^= k[8], s1 ^= k[9], s2 ^=k[10], s3 ^=k[11];
lib/libcrypto/camellia/camellia.c
429
k[ 4] = s0, k[ 5] = s1, k[ 6] = s2, k[ 7] = s3;
lib/libcrypto/camellia/camellia.c
431
k[20] = s0, k[21] = s1, k[22] = s2, k[23] = s3;
lib/libcrypto/camellia/camellia.c
433
k[40] = s0, k[41] = s1, k[42] = s2, k[43] = s3;
lib/libcrypto/camellia/camellia.c
435
k[64] = s1, k[65] = s2, k[66] = s3, k[67] = s0;
lib/libcrypto/camellia/camellia.c
437
s0 = k[ 8], s1 = k[ 9], s2 = k[10], s3 = k[11];
lib/libcrypto/camellia/camellia.c
439
k[ 8] = s0, k[ 9] = s1, k[10] = s2, k[11] = s3;
lib/libcrypto/camellia/camellia.c
441
k[16] = s0, k[17] = s1, k[18] = s2, k[19] = s3;
lib/libcrypto/camellia/camellia.c
443
k[36] = s0, k[37] = s1, k[38] = s2, k[39] = s3;
lib/libcrypto/camellia/camellia.c
445
k[52] = s1, k[53] = s2, k[54] = s3, k[55] = s0;
lib/libcrypto/camellia/camellia.c
447
s0 = k[12], s1 = k[13], s2 = k[14], s3 = k[15];
lib/libcrypto/camellia/camellia.c
449
k[12] = s0, k[13] = s1, k[14] = s2, k[15] = s3;
lib/libcrypto/camellia/camellia.c
451
k[28] = s0, k[29] = s1, k[30] = s2, k[31] = s3;
lib/libcrypto/camellia/camellia.c
453
k[48] = s1, k[49] = s2, k[50] = s3, k[51] = s0;
lib/libcrypto/camellia/camellia.c
455
k[56] = s1, k[57] = s2, k[58] = s3, k[59] = s0;
lib/libcrypto/camellia/camellia.c
457
s0 = k[ 0], s1 = k[ 1], s2 = k[ 2], s3 = k[ 3];
lib/libcrypto/camellia/camellia.c
459
k[24] = s1, k[25] = s2, k[26] = s3, k[27] = s0;
lib/libcrypto/camellia/camellia.c
461
k[32] = s1, k[33] = s2, k[34] = s3, k[35] = s0;
lib/libcrypto/camellia/camellia.c
463
k[44] = s1, k[45] = s2, k[46] = s3, k[47] = s0;
lib/libcrypto/camellia/camellia.c
465
k[60] = s2, k[61] = s3, k[62] = s0, k[63] = s1;
lib/libcrypto/camellia/camellia.c
484
const u32 *k = keyTable, *kend = keyTable + grandRounds * 16;
lib/libcrypto/camellia/camellia.c
486
s0 = GETU32(plaintext) ^ k[0];
lib/libcrypto/camellia/camellia.c
487
s1 = GETU32(plaintext + 4) ^ k[1];
lib/libcrypto/camellia/camellia.c
488
s2 = GETU32(plaintext + 8) ^ k[2];
lib/libcrypto/camellia/camellia.c
489
s3 = GETU32(plaintext + 12) ^ k[3];
lib/libcrypto/camellia/camellia.c
490
k += 4;
lib/libcrypto/camellia/camellia.c
494
Camellia_Feistel(s0, s1, s2, s3, k + 0);
lib/libcrypto/camellia/camellia.c
495
Camellia_Feistel(s2, s3, s0, s1, k + 2);
lib/libcrypto/camellia/camellia.c
496
Camellia_Feistel(s0, s1, s2, s3, k + 4);
lib/libcrypto/camellia/camellia.c
497
Camellia_Feistel(s2, s3, s0, s1, k + 6);
lib/libcrypto/camellia/camellia.c
498
Camellia_Feistel(s0, s1, s2, s3, k + 8);
lib/libcrypto/camellia/camellia.c
499
Camellia_Feistel(s2, s3, s0, s1, k + 10);
lib/libcrypto/camellia/camellia.c
500
k += 12;
lib/libcrypto/camellia/camellia.c
502
if (k == kend)
lib/libcrypto/camellia/camellia.c
508
s1 ^= LeftRotate(s0 & k[0], 1);
lib/libcrypto/camellia/camellia.c
509
s2 ^= s3 | k[3];
lib/libcrypto/camellia/camellia.c
510
s0 ^= s1 | k[1];
lib/libcrypto/camellia/camellia.c
511
s3 ^= LeftRotate(s2 & k[2], 1);
lib/libcrypto/camellia/camellia.c
512
k += 4;
lib/libcrypto/camellia/camellia.c
515
s2 ^= k[0], s3 ^= k[1], s0 ^= k[2], s1 ^= k[3];
lib/libcrypto/camellia/camellia.c
536
const u32 *k = keyTable+grandRounds * 16, *kend = keyTable+4;
lib/libcrypto/camellia/camellia.c
538
s0 = GETU32(ciphertext) ^ k[0];
lib/libcrypto/camellia/camellia.c
539
s1 = GETU32(ciphertext+4) ^ k[1];
lib/libcrypto/camellia/camellia.c
540
s2 = GETU32(ciphertext+8) ^ k[2];
lib/libcrypto/camellia/camellia.c
541
s3 = GETU32(ciphertext+12) ^ k[3];
lib/libcrypto/camellia/camellia.c
545
k -= 12;
lib/libcrypto/camellia/camellia.c
546
Camellia_Feistel(s0, s1, s2, s3, k+10);
lib/libcrypto/camellia/camellia.c
547
Camellia_Feistel(s2, s3, s0, s1, k+8);
lib/libcrypto/camellia/camellia.c
548
Camellia_Feistel(s0, s1, s2, s3, k+6);
lib/libcrypto/camellia/camellia.c
549
Camellia_Feistel(s2, s3, s0, s1, k+4);
lib/libcrypto/camellia/camellia.c
550
Camellia_Feistel(s0, s1, s2, s3, k+2);
lib/libcrypto/camellia/camellia.c
551
Camellia_Feistel(s2, s3, s0, s1, k+0);
lib/libcrypto/camellia/camellia.c
553
if (k == kend)
lib/libcrypto/camellia/camellia.c
559
k -= 4;
lib/libcrypto/camellia/camellia.c
560
s1 ^= LeftRotate(s0 & k[2], 1);
lib/libcrypto/camellia/camellia.c
561
s2 ^= s3 | k[1];
lib/libcrypto/camellia/camellia.c
562
s0 ^= s1 | k[3];
lib/libcrypto/camellia/camellia.c
563
s3 ^= LeftRotate(s2 & k[0], 1);
lib/libcrypto/camellia/camellia.c
566
k -= 4;
lib/libcrypto/camellia/camellia.c
567
s2 ^= k[0], s3 ^= k[1], s0 ^= k[2], s1 ^= k[3];
lib/libcrypto/cast/cast.c
597
const CAST_LONG *k;
lib/libcrypto/cast/cast.c
599
k = &(key->data[0]);
lib/libcrypto/cast/cast.c
603
E_CAST( 0, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
604
E_CAST( 1, k,r, l,^, -,+);
lib/libcrypto/cast/cast.c
605
E_CAST( 2, k,l, r, -,+,^);
lib/libcrypto/cast/cast.c
606
E_CAST( 3, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
607
E_CAST( 4, k,l, r,^, -,+);
lib/libcrypto/cast/cast.c
608
E_CAST( 5, k,r, l, -,+,^);
lib/libcrypto/cast/cast.c
609
E_CAST( 6, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
610
E_CAST( 7, k,r, l,^, -,+);
lib/libcrypto/cast/cast.c
611
E_CAST( 8, k,l, r, -,+,^);
lib/libcrypto/cast/cast.c
612
E_CAST( 9, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
613
E_CAST(10, k,l, r,^, -,+);
lib/libcrypto/cast/cast.c
614
E_CAST(11, k,r, l, -,+,^);
lib/libcrypto/cast/cast.c
616
E_CAST(12, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
617
E_CAST(13, k,r, l,^, -,+);
lib/libcrypto/cast/cast.c
618
E_CAST(14, k,l, r, -,+,^);
lib/libcrypto/cast/cast.c
619
E_CAST(15, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
631
const CAST_LONG *k;
lib/libcrypto/cast/cast.c
633
k = &(key->data[0]);
lib/libcrypto/cast/cast.c
638
E_CAST(15, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
639
E_CAST(14, k,r, l, -,+,^);
lib/libcrypto/cast/cast.c
640
E_CAST(13, k,l, r,^, -,+);
lib/libcrypto/cast/cast.c
641
E_CAST(12, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
643
E_CAST(11, k,l, r, -,+,^);
lib/libcrypto/cast/cast.c
644
E_CAST(10, k,r, l,^, -,+);
lib/libcrypto/cast/cast.c
645
E_CAST( 9, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
646
E_CAST( 8, k,r, l, -,+,^);
lib/libcrypto/cast/cast.c
647
E_CAST( 7, k,l, r,^, -,+);
lib/libcrypto/cast/cast.c
648
E_CAST( 6, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
649
E_CAST( 5, k,l, r, -,+,^);
lib/libcrypto/cast/cast.c
650
E_CAST( 4, k,r, l,^, -,+);
lib/libcrypto/cast/cast.c
651
E_CAST( 3, k,l, r,+,^, -);
lib/libcrypto/cast/cast.c
652
E_CAST( 2, k,r, l, -,+,^);
lib/libcrypto/cast/cast.c
653
E_CAST( 1, k,l, r,^, -,+);
lib/libcrypto/cast/cast.c
654
E_CAST( 0, k,r, l,+,^, -);
lib/libcrypto/cast/cast.c
678
CAST_LONG k[32];
lib/libcrypto/cast/cast.c
695
K = &k[0];
lib/libcrypto/cast/cast.c
757
if (K != k)
lib/libcrypto/cast/cast.c
763
key->data[i*2] = k[i];
lib/libcrypto/cast/cast.c
764
key->data[i*2 + 1] = ((k[i + 16]) + 16)&0x1f;
lib/libcrypto/chacha/chacha-merged.c
100
x->input[9] = U8TO32_LITTLE(k + 4);
lib/libcrypto/chacha/chacha-merged.c
101
x->input[10] = U8TO32_LITTLE(k + 8);
lib/libcrypto/chacha/chacha-merged.c
102
x->input[11] = U8TO32_LITTLE(k + 12);
lib/libcrypto/chacha/chacha-merged.c
25
static inline void chacha_keysetup(struct chacha_ctx *x, const u8 *k, u32 kbits)
lib/libcrypto/chacha/chacha-merged.c
85
chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)
lib/libcrypto/chacha/chacha-merged.c
89
x->input[4] = U8TO32_LITTLE(k + 0);
lib/libcrypto/chacha/chacha-merged.c
90
x->input[5] = U8TO32_LITTLE(k + 4);
lib/libcrypto/chacha/chacha-merged.c
91
x->input[6] = U8TO32_LITTLE(k + 8);
lib/libcrypto/chacha/chacha-merged.c
92
x->input[7] = U8TO32_LITTLE(k + 12);
lib/libcrypto/chacha/chacha-merged.c
94
k += 16;
lib/libcrypto/chacha/chacha-merged.c
99
x->input[8] = U8TO32_LITTLE(k + 0);
lib/libcrypto/chacha/chacha.c
44
unsigned char *k;
lib/libcrypto/chacha/chacha.c
50
k = ctx->ks + 64 - ctx->unused;
lib/libcrypto/chacha/chacha.c
53
*(out++) = *(in++) ^ *(k++);
lib/libcrypto/curve25519/curve25519.c
3612
int k;
lib/libcrypto/curve25519/curve25519.c
3627
for (k = i + b; k < 256; ++k) {
lib/libcrypto/curve25519/curve25519.c
3628
if (!r[k]) {
lib/libcrypto/curve25519/curve25519.c
3629
r[k] = 1;
lib/libcrypto/curve25519/curve25519.c
3632
r[k] = 0;
lib/libcrypto/des/des_key.c
345
DES_LONG *k;
lib/libcrypto/des/des_key.c
348
k = &schedule->ks->deslong[0];
lib/libcrypto/des/des_key.c
391
*(k++) = ROTATE(t2, 30) & 0xffffffffL;
lib/libcrypto/des/des_key.c
394
*(k++) = ROTATE(t2, 26) & 0xffffffffL;
lib/libcrypto/dsa/dsa_gen.c
114
int i, k, n = 0, m = 0, qsize = qbits >> 3;
lib/libcrypto/dsa/dsa_gen.c
244
for (k = 0; k <= n; k++) {
lib/libcrypto/dsa/dsa_gen.c
259
if (!BN_lshift(r0, r0, (qsize << 3) * k))
lib/libcrypto/dsa/dsa_ossl.c
208
BIGNUM *k = NULL, *l = NULL, *m = NULL, *kinv = NULL, *r = NULL;
lib/libcrypto/dsa/dsa_ossl.c
226
if ((k = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/dsa/dsa_ossl.c
235
if (!BN_set_bit(k, q_bits) ||
lib/libcrypto/dsa/dsa_ossl.c
240
if (!bn_rand_interval(k, 1, dsa->q))
lib/libcrypto/dsa/dsa_ossl.c
243
BN_set_flags(k, BN_FLG_CONSTTIME);
lib/libcrypto/dsa/dsa_ossl.c
266
if (!BN_add(l, k, dsa->q) ||
lib/libcrypto/dsa/dsa_ossl.c
268
!bn_copy(k, BN_num_bits(l) > q_bits ? l : m))
lib/libcrypto/dsa/dsa_ossl.c
271
if (!BN_mod_exp_mont_ct(r, dsa->g, k, dsa->p, ctx, dsa->method_mont_p))
lib/libcrypto/dsa/dsa_ossl.c
278
if ((kinv = BN_mod_inverse_ct(NULL, k, dsa->q, ctx)) == NULL)
lib/libcrypto/ec/ec_mult.c
281
int k;
lib/libcrypto/ec/ec_mult.c
320
for (k = num_digits - 1; k >= 0; k--) {
lib/libcrypto/ec/ec_mult.c
329
if ((digit = ec_wnaf_digit(wnaf[i], k)) == 0)
lib/libcrypto/ec/ecp_methods.c
1070
BIGNUM *k = NULL;
lib/libcrypto/ec/ecp_methods.c
1086
if ((k = BN_CTX_get(ctx)) == NULL)
lib/libcrypto/ec/ecp_methods.c
1099
if (!bn_wexpand(k, group_top + 2) ||
lib/libcrypto/ec/ecp_methods.c
1103
if (!bn_copy(k, scalar))
lib/libcrypto/ec/ecp_methods.c
1106
BN_set_flags(k, BN_FLG_CONSTTIME);
lib/libcrypto/ec/ecp_methods.c
1108
if (BN_num_bits(k) > cardinality_bits || BN_is_negative(k)) {
lib/libcrypto/ec/ecp_methods.c
1113
if (!BN_nnmod(k, k, cardinality, ctx))
lib/libcrypto/ec/ecp_methods.c
1117
if (!BN_add(lambda, k, cardinality))
lib/libcrypto/ec/ecp_methods.c
1120
if (!BN_add(k, lambda, cardinality))
lib/libcrypto/ec/ecp_methods.c
1127
if (!BN_swap_ct(kbit, k, lambda, group_top + 2))
lib/libcrypto/ec/ecp_methods.c
1216
kbit = BN_is_bit_set(k, i) ^ pbit;
lib/libcrypto/ecdsa/ecdsa.c
279
BIGNUM *k = NULL, *r = NULL;
lib/libcrypto/ecdsa/ecdsa.c
300
if ((k = BN_new()) == NULL)
lib/libcrypto/ecdsa/ecdsa.c
338
if (!BN_set_bit(k, order_bits) ||
lib/libcrypto/ecdsa/ecdsa.c
346
if (!bn_rand_interval(k, 1, order))
lib/libcrypto/ecdsa/ecdsa.c
350
if (!EC_POINT_mul(group, point, k, NULL, NULL, ctx)) {
lib/libcrypto/ecdsa/ecdsa.c
368
if (BN_mod_inverse_ct(k, k, order, ctx) == NULL) {
lib/libcrypto/ecdsa/ecdsa.c
373
*out_kinv = k;
lib/libcrypto/ecdsa/ecdsa.c
374
k = NULL;
lib/libcrypto/ecdsa/ecdsa.c
385
BN_free(k);
lib/libcrypto/evp/bio_b64.c
155
int ret = 0, i, ii, j, k, x, n, num, ret_code = 0;
lib/libcrypto/evp/bio_b64.c
247
k = EVP_DecodeUpdate(&(ctx->base64),
lib/libcrypto/evp/bio_b64.c
250
if ((k <= 0) && (num == 0) && (ctx->start))
lib/libcrypto/evp/bio_enc.c
406
BIO_set_cipher(BIO *bio, const EVP_CIPHER *c, const unsigned char *k,
lib/libcrypto/evp/bio_enc.c
425
if (!EVP_CipherInit_ex(ctx->cipher_ctx, c, NULL, k, i, e))
lib/libcrypto/evp/evp.h
561
int BIO_set_cipher(BIO *b, const EVP_CIPHER *c, const unsigned char *k,
lib/libcrypto/evp/evp_pbe.c
334
int cplen, j, k, tkeylen, mdlen;
lib/libcrypto/evp/evp_pbe.c
391
for (k = 0; k < cplen; k++)
lib/libcrypto/evp/evp_pbe.c
392
p[k] ^= digtmp[k];
lib/libcrypto/mlkem/mlkem.c
66
uint8_t *k = NULL;
lib/libcrypto/mlkem/mlkem.c
80
if ((k = calloc(1, k_len)) == NULL)
lib/libcrypto/mlkem/mlkem.c
83
if (!mlkem_generate_key_external_entropy(k, private_key, entropy))
lib/libcrypto/mlkem/mlkem.c
88
*out_encoded_public_key = k;
lib/libcrypto/mlkem/mlkem.c
90
k = NULL;
lib/libcrypto/mlkem/mlkem.c
96
freezero(k, k_len);
lib/libcrypto/mlkem/mlkem_internal.c
260
int i, j, k = 0;
lib/libcrypto/mlkem/mlkem_internal.c
266
for (j = k; j < k + offset; j++) {
lib/libcrypto/mlkem/mlkem_internal.c
275
k += 2 * offset;
lib/libcrypto/mlkem/mlkem_internal.c
300
int i, j, k, offset, step = DEGREE / 2;
lib/libcrypto/mlkem/mlkem_internal.c
308
k = 0;
lib/libcrypto/mlkem/mlkem_internal.c
311
for (j = k; j < k + offset; j++) {
lib/libcrypto/mlkem/mlkem_internal.c
319
k += 2 * offset;
lib/libcrypto/pem/pem_lib.c
677
int end = 0, i, k, bl = 0, hl = 0, nohead = 0;
lib/libcrypto/pem/pem_lib.c
819
i = EVP_DecodeFinal(&ctx, (unsigned char *)&(dataB->data[bl]), &k);
lib/libcrypto/pem/pem_lib.c
824
bl += k;
lib/libcrypto/pkcs12/p12_key.c
174
int k;
lib/libcrypto/pkcs12/p12_key.c
177
for (k = v - 1; k >= 0; k--) {
lib/libcrypto/pkcs12/p12_key.c
178
c += I[j + k] + B[k];
lib/libcrypto/pkcs12/p12_key.c
179
I[j + k] = (unsigned char)c;
lib/libcrypto/pkcs7/pk7_smime.c
260
int i, j = 0, k, ret = 0;
lib/libcrypto/pkcs7/pk7_smime.c
311
for (k = 0; k < sk_X509_num(signers); k++) {
lib/libcrypto/pkcs7/pk7_smime.c
312
signer = sk_X509_value (signers, k);
lib/libcrypto/rc2/rc2.c
102
k = (unsigned char *)&(key->data[0]);
lib/libcrypto/rc2/rc2.c
103
*k = 0; /* for if there is a zero length key */
lib/libcrypto/rc2/rc2.c
113
k[i] = data[i];
lib/libcrypto/rc2/rc2.c
116
d = k[len - 1];
lib/libcrypto/rc2/rc2.c
120
d = key_table[(k[j] + d) & 0xff];
lib/libcrypto/rc2/rc2.c
121
k[i] = d;
lib/libcrypto/rc2/rc2.c
130
d = key_table[k[i] & c];
lib/libcrypto/rc2/rc2.c
131
k[i] = d;
lib/libcrypto/rc2/rc2.c
133
d = key_table[k[i + j] ^ d];
lib/libcrypto/rc2/rc2.c
134
k[i] = d;
lib/libcrypto/rc2/rc2.c
140
*(ki--) = ((k[i] << 8)|k[i - 1]) & 0xffff;
lib/libcrypto/rc2/rc2.c
98
unsigned char *k;
lib/libcrypto/rsa/rsa_chk.c
147
r = BN_div_ct(k, NULL, l, m, ctx); /* remainder is 0 */
lib/libcrypto/rsa/rsa_chk.c
153
r = BN_mod_mul(i, key->d, key->e, k, ctx);
lib/libcrypto/rsa/rsa_chk.c
216
BN_free(k);
lib/libcrypto/rsa/rsa_chk.c
61
BIGNUM *i, *j, *k, *l, *m;
lib/libcrypto/rsa/rsa_chk.c
73
k = BN_new();
lib/libcrypto/rsa/rsa_chk.c
77
if (i == NULL || j == NULL || k == NULL || l == NULL || m == NULL ||
lib/libcrypto/rsa/rsa_eay.c
129
int i, j, k, num = 0, r = -1;
lib/libcrypto/rsa/rsa_eay.c
207
for (k = 0; k < num - i; k++)
lib/libcrypto/rsa/rsa_eay.c
208
to[k] = 0;
lib/libcrypto/rsa/rsa_eay.c
309
int i, j, k, num = 0, r = -1;
lib/libcrypto/rsa/rsa_eay.c
419
for (k = 0; k < num - i; k++)
lib/libcrypto/rsa/rsa_eay.c
420
to[k] = 0;
lib/libcrypto/sm2/sm2_crypt.c
254
BIGNUM *k, *x1, *y1, *x2, *y2;
lib/libcrypto/sm2/sm2_crypt.c
316
if ((k = BN_CTX_get(ctx)) == NULL) {
lib/libcrypto/sm2/sm2_crypt.c
349
if (!BN_rand_range(k, order)) {
lib/libcrypto/sm2/sm2_crypt.c
354
if (!EC_POINT_mul(group, kG, k, NULL, NULL, ctx)) {
lib/libcrypto/sm2/sm2_crypt.c
364
if (!EC_POINT_mul(group, kP, NULL, P, k, ctx)) {
lib/libcrypto/sm2/sm2_sign.c
131
if ((k = BN_CTX_get(ctx)) == NULL) {
lib/libcrypto/sm2/sm2_sign.c
159
if (!BN_rand_range(k, order)) {
lib/libcrypto/sm2/sm2_sign.c
164
if (!EC_POINT_mul(group, kG, k, NULL, NULL, ctx)) {
lib/libcrypto/sm2/sm2_sign.c
184
if (!BN_add(rk, r, k)) {
lib/libcrypto/sm2/sm2_sign.c
207
if (!BN_sub(tmp, k, tmp)) {
lib/libcrypto/sm2/sm2_sign.c
97
BIGNUM *k, *rk, *tmp, *x1;
lib/libcrypto/sm4/sm4.c
149
SM4_set_key(const uint8_t *key, SM4_KEY *k)
lib/libcrypto/sm4/sm4.c
151
struct sm4_key *ks = (struct sm4_key *)k;
lib/libcrypto/sm4/sm4.c
181
SM4_encrypt(const uint8_t *in, uint8_t *out, const SM4_KEY *k)
lib/libcrypto/sm4/sm4.c
183
struct sm4_key *ks = (struct sm4_key *)k;
lib/libcrypto/sm4/sm4.c
243
SM4_decrypt(const uint8_t *in, uint8_t *out, const SM4_KEY *k)
lib/libcrypto/sm4/sm4.c
245
struct sm4_key *ks = (struct sm4_key *)k;
lib/libcrypto/x509/by_dir.c
268
int i, j, k;
lib/libcrypto/x509/by_dir.c
318
k = hent->suffix;
lib/libcrypto/x509/by_dir.c
321
k = 0;
lib/libcrypto/x509/by_dir.c
325
k = 0;
lib/libcrypto/x509/by_dir.c
330
ent->dir, h, postfix, k);
lib/libcrypto/x509/by_dir.c
352
k++;
lib/libcrypto/x509/by_dir.c
382
hent->suffix = k;
lib/libcrypto/x509/by_dir.c
390
} else if (hent->suffix < k)
lib/libcrypto/x509/by_dir.c
391
hent->suffix = k;
lib/libcrypto/x509/x509_addr.c
1313
int i, j, k, length;
lib/libcrypto/x509/x509_addr.c
1384
for (k = length - 1; k >= 0 && b_min[k]-- == 0x00; k--)
lib/libcrypto/x509/x509_cmp.c
382
X509_check_private_key(const X509 *x, const EVP_PKEY *k)
lib/libcrypto/x509/x509_cmp.c
390
ret = EVP_PKEY_cmp(xk, k);
lib/libcrypto/x509/x509_policy.c
773
int i, j, k;
lib/libcrypto/x509/x509_policy.c
846
for (k = 0; k < num_parent_policies; k++) {
lib/libcrypto/x509/x509_policy.c
851
k));
lib/libcurses/base/lib_pad.c
261
int k = NewScreen(sp)->_maxx - j;
lib/libcurses/base/lib_pad.c
263
|| pline->text[k] != nline->text[k]) {
lib/libcurses/tinfo/alloc_ttype.c
326
unsigned j, k;
lib/libcurses/tinfo/alloc_ttype.c
339
for (k = total - 1; k > j; k--)
lib/libcurses/tinfo/alloc_ttype.c
340
tp->ext_Names[k] = tp->ext_Names[k - 1];
lib/libcurses/tinfo/alloc_ttype.c
349
for (k = (unsigned) (tp->num_Booleans - 1); k > j; k--)
lib/libcurses/tinfo/alloc_ttype.c
350
tp->Booleans[k] = tp->Booleans[k - 1];
lib/libcurses/tinfo/alloc_ttype.c
356
for (k = (unsigned) (tp->num_Numbers - 1); k > j; k--)
lib/libcurses/tinfo/alloc_ttype.c
357
tp->Numbers[k] = tp->Numbers[k - 1];
lib/libcurses/tinfo/alloc_ttype.c
363
for (k = (unsigned) (tp->num_Strings - 1); k > j; k--)
lib/libcurses/tinfo/alloc_ttype.c
364
tp->Strings[k] = tp->Strings[k - 1];
lib/libcurses/tinfo/alloc_ttype.c
380
int j, k;
lib/libcurses/tinfo/alloc_ttype.c
393
k = _nc_ins_ext_name(to, name, BOOLEAN);
lib/libcurses/tinfo/alloc_ttype.c
394
to->Booleans[k] = FALSE;
lib/libcurses/tinfo/alloc_ttype.c
401
k = _nc_ins_ext_name(to, name, NUMBER);
lib/libcurses/tinfo/alloc_ttype.c
402
to->Numbers[k] = CANCELLED_NUMERIC;
lib/libcurses/tinfo/alloc_ttype.c
409
k = _nc_ins_ext_name(to, name, STRING);
lib/libcurses/tinfo/alloc_ttype.c
410
to->Strings[k] = CANCELLED_STRING;
lib/libcurses/tinfo/db_iterator.c
372
int k = 0;
lib/libcurses/tinfo/db_iterator.c
373
my_list[k++] = my_blob;
lib/libcurses/tinfo/db_iterator.c
376
&& ((&my_blob[j] - my_list[k - 1]) != 3
lib/libcurses/tinfo/db_iterator.c
377
|| !quick_prefix(my_list[k - 1]))) {
lib/libcurses/tinfo/db_iterator.c
379
my_list[k++] = &my_blob[j + 1];
lib/libcurses/tinfo/db_iterator.c
395
for (k = 0; k < j; ++k) {
lib/libcurses/tinfo/db_iterator.c
396
if (!strcmp(my_list[j], my_list[k])) {
lib/libcurses/tinfo/db_iterator.c
398
k = j - 1;
lib/libcurses/tinfo/db_iterator.c
402
j = k;
lib/libcurses/tinfo/db_iterator.c
416
for (k = 0; k < j; ++k) {
lib/libcurses/tinfo/db_iterator.c
417
if (my_stat[j].st_dev == my_stat[k].st_dev
lib/libcurses/tinfo/db_iterator.c
418
&& my_stat[j].st_ino == my_stat[k].st_ino) {
lib/libcurses/tinfo/db_iterator.c
427
k = j;
lib/libcurses/tinfo/db_iterator.c
428
while ((my_list[k] = my_list[k + 1]) != 0) {
lib/libcurses/tinfo/db_iterator.c
429
++k;
lib/libcurses/tinfo/read_termcap.c
1036
int j, k;
lib/libcurses/tinfo/read_termcap.c
1094
for (k = 0; k < j; k++) {
lib/libcurses/tinfo/read_termcap.c
1095
if (test_stat[k].st_dev == test_stat[j].st_dev
lib/libcurses/tinfo/read_termcap.c
1096
&& test_stat[k].st_ino == test_stat[j].st_ino) {
lib/libcurses/tinfo/read_termcap.c
1104
for (k = j + 1; k < filecount; k++) {
lib/libcurses/tinfo/read_termcap.c
1105
termpaths[k - 1] = termpaths[k];
lib/libcurses/tinfo/read_termcap.c
1106
test_stat[k - 1] = test_stat[k];
lib/libcurses/tinfo/trim_sgr0.c
251
size_t i, j, k;
lib/libcurses/tinfo/trim_sgr0.c
272
k = strlen(exit_alt_charset_mode);
lib/libcurses/tinfo/trim_sgr0.c
273
if (j > k) {
lib/libcurses/tinfo/trim_sgr0.c
274
for (i = 0; i <= (j - k); ++i) {
lib/libcurses/trace/visbuf.c
223
int j = wctomb(temp, c), k;
lib/libcurses/trace/visbuf.c
229
for (k = 0; k < j; ++k) {
lib/libcurses/trace/visbuf.c
230
tp = VisChar(tp, UChar(temp[k]), WideLen(len));
lib/libcurses/trace/visbuf.c
331
int k;
lib/libcurses/trace/visbuf.c
351
for (k = 0; k < PUTC_n; k++) {
lib/libcurses/trace/visbuf.c
352
VisChar(temp, UChar(PUTC_buf[k]), sizeof(temp));
lib/libcurses/tty/tty_update.c
844
int j, k;
lib/libcurses/tty/tty_update.c
876
for (k = 1; k <= magic_cookie_glitch; k++) {
lib/libcurses/tty/tty_update.c
877
if (j - k < 0
lib/libcurses/tty/tty_update.c
878
|| !ISBLANK(thisline[j - k])
lib/libcurses/tty/tty_update.c
879
|| !SAFE(SP_PARM, AttrOf(thisline[j - k]))) {
lib/libcurses/tty/tty_update.c
882
i, j - k,
lib/libcurses/tty/tty_update.c
883
(ISBLANK(thisline[j - k])
lib/libcurses/tty/tty_update.c
886
(SAFE(SP_PARM, AttrOf(thisline[j - k]))
lib/libcurses/tty/tty_update.c
932
for (k = 1; k <= magic_cookie_glitch; k++) {
lib/libcurses/tty/tty_update.c
933
if (n + k >= screen_columns(SP_PARM)
lib/libcurses/tty/tty_update.c
934
|| !ISBLANK(lastline[n + k])
lib/libcurses/tty/tty_update.c
935
|| !SAFE(SP_PARM, AttrOf(lastline[n + k]))) {
lib/libcurses/tty/tty_update.c
939
i, j - k,
lib/libcurses/tty/tty_update.c
940
(ISBLANK(lastline[n + k])
lib/libcurses/tty/tty_update.c
943
(SAFE(SP_PARM, AttrOf(lastline[n + k]))
lib/libcurses/tty/tty_update.c
979
for (k = 1; k <= magic_cookie_glitch; k++)
lib/libcurses/tty/tty_update.c
980
AddAttr(thisline[j - k], turnon);
lib/libcurses/widechar/lib_in_wchnstr.c
57
int j, k, limit;
lib/libcurses/widechar/lib_in_wchnstr.c
68
for (j = k = 0; j < n; ++j) {
lib/libcurses/widechar/lib_in_wchnstr.c
70
wchstr[k++] = src[j];
lib/libcurses/widechar/lib_in_wchnstr.c
73
memset(&(wchstr[k]), 0, sizeof(*wchstr));
lib/libedit/chared.c
82
c_kill_t *k = &el->el_chared.c_kill;
lib/libedit/chared.c
84
(void)memcpy(k->buf, ptr, size * sizeof(*k->buf));
lib/libedit/chared.c
85
k->last = k->buf + size;
lib/libedit/keymacro.c
467
node__free(keymacro_node_t *k)
lib/libedit/keymacro.c
469
if (k == NULL)
lib/libedit/keymacro.c
471
node__free(k->sibling);
lib/libedit/keymacro.c
472
node__free(k->next);
lib/libedit/keymacro.c
473
free(k);
lib/libedit/readline.c
2255
rl_set_keymap(Keymap k)
lib/libedit/readline.c
2260
rl_generic_bind(int type, const char * keyseq, const char * data, Keymap k)
lib/libedit/readline.c
2266
rl_bind_key_in_map(int key, rl_command_func_t *fun, Keymap k)
lib/libedit/vi.c
102
k->buf);
lib/libedit/vi.c
113
(void) memcpy(el->el_line.cursor, k->buf, len *
lib/libedit/vi.c
95
c_kill_t *k = &el->el_chared.c_kill;
lib/libedit/vi.c
96
size_t len = (size_t)(k->last - k->buf);
lib/libedit/vi.c
98
if (k->buf == NULL || len == 0)
lib/libexpat/lib/siphash.h
142
uint64_t k[2];
lib/libexpat/lib/siphash.h
145
#define sip_keyof(k) sip_tokey(&(struct sipkey){{0}}, (k))
lib/libexpat/lib/siphash.h
149
key->k[0] = SIP_U8TO64_LE((const unsigned char *)src);
lib/libexpat/lib/siphash.h
150
key->k[1] = SIP_U8TO64_LE((const unsigned char *)src + 8);
lib/libexpat/lib/siphash.h
193
H->v0 = SIP_ULL(0x736f6d65U, 0x70736575U) ^ key->k[0];
lib/libexpat/lib/siphash.h
194
H->v1 = SIP_ULL(0x646f7261U, 0x6e646f6dU) ^ key->k[1];
lib/libexpat/lib/siphash.h
195
H->v2 = SIP_ULL(0x6c796765U, 0x6e657261U) ^ key->k[0];
lib/libexpat/lib/siphash.h
196
H->v3 = SIP_ULL(0x74656462U, 0x79746573U) ^ key->k[1];
lib/libexpat/lib/siphash.h
359
struct sipkey k;
lib/libexpat/lib/siphash.h
362
sip_tokey(&k, "\000\001\002\003\004\005\006\007\010\011"
lib/libexpat/lib/siphash.h
368
if (siphash24(in, i, &k) != SIP_U8TO64_LE(vectors[i]))
lib/libexpat/lib/xmlparse.c
1108
label, (unsigned long long)entropy_128.k[0],
lib/libexpat/lib/xmlparse.c
1109
(unsigned long long)entropy_128.k[1]);
lib/libexpat/lib/xmlparse.c
1148
entropy.k[0] = 0;
lib/libexpat/lib/xmlparse.c
1149
entropy.k[1] = gather_time_entropy();
lib/libexpat/lib/xmlparse.c
1152
entropy.k[1] ^= getpid();
lib/libexpat/lib/xmlparse.c
1157
entropy.k[1] *= 2147483647;
lib/libexpat/lib/xmlparse.c
1160
entropy.k[1] *= 2305843009213693951ULL;
lib/libexpat/lib/xmlparse.c
1541
parser->m_hash_secret_salt_128.k[0] = 0;
lib/libexpat/lib/xmlparse.c
1542
parser->m_hash_secret_salt_128.k[1] = 0;
lib/libexpat/lib/xmlparse.c
2244
rootParser->m_hash_secret_salt_128.k[0] = 0;
lib/libexpat/lib/xmlparse.c
2245
rootParser->m_hash_secret_salt_128.k[1] = hash_salt;
lib/libfido2/src/eddsa.c
143
eddsa_pk_to_EVP_PKEY(const eddsa_pk_t *k)
lib/libfido2/src/eddsa.c
147
if ((pkey = EVP_PKEY_new_raw_public_key(EVP_PKEY_ED25519, NULL, k->x,
lib/libfido2/src/eddsa.c
148
sizeof(k->x))) == NULL)
lib/libfido2/src/eddsa.c
77
eddsa_pk_t *k = arg;
lib/libfido2/src/eddsa.c
85
return (decode_coord(val, &k->x, sizeof(k->x)));
lib/libfido2/src/eddsa.c
92
eddsa_pk_decode(const cbor_item_t *item, eddsa_pk_t *k)
lib/libfido2/src/eddsa.c
96
cbor_map_iter(item, k, decode_pubkey_point) < 0) {
lib/libfido2/src/es256.c
225
EVP_PKEY *k = NULL;
lib/libfido2/src/es256.c
240
EVP_PKEY_keygen_init(kctx) <= 0 || EVP_PKEY_keygen(kctx, &k) <= 0) {
lib/libfido2/src/es256.c
245
if ((ec = EVP_PKEY_get0_EC_KEY(k)) == NULL ||
lib/libfido2/src/es256.c
257
if (k != NULL)
lib/libfido2/src/es256.c
258
EVP_PKEY_free(k);
lib/libfido2/src/es256.c
268
es256_pk_to_EVP_PKEY(const es256_pk_t *k)
lib/libfido2/src/es256.c
288
if (BN_bin2bn(k->x, sizeof(k->x), x) == NULL ||
lib/libfido2/src/es256.c
289
BN_bin2bn(k->y, sizeof(k->y), y) == NULL) {
lib/libfido2/src/es256.c
40
es256_pk_t *k = arg;
lib/libfido2/src/es256.c
408
es256_sk_to_EVP_PKEY(const es256_sk_t *k)
lib/libfido2/src/es256.c
422
BN_bin2bn(k->d, sizeof(k->d), d) == NULL) {
lib/libfido2/src/es256.c
48
return (decode_coord(val, &k->x, sizeof(k->x)));
lib/libfido2/src/es256.c
50
return (decode_coord(val, &k->y, sizeof(k->y)));
lib/libfido2/src/es256.c
57
es256_pk_decode(const cbor_item_t *item, es256_pk_t *k)
lib/libfido2/src/es256.c
61
cbor_map_iter(item, k, decode_pubkey_point) < 0) {
lib/libfido2/src/rs256.c
117
rs256_pk_to_EVP_PKEY(const rs256_pk_t *k)
lib/libfido2/src/rs256.c
128
if (BN_bin2bn(k->n, sizeof(k->n), n) == NULL ||
lib/libfido2/src/rs256.c
129
BN_bin2bn(k->e, sizeof(k->e), e) == NULL) {
lib/libfido2/src/rs256.c
178
int k;
lib/libfido2/src/rs256.c
192
if ((k = BN_num_bytes(n)) < 0 || (size_t)k > sizeof(pk->n) ||
lib/libfido2/src/rs256.c
193
(k = BN_num_bytes(e)) < 0 || (size_t)k > sizeof(pk->e)) {
lib/libfido2/src/rs256.c
198
if ((k = BN_bn2bin(n, pk->n)) < 0 || (size_t)k > sizeof(pk->n) ||
lib/libfido2/src/rs256.c
199
(k = BN_bn2bin(e, pk->e)) < 0 || (size_t)k > sizeof(pk->e)) {
lib/libfido2/src/rs256.c
49
rs256_pk_t *k = arg;
lib/libfido2/src/rs256.c
57
return (decode_bignum(val, &k->n, sizeof(k->n)));
lib/libfido2/src/rs256.c
59
return (decode_bignum(val, &k->e, sizeof(k->e)));
lib/libfido2/src/rs256.c
66
rs256_pk_decode(const cbor_item_t *item, rs256_pk_t *k)
lib/libfido2/src/rs256.c
70
cbor_map_iter(item, k, decode_rsa_pubkey) < 0) {
lib/libfuse/dict.c
38
dict_check(struct dict *d, const char *k)
lib/libfuse/dict.c
42
if (strlcpy(key.key, k, sizeof key.key) >= sizeof key.key)
lib/libfuse/dict.c
43
errx(1, "dict_check(%p, %s): key too large", d, k);
lib/libfuse/dict.c
49
dict_set(struct dict *d, const char *k, void *data)
lib/libfuse/dict.c
53
if (strlcpy(key.key, k, sizeof key.key) >= sizeof key.key)
lib/libfuse/dict.c
54
errx(1, "dict_set(%p, %s): key too large", d, k);
lib/libfuse/dict.c
60
strlcpy(entry->key, k, sizeof entry->key);
lib/libfuse/dict.c
70
dict_get(struct dict *d, const char *k)
lib/libfuse/dict.c
74
if (strlcpy(key.key, k, sizeof key.key) >= sizeof key.key)
lib/libfuse/dict.c
75
errx(1, "dict_get(%p, %s): key too large", d, k);
lib/libfuse/dict.c
83
dict_pop(struct dict *d, const char *k)
lib/libfuse/dict.c
88
if (strlcpy(key.key, k, sizeof key.key) >= sizeof key.key)
lib/libfuse/dict.c
89
errx(1, "dict_pop(%p, %s): key too large", d, k);
lib/libfuse/fuse_opt.h
51
#define FUSE_OPT_KEY(t, k) { t, (unsigned long)-1, k }
lib/libkeynote/keynote-keygen.c
70
int i, k;
lib/libkeynote/keynote-keygen.c
75
for (i = 0, k = strlen(algname) + 2; i < strlen(key); i++, k++)
lib/libkeynote/keynote-keygen.c
77
if (k == length)
lib/libkeynote/keynote-keygen.c
88
k = 0;
lib/libkeynote/keynote.y
871
get_kth(int k)
lib/libkeynote/keynote.y
877
k -= keynote_kth_array[i];
lib/libkeynote/keynote.y
879
if (k <= 0)
lib/libkeynote/parse_assertion.c
370
int k, i, j, seen_field = 0, ver = 0, end_of_assertion = 0;
lib/libkeynote/parse_assertion.c
600
for (k = 1; te + k < as->as_buf + len && *(te + k) != '\n'; k++)
lib/libkeynote/parse_assertion.c
601
if (!isspace((unsigned char)*(te + k)))
lib/libm/src/b_exp__D.c
100
hi=(x-k*ln2hi); /* Exact. */
lib/libm/src/b_exp__D.c
101
x= hi - (lo = k*ln2lo-c);
lib/libm/src/b_exp__D.c
107
return scalb(1.+(hi-(lo - c)), k);
lib/libm/src/b_exp__D.c
87
int k;
lib/libm/src/b_exp__D.c
96
k = z + copysign(.5, x);
lib/libm/src/e_atan2.c
104
k = (iy-ix)>>20;
lib/libm/src/e_atan2.c
105
if(k > 60) z=pi_o_2+0.5*pi_lo; /* |y/x| > 2**60 */
lib/libm/src/e_atan2.c
106
else if(hx<0&&k<-60) z=0.0; /* |y|/x < -2**60 */
lib/libm/src/e_atan2.c
57
int32_t k,m,hx,hy,ix,iy;
lib/libm/src/e_atan2f.c
31
int32_t k,m,hx,hy,ix,iy;
lib/libm/src/e_atan2f.c
77
k = (iy-ix)>>23;
lib/libm/src/e_atan2f.c
78
if(k > 60) z=pi_o_2+(float)0.5*pi_lo; /* |y/x| > 2**60 */
lib/libm/src/e_atan2f.c
79
else if(hx<0&&k<-60) z=0.0; /* |y|/x < -2**60 */
lib/libm/src/e_atan2l.c
149
k = expty-exptx;
lib/libm/src/e_atan2l.c
150
if(k > LDBL_MANT_DIG+2) { /* |y/x| huge */
lib/libm/src/e_atan2l.c
154
else if(expsignx<0&&k<-LDBL_MANT_DIG-2) z=0.0; /* |y/x| tiny, x<0 */
lib/libm/src/e_atan2l.c
59
int32_t k,m;
lib/libm/src/e_exp.c
104
int32_t k,xsb;
lib/libm/src/e_exp.c
127
hi = x-ln2HI[xsb]; lo=ln2LO[xsb]; k = 1-xsb-xsb;
lib/libm/src/e_exp.c
129
k = invln2*x+halF[xsb];
lib/libm/src/e_exp.c
130
t = k;
lib/libm/src/e_exp.c
139
else k = 0;
lib/libm/src/e_exp.c
144
if(k==0) return one-((x*c)/(c-2.0)-x);
lib/libm/src/e_exp.c
146
if(k >= -1021) {
lib/libm/src/e_exp.c
149
SET_HIGH_WORD(y,hy+(k<<20)); /* add k to y's exponent */
lib/libm/src/e_exp.c
154
SET_HIGH_WORD(y,hy+((k+1000)<<20)); /* add k to y's exponent */
lib/libm/src/e_expf.c
42
int32_t k,xsb;
lib/libm/src/e_expf.c
48
k = 0;
lib/libm/src/e_expf.c
63
hi = x-ln2HI[xsb]; lo=ln2LO[xsb]; k = 1-xsb-xsb;
lib/libm/src/e_expf.c
65
k = invln2*x+halF[xsb];
lib/libm/src/e_expf.c
66
t = k;
lib/libm/src/e_expf.c
79
if(k==0) return one-((x*c)/(c-(float)2.0)-x);
lib/libm/src/e_expf.c
81
if(k >= -125) {
lib/libm/src/e_expf.c
84
SET_FLOAT_WORD(y,hy+(k<<23)); /* add k to y's exponent */
lib/libm/src/e_expf.c
89
SET_FLOAT_WORD(y,hy+((k+100)<<23)); /* add k to y's exponent */
lib/libm/src/e_hypot.c
115
if(k!=0) {
lib/libm/src/e_hypot.c
119
SET_HIGH_WORD(t1,high+(k<<20));
lib/libm/src/e_hypot.c
54
int32_t j,k,ha,hb;
lib/libm/src/e_hypot.c
64
k=0;
lib/libm/src/e_hypot.c
76
ha -= 0x25800000; hb -= 0x25800000; k += 600;
lib/libm/src/e_hypot.c
89
k -= 1022;
lib/libm/src/e_hypot.c
93
k -= 600;
lib/libm/src/e_hypotf.c
23
int32_t j,k,ha,hb;
lib/libm/src/e_hypotf.c
33
k=0;
lib/libm/src/e_hypotf.c
42
ha -= 0x22000000; hb -= 0x22000000; k += 68;
lib/libm/src/e_hypotf.c
52
k -= 126;
lib/libm/src/e_hypotf.c
56
k -= 68;
lib/libm/src/e_hypotf.c
75
if(k!=0) {
lib/libm/src/e_hypotf.c
76
SET_FLOAT_WORD(t1,0x3f800000+(k<<23));
lib/libm/src/e_jn.c
152
double q0,q1,h,tmp; int32_t k,m;
lib/libm/src/e_jn.c
154
q0 = w; z = w+h; q1 = w*z - 1.0; k=1;
lib/libm/src/e_jn.c
156
k += 1; z += h;
lib/libm/src/e_jn.c
162
for(t=zero, i = 2*(n+k); i>=m; i -= 2) t = one/(i/x-t);
lib/libm/src/e_jnf.c
105
float q0,q1,h,tmp; int32_t k,m;
lib/libm/src/e_jnf.c
107
q0 = w; z = w+h; q1 = w*z - (float)1.0; k=1;
lib/libm/src/e_jnf.c
109
k += 1; z += h;
lib/libm/src/e_jnf.c
115
for(t=zero, i = 2*(n+k); i>=m; i -= 2) t = one/(i/x-t);
lib/libm/src/e_log.c
101
k += (hx>>20)-1023;
lib/libm/src/e_log.c
105
k += (i>>20);
lib/libm/src/e_log.c
108
if(f==zero) if(k==0) return zero; else {dk=(double)k;
lib/libm/src/e_log.c
111
if(k==0) return f-R; else {dk=(double)k;
lib/libm/src/e_log.c
115
dk = (double)k;
lib/libm/src/e_log.c
126
if(k==0) return f-(hfsq-s*(hfsq+R)); else
lib/libm/src/e_log.c
129
if(k==0) return f-s*(f-R); else
lib/libm/src/e_log.c
87
int32_t k,hx,i,j;
lib/libm/src/e_log.c
92
k=0;
lib/libm/src/e_log.c
97
k -= 54; x *= two54; /* subnormal number, scale up x */
lib/libm/src/e_log10.c
63
int32_t i,k,hx;
lib/libm/src/e_log10.c
68
k=0;
lib/libm/src/e_log10.c
73
k -= 54; x *= two54; /* subnormal number, scale up x */
lib/libm/src/e_log10.c
77
k += (hx>>20)-1023;
lib/libm/src/e_log10.c
78
i = ((u_int32_t)k&0x80000000)>>31;
lib/libm/src/e_log10.c
80
y = (double)(k+i);
lib/libm/src/e_log10f.c
31
int32_t i,k,hx;
lib/libm/src/e_log10f.c
35
k=0;
lib/libm/src/e_log10f.c
40
k -= 25; x *= two25; /* subnormal number, scale up x */
lib/libm/src/e_log10f.c
44
k += (hx>>23)-127;
lib/libm/src/e_log10f.c
45
i = ((u_int32_t)k&0x80000000)>>31;
lib/libm/src/e_log10f.c
47
y = (float)(k+i);
lib/libm/src/e_log2.c
35
int32_t k,hx,i,j;
lib/libm/src/e_log2.c
40
k=0;
lib/libm/src/e_log2.c
45
k -= 54; x *= two54; /* subnormal number, scale up x */
lib/libm/src/e_log2.c
49
k += (hx>>20)-1023;
lib/libm/src/e_log2.c
53
k += (i>>20);
lib/libm/src/e_log2.c
55
dk = (double)k;
lib/libm/src/e_log2f.c
36
int32_t k,ix,i,j;
lib/libm/src/e_log2f.c
40
k=0;
lib/libm/src/e_log2f.c
45
k -= 25; x *= two25; /* subnormal number, scale up x */
lib/libm/src/e_log2f.c
49
k += (ix>>23)-127;
lib/libm/src/e_log2f.c
53
k += (i>>23);
lib/libm/src/e_log2f.c
54
dk = (float)k;
lib/libm/src/e_logf.c
37
int32_t k,ix,i,j;
lib/libm/src/e_logf.c
41
k=0;
lib/libm/src/e_logf.c
46
k -= 25; x *= two25; /* subnormal number, scale up x */
lib/libm/src/e_logf.c
50
k += (ix>>23)-127;
lib/libm/src/e_logf.c
54
k += (i>>23);
lib/libm/src/e_logf.c
57
if(f==zero) {if(k==0) return zero; else {dk=(float)k;
lib/libm/src/e_logf.c
60
if(k==0) return f-R; else {dk=(float)k;
lib/libm/src/e_logf.c
64
dk = (float)k;
lib/libm/src/e_logf.c
75
if(k==0) return f-(hfsq-s*(hfsq+R)); else
lib/libm/src/e_logf.c
78
if(k==0) return f-s*(f-R); else
lib/libm/src/e_pow.c
101
int32_t i,j,k,yisint,n;
lib/libm/src/e_pow.c
129
k = (iy>>20)-0x3ff; /* exponent */
lib/libm/src/e_pow.c
130
if(k>20) {
lib/libm/src/e_pow.c
131
j = ly>>(52-k);
lib/libm/src/e_pow.c
132
if((j<<(52-k))==ly) yisint = 2-(j&1);
lib/libm/src/e_pow.c
134
j = iy>>(20-k);
lib/libm/src/e_pow.c
135
if((j<<(20-k))==iy) yisint = 2-(j&1);
lib/libm/src/e_pow.c
212
if(j<=0x3988E) k=0; /* |x|<sqrt(3/2) */
lib/libm/src/e_pow.c
213
else if(j<0xBB67A) k=1; /* |x|<sqrt(3) */
lib/libm/src/e_pow.c
214
else {k=0;n+=1;ix -= 0x00100000;}
lib/libm/src/e_pow.c
218
u = ax-bp[k]; /* bp[0]=1.0, bp[1]=1.5 */
lib/libm/src/e_pow.c
219
v = one/(ax+bp[k]);
lib/libm/src/e_pow.c
225
SET_HIGH_WORD(t_h,((ix>>1)|0x20000000)+0x00080000+(k<<18));
lib/libm/src/e_pow.c
226
t_l = ax - (t_h-bp[k]);
lib/libm/src/e_pow.c
244
z_l = cp_l*p_h+p_l*cp+dp_l[k];
lib/libm/src/e_pow.c
247
t1 = (((z_h+z_l)+dp_h[k])+t);
lib/libm/src/e_pow.c
249
t2 = z_l-(((t1-t)-dp_h[k])-z_h);
lib/libm/src/e_pow.c
276
k = (i>>20)-0x3ff;
lib/libm/src/e_pow.c
279
n = j+(0x00100000>>(k+1));
lib/libm/src/e_pow.c
280
k = ((n&0x7fffffff)>>20)-0x3ff; /* new k for n */
lib/libm/src/e_pow.c
282
SET_HIGH_WORD(t,n&~(0x000fffff>>k));
lib/libm/src/e_pow.c
283
n = ((n&0x000fffff)|0x00100000)>>(20-k);
lib/libm/src/e_powf.c
150
if(j<=0x1cc471) k=0; /* |x|<sqrt(3/2) */
lib/libm/src/e_powf.c
151
else if(j<0x5db3d7) k=1; /* |x|<sqrt(3) */
lib/libm/src/e_powf.c
152
else {k=0;n+=1;ix -= 0x00800000;}
lib/libm/src/e_powf.c
156
u = ax-bp[k]; /* bp[0]=1.0, bp[1]=1.5 */
lib/libm/src/e_powf.c
157
v = one/(ax+bp[k]);
lib/libm/src/e_powf.c
163
SET_FLOAT_WORD(t_h,((ix>>1)|0x20000000)+0x0040000+(k<<21));
lib/libm/src/e_powf.c
164
t_l = ax - (t_h-bp[k]);
lib/libm/src/e_powf.c
184
z_l = cp_l*p_h+p_l*cp+dp_l[k];
lib/libm/src/e_powf.c
187
t1 = (((z_h+z_l)+dp_h[k])+t);
lib/libm/src/e_powf.c
190
t2 = z_l-(((t1-t)-dp_h[k])-z_h);
lib/libm/src/e_powf.c
218
k = (i>>23)-0x7f;
lib/libm/src/e_powf.c
221
n = j+(0x00800000>>(k+1));
lib/libm/src/e_powf.c
222
k = ((n&0x7fffffff)>>23)-0x7f; /* new k for n */
lib/libm/src/e_powf.c
223
SET_FLOAT_WORD(t,n&~(0x007fffff>>k));
lib/libm/src/e_powf.c
224
n = ((n&0x007fffff)|0x00800000)>>(23-k);
lib/libm/src/e_powf.c
57
int32_t i,j,k,yisint,n;
lib/libm/src/e_powf.c
84
k = (iy>>23)-0x7f; /* exponent */
lib/libm/src/e_powf.c
85
j = iy>>(23-k);
lib/libm/src/e_powf.c
86
if((j<<(23-k))==iy) yisint = 2-(j&1);
lib/libm/src/e_sqrtl.c
144
int k, r;
lib/libm/src/e_sqrtl.c
173
k = -514;
lib/libm/src/e_sqrtl.c
175
k = 0;
lib/libm/src/e_sqrtl.c
182
k += u.bits.ext_exp - 0x3fff; /* 2k = n - 1. */
lib/libm/src/e_sqrtl.c
185
k += u.bits.ext_exp - 0x4000; /* 2k = n - 2. */
lib/libm/src/e_sqrtl.c
205
u.bits.ext_exp += (k >> 1) - 1;
lib/libm/src/k_rem_pio2.c
287
int32_t jz,jx,jv,jp,jk,carry,n,iq[20],i,j,k,m,q0,ih;
lib/libm/src/k_rem_pio2.c
360
for(k=1;iq[jk-k]==0;k++); /* k = no. of terms needed */
lib/libm/src/k_rem_pio2.c
362
for(i=jz+1;i<=jz+k;i++) { /* add q[jz+1] to q[jz+k] */
lib/libm/src/k_rem_pio2.c
367
jz += k;
lib/libm/src/k_rem_pio2.c
394
for(fw=0.0,k=0;k<=jp&&k<=jz-i;k++) fw += PIo2[k]*q[i+k];
lib/libm/src/k_rem_pio2f.c
121
for(k=1;iq[jk-k]==0;k++); /* k = no. of terms needed */
lib/libm/src/k_rem_pio2f.c
123
for(i=jz+1;i<=jz+k;i++) { /* add q[jz+1] to q[jz+k] */
lib/libm/src/k_rem_pio2f.c
128
jz += k;
lib/libm/src/k_rem_pio2f.c
155
for(fw=0.0,k=0;k<=jp&&k<=jz-i;k++) fw += PIo2[k]*q[i+k];
lib/libm/src/k_rem_pio2f.c
48
int32_t jz,jx,jv,jp,jk,carry,n,iq[20],i,j,k,m,q0,ih;
lib/libm/src/ld128/e_hypotl.c
115
if(k!=0) {
lib/libm/src/ld128/e_hypotl.c
119
SET_LDOUBLE_MSW64(t1,high+(k<<48));
lib/libm/src/ld128/e_hypotl.c
53
int64_t j,k,ha,hb;
lib/libm/src/ld128/e_hypotl.c
63
k=0;
lib/libm/src/ld128/e_hypotl.c
76
hb -= 0x2580000000000000LL; k += 9600;
lib/libm/src/ld128/e_hypotl.c
89
k -= 16382;
lib/libm/src/ld128/e_hypotl.c
93
k -= 9600;
lib/libm/src/ld128/e_logl.c
195
int k, e;
lib/libm/src/ld128/e_logl.c
201
k = m & 0x7fffffff;
lib/libm/src/ld128/e_logl.c
203
if ((k | u.parts32.mswlo | u.parts32.lswhi | u.parts32.lswlo) == 0)
lib/libm/src/ld128/e_logl.c
213
if (k >= 0x7fff0000)
lib/libm/src/ld128/e_logl.c
226
k = (m - 0xff00) >> 9;
lib/libm/src/ld128/e_logl.c
229
t.parts32.mswhi = 0x3fff0000 + (k << 9);
lib/libm/src/ld128/e_logl.c
235
k += 64;
lib/libm/src/ld128/e_logl.c
239
k = (m - 0xfe00) >> 10;
lib/libm/src/ld128/e_logl.c
240
t.parts32.mswhi = 0x3ffe0000 + (k << 10);
lib/libm/src/ld128/e_logl.c
249
k = 64;
lib/libm/src/ld128/e_logl.c
279
y += logtbl[k-26]; /* log(t) - (t-1) */
lib/libm/src/ld128/e_powl.c
149
int32_t i, j, k, yisint, n;
lib/libm/src/ld128/e_powl.c
295
k = 0; /* |x|<sqrt(3/2) */
lib/libm/src/ld128/e_powl.c
297
k = 1; /* |x|<sqrt(3) */
lib/libm/src/ld128/e_powl.c
300
k = 0;
lib/libm/src/ld128/e_powl.c
310
u = ax - bp[k]; /* bp[0]=1.0, bp[1]=1.5 */
lib/libm/src/ld128/e_powl.c
311
v = one / (ax + bp[k]);
lib/libm/src/ld128/e_powl.c
320
t_h = ax + bp[k];
lib/libm/src/ld128/e_powl.c
325
t_l = ax - (t_h - bp[k]);
lib/libm/src/ld128/e_powl.c
351
z_l = cp_l * p_h + p_l * cp + dp_l[k];
lib/libm/src/ld128/e_powl.c
354
t1 = (((z_h + z_l) + dp_h[k]) + t);
lib/libm/src/ld128/e_powl.c
359
t2 = z_l - (((t1 - t) - dp_h[k]) - z_h);
lib/libm/src/ld128/e_powl.c
404
k = (i >> 16) - 0x3fff;
lib/libm/src/ld128/s_cbrtl.c
36
int k;
lib/libm/src/ld128/s_cbrtl.c
39
k = (hx>>48)&0x7fff;
lib/libm/src/ld128/s_cbrtl.c
45
if (k == BIAS + LDBL_MAX_EXP)
lib/libm/src/ld128/s_cbrtl.c
48
if (k == 0) {
lib/libm/src/ld128/s_cbrtl.c
57
k = (hx>>48)&0x7fff;
lib/libm/src/ld128/s_cbrtl.c
58
k -= BIAS + 514;
lib/libm/src/ld128/s_cbrtl.c
60
k -= BIAS;
lib/libm/src/ld128/s_cbrtl.c
66
switch (k % 3) {
lib/libm/src/ld128/s_cbrtl.c
70
k--;
lib/libm/src/ld128/s_cbrtl.c
75
k -= 2;
lib/libm/src/ld128/s_cbrtl.c
79
expsign = ((hx>>48) & 0x8000) | (BIAS + k / 3);
lib/libm/src/ld128/s_exp2l.c
363
int k;
lib/libm/src/ld128/s_exp2l.c
406
k = (int)i0 >> TBLBITS;
lib/libm/src/ld128/s_exp2l.c
414
if (k >= LDBL_MIN_EXP) {
lib/libm/src/ld128/s_exp2l.c
415
es = LDBL_MAX_EXP - 1 + k;
lib/libm/src/ld128/s_exp2l.c
420
es = LDBL_MAX_EXP - 1 + k + 10000;
lib/libm/src/ld128/s_exp2l.c
433
if(k >= LDBL_MIN_EXP) {
lib/libm/src/ld128/s_exp2l.c
434
if (k == LDBL_MAX_EXP)
lib/libm/src/ld128/s_expm1l.c
136
k = px;
lib/libm/src/ld128/s_expm1l.c
159
px = ldexpl (1.0L, k);
lib/libm/src/ld128/s_expm1l.c
99
int k;
lib/libm/src/ld80/e_hypotl.c
115
if(k!=0) {
lib/libm/src/ld80/e_hypotl.c
119
SET_LDOUBLE_EXP(t1,es+k);
lib/libm/src/ld80/e_hypotl.c
53
u_int32_t j,k,ea,eb;
lib/libm/src/ld80/e_hypotl.c
63
k=0;
lib/libm/src/ld80/e_hypotl.c
75
ea -= 0x2580; eb -= 0x2580; k += 9600;
lib/libm/src/ld80/e_hypotl.c
87
k -= 16382;
lib/libm/src/ld80/e_hypotl.c
91
k -= 9600;
lib/libm/src/ld80/e_powl.c
171
#define douba(k) A[k]
lib/libm/src/ld80/e_powl.c
172
#define doubb(k) B[k]
lib/libm/src/ld80/s_cbrtl.c
36
int k;
lib/libm/src/ld80/s_cbrtl.c
40
k = expsign & 0x7fff;
lib/libm/src/ld80/s_cbrtl.c
46
if (k == BIAS + LDBL_MAX_EXP)
lib/libm/src/ld80/s_cbrtl.c
49
if (k == 0) {
lib/libm/src/ld80/s_cbrtl.c
57
GET_LDOUBLE_EXP(k,x);
lib/libm/src/ld80/s_cbrtl.c
58
k &= 0x7fff;
lib/libm/src/ld80/s_cbrtl.c
59
k -= BIAS + 514;
lib/libm/src/ld80/s_cbrtl.c
61
k -= BIAS;
lib/libm/src/ld80/s_cbrtl.c
65
switch (k % 3) {
lib/libm/src/ld80/s_cbrtl.c
69
k--;
lib/libm/src/ld80/s_cbrtl.c
74
k -= 2;
lib/libm/src/ld80/s_cbrtl.c
77
SET_LDOUBLE_EXP(v, (expsign & 0x8000) | (BIAS + k / 3));
lib/libm/src/ld80/s_exp2l.c
217
int k;
lib/libm/src/ld80/s_exp2l.c
255
k = (int)i0 >> TBLBITS;
lib/libm/src/ld80/s_exp2l.c
263
if (k >= LDBL_MIN_EXP) {
lib/libm/src/ld80/s_exp2l.c
264
es = LDBL_MAX_EXP - 1 + k;
lib/libm/src/ld80/s_exp2l.c
269
es = LDBL_MAX_EXP - 1 + k + 10000;
lib/libm/src/ld80/s_exp2l.c
283
if (k >= LDBL_MIN_EXP) {
lib/libm/src/ld80/s_exp2l.c
284
if (k == LDBL_MAX_EXP)
lib/libm/src/ld80/s_expm1l.c
110
k = px;
lib/libm/src/ld80/s_expm1l.c
135
px = ldexpl(1.0L, k);
lib/libm/src/ld80/s_expm1l.c
93
int k;
lib/libm/src/s_exp2.c
343
int k;
lib/libm/src/s_exp2.c
368
k = (i0 >> TBLBITS) << 20;
lib/libm/src/s_exp2.c
376
if (k >= -(1021 << 20))
lib/libm/src/s_exp2.c
377
INSERT_WORDS(twopk, 0x3ff00000 + k, 0);
lib/libm/src/s_exp2.c
379
INSERT_WORDS(twopkp1000, 0x3ff00000 + k + (1000 << 20), 0);
lib/libm/src/s_exp2.c
383
if(k >= -(1021 << 20)) {
lib/libm/src/s_exp2.c
384
if (k == 1024 << 20)
lib/libm/src/s_exp2f.c
121
k = (i0 >> TBLBITS) << 20;
lib/libm/src/s_exp2f.c
125
INSERT_WORDS(twopk, 0x3ff00000 + k, 0);
lib/libm/src/s_exp2f.c
97
int32_t k;
lib/libm/src/s_expm1.c
132
int32_t k,xsb;
lib/libm/src/s_expm1.c
162
{hi = x - ln2_hi; lo = ln2_lo; k = 1;}
lib/libm/src/s_expm1.c
164
{hi = x + ln2_hi; lo = -ln2_lo; k = -1;}
lib/libm/src/s_expm1.c
166
k = invln2*x+((xsb==0)?0.5:-0.5);
lib/libm/src/s_expm1.c
167
t = k;
lib/libm/src/s_expm1.c
178
else k = 0;
lib/libm/src/s_expm1.c
186
if(k==0) return x - (x*e-hxs); /* c is 0 */
lib/libm/src/s_expm1.c
190
if(k== -1) return 0.5*(x-e)-0.5;
lib/libm/src/s_expm1.c
191
if(k==1) {
lib/libm/src/s_expm1.c
195
if (k <= -2 || k>56) { /* suffice to return exp(x)-1 */
lib/libm/src/s_expm1.c
199
SET_HIGH_WORD(y,high+(k<<20)); /* add k to y's exponent */
lib/libm/src/s_expm1.c
203
if(k<20) {
lib/libm/src/s_expm1.c
205
SET_HIGH_WORD(t,0x3ff00000 - (0x200000>>k)); /* t=1-2^-k */
lib/libm/src/s_expm1.c
208
SET_HIGH_WORD(y,high+(k<<20)); /* add k to y's exponent */
lib/libm/src/s_expm1.c
211
SET_HIGH_WORD(t,((0x3ff-k)<<20)); /* 2^-k */
lib/libm/src/s_expm1.c
215
SET_HIGH_WORD(y,high+(k<<20)); /* add k to y's exponent */
lib/libm/src/s_expm1f.c
102
SET_FLOAT_WORD(y,i+(k<<23)); /* add k to y's exponent */
lib/libm/src/s_expm1f.c
106
if(k<23) {
lib/libm/src/s_expm1f.c
108
SET_FLOAT_WORD(t,0x3f800000 - (0x1000000>>k)); /* t=1-2^-k */
lib/libm/src/s_expm1f.c
111
SET_FLOAT_WORD(y,i+(k<<23)); /* add k to y's exponent */
lib/libm/src/s_expm1f.c
114
SET_FLOAT_WORD(t,((0x7f-k)<<23)); /* 2^-k */
lib/libm/src/s_expm1f.c
118
SET_FLOAT_WORD(y,i+(k<<23)); /* add k to y's exponent */
lib/libm/src/s_expm1f.c
38
int32_t k,xsb;
lib/libm/src/s_expm1f.c
65
{hi = x - ln2_hi; lo = ln2_lo; k = 1;}
lib/libm/src/s_expm1f.c
67
{hi = x + ln2_hi; lo = -ln2_lo; k = -1;}
lib/libm/src/s_expm1f.c
69
k = invln2*x+((xsb==0)?(float)0.5:(float)-0.5);
lib/libm/src/s_expm1f.c
70
t = k;
lib/libm/src/s_expm1f.c
81
else k = 0;
lib/libm/src/s_expm1f.c
89
if(k==0) return x - (x*e-hxs); /* c is 0 */
lib/libm/src/s_expm1f.c
93
if(k== -1) return (float)0.5*(x-e)-(float)0.5;
lib/libm/src/s_expm1f.c
94
if(k==1) {
lib/libm/src/s_expm1f.c
98
if (k <= -2 || k>56) { /* suffice to return exp(x)-1 */
lib/libm/src/s_log1p.c
101
int32_t k,hx,hu,ax;
lib/libm/src/s_log1p.c
106
k = 1;
lib/libm/src/s_log1p.c
120
k=0;f=x;hu=1;} /* -0.2929<x<0.41422 */
lib/libm/src/s_log1p.c
123
if(k!=0) {
lib/libm/src/s_log1p.c
127
k = (hu>>20)-1023;
lib/libm/src/s_log1p.c
128
c = (k>0)? 1.0-(u-x):x-(u-1.0);/* correction term */
lib/libm/src/s_log1p.c
133
k = (hu>>20)-1023;
lib/libm/src/s_log1p.c
140
k += 1;
lib/libm/src/s_log1p.c
148
if(f==zero) if(k==0) return zero;
lib/libm/src/s_log1p.c
149
else {c += k*ln2_lo; return k*ln2_hi+c;}
lib/libm/src/s_log1p.c
151
if(k==0) return f-R; else
lib/libm/src/s_log1p.c
152
return k*ln2_hi-((R-(k*ln2_lo+c))-f);
lib/libm/src/s_log1p.c
157
if(k==0) return f-(hfsq-s*(hfsq+R)); else
lib/libm/src/s_log1p.c
158
return k*ln2_hi-((hfsq-(s*(hfsq+R)+(k*ln2_lo+c)))-f);
lib/libm/src/s_log1pf.c
37
int32_t k,hx,hu,ax;
lib/libm/src/s_log1pf.c
42
k = 1;
lib/libm/src/s_log1pf.c
56
k=0;f=x;hu=1;} /* -0.2929<x<0.41422 */
lib/libm/src/s_log1pf.c
59
if(k!=0) {
lib/libm/src/s_log1pf.c
63
k = (hu>>23)-127;
lib/libm/src/s_log1pf.c
65
c = (k>0)? (float)1.0-(u-x):x-(u-(float)1.0);
lib/libm/src/s_log1pf.c
70
k = (hu>>23)-127;
lib/libm/src/s_log1pf.c
77
k += 1;
lib/libm/src/s_log1pf.c
85
if(f==zero) if(k==0) return zero;
lib/libm/src/s_log1pf.c
86
else {c += k*ln2_lo; return k*ln2_hi+c;}
lib/libm/src/s_log1pf.c
88
if(k==0) return f-R; else
lib/libm/src/s_log1pf.c
89
return k*ln2_hi-((R-(k*ln2_lo+c))-f);
lib/libm/src/s_log1pf.c
94
if(k==0) return f-(hfsq-s*(hfsq+R)); else
lib/libm/src/s_log1pf.c
95
return k*ln2_hi-((hfsq-(s*(hfsq+R)+(k*ln2_lo+c)))-f);
lib/libm/src/s_scalbnf.c
28
int32_t k,ix;
lib/libm/src/s_scalbnf.c
30
k = (ix&0x7f800000)>>23; /* extract exponent */
lib/libm/src/s_scalbnf.c
31
if (k==0) { /* 0 or subnormal x */
lib/libm/src/s_scalbnf.c
35
k = ((ix&0x7f800000)>>23) - 25;
lib/libm/src/s_scalbnf.c
38
if (k==0xff) return x+x; /* NaN or Inf */
lib/libm/src/s_scalbnf.c
39
k = k+n;
lib/libm/src/s_scalbnf.c
40
if (k > 0xfe) return huge*copysignf(huge,x); /* overflow */
lib/libm/src/s_scalbnf.c
41
if (k > 0) /* normal result */
lib/libm/src/s_scalbnf.c
42
{SET_FLOAT_WORD(x,(ix&0x807fffff)|(k<<23)); return x;}
lib/libm/src/s_scalbnf.c
43
if (k <= -25)
lib/libm/src/s_scalbnf.c
47
k += 25; /* subnormal result */
lib/libm/src/s_scalbnf.c
48
SET_FLOAT_WORD(x,(ix&0x807fffff)|(k<<23));
lib/libm/src/s_scalbnl.c
47
int k;
lib/libm/src/s_scalbnl.c
49
k = u.bits.ext_exp; /* extract exponent */
lib/libm/src/s_scalbnl.c
50
if (k==0) { /* 0 or subnormal x */
lib/libm/src/s_scalbnl.c
60
k = u.bits.ext_exp - 128;
lib/libm/src/s_scalbnl.c
63
if (k==0x7fff) return x+x; /* NaN or Inf */
lib/libm/src/s_scalbnl.c
64
k = k+n;
lib/libm/src/s_scalbnl.c
65
if (k >= 0x7fff) return huge*copysignl(huge,x); /* overflow */
lib/libm/src/s_scalbnl.c
66
if (k > 0) /* normal result */
lib/libm/src/s_scalbnl.c
67
{u.bits.ext_exp = k; return u.e;}
lib/libm/src/s_scalbnl.c
68
if (k <= -128) {
lib/libm/src/s_scalbnl.c
73
k += 128; /* subnormal result */
lib/libm/src/s_scalbnl.c
74
u.bits.ext_exp = k;
lib/libmenu/m_post.c
159
int j, k, ncy, ncx;
lib/libmenu/m_post.c
173
for (k = 0; k < count; k++)
lib/libpcap/bpf_image.c
141
v = n + 1 + p->k;
lib/libpcap/bpf_image.c
44
v = p->k;
lib/libpcap/gencode.c
1564
tmp->s.k = 6;
lib/libpcap/gencode.c
1568
s->s.k = off_nl + 6;
lib/libpcap/gencode.c
1571
b->s.k = 0x1fff;
lib/libpcap/gencode.c
1595
tmp->s.k = 0;
lib/libpcap/gencode.c
1600
tmp->s.k = 0x0f;
lib/libpcap/gencode.c
1605
tmp->s.k = 2;
lib/libpcap/gencode.c
1614
tmp->s.k = iphl_reg;
lib/libpcap/gencode.c
1620
s->s.k = iphl_reg;
lib/libpcap/gencode.c
1624
s->s.k = off_nl;
lib/libpcap/gencode.c
1639
tmp->s.k = off_nl + off; /* off_nl == 0 if variable_nl */
lib/libpcap/gencode.c
1644
b->s.k = v;
lib/libpcap/gencode.c
1872
s[i]->s.k = off_nl + 9;
lib/libpcap/gencode.c
1876
s[i]->s.k = off_nl;
lib/libpcap/gencode.c
1884
s[i]->s.k = off_nl + 6;
lib/libpcap/gencode.c
1888
s[i]->s.k = 40;
lib/libpcap/gencode.c
1899
s[i]->s.k = v;
lib/libpcap/gencode.c
1909
s[i]->s.k = IPPROTO_NONE;
lib/libpcap/gencode.c
1922
s[i]->s.k = IPPROTO_HOPOPTS;
lib/libpcap/gencode.c
1929
s[i]->s.k = IPPROTO_DSTOPTS;
lib/libpcap/gencode.c
1935
s[i]->s.k = IPPROTO_ROUTING;
lib/libpcap/gencode.c
1941
s[i]->s.k = IPPROTO_FRAGMENT;
lib/libpcap/gencode.c
1959
s[i]->s.k = reg1;
lib/libpcap/gencode.c
1963
s[i]->s.k = 1;
lib/libpcap/gencode.c
1970
s[i]->s.k = off_nl;
lib/libpcap/gencode.c
1974
s[i]->s.k = reg2;
lib/libpcap/gencode.c
1978
s[i]->s.k = reg1;
lib/libpcap/gencode.c
1982
s[i]->s.k = off_nl;
lib/libpcap/gencode.c
1986
s[i]->s.k = 1;
lib/libpcap/gencode.c
1990
s[i]->s.k = 8;
lib/libpcap/gencode.c
1997
s[i]->s.k = reg2;
lib/libpcap/gencode.c
2002
s[i]->s.k = again - i - 1;
lib/libpcap/gencode.c
2012
s[i]->s.k = 0;
lib/libpcap/gencode.c
2023
s[i]->s.k = IPPROTO_AH;
lib/libpcap/gencode.c
2039
s[i]->s.k = reg1;
lib/libpcap/gencode.c
2043
s[i]->s.k = 1;
lib/libpcap/gencode.c
2050
s[i]->s.k = off_nl;
lib/libpcap/gencode.c
2054
s[i]->s.k = reg2;
lib/libpcap/gencode.c
2058
s[i]->s.k = reg1;
lib/libpcap/gencode.c
2062
s[i]->s.k = off_nl;
lib/libpcap/gencode.c
2066
s[i]->s.k = 2;
lib/libpcap/gencode.c
2070
s[i]->s.k = 4;
lib/libpcap/gencode.c
2077
s[i]->s.k = reg2;
lib/libpcap/gencode.c
2082
s[i]->s.k = again - i - 1;
lib/libpcap/gencode.c
2088
s[i]->s.k = 0;
lib/libpcap/gencode.c
2107
b->s.k = v;
lib/libpcap/gencode.c
259
b->s.k = v;
lib/libpcap/gencode.c
2649
s->s.k = a->regno;
lib/libpcap/gencode.c
2659
s->s.k = a->regno;
lib/libpcap/gencode.c
2721
tmp->s.k = off_nl; /* off_nl == 0 for variable_nl */
lib/libpcap/gencode.c
2742
tmp->s.k = off_nl; /* off_nl is 0 if variable_nl */
lib/libpcap/gencode.c
2761
s->s.k = regno;
lib/libpcap/gencode.c
2779
b->s.k = 0x80000000;
lib/libpcap/gencode.c
2819
s->next->s.k = regno;
lib/libpcap/gencode.c
2835
s->next->s.k = regno;
lib/libpcap/gencode.c
2854
s->s.k = val;
lib/libpcap/gencode.c
2856
s->next->s.k = reg;
lib/libpcap/gencode.c
2871
s->s.k = 0;
lib/libpcap/gencode.c
2874
s->s.k = a->regno;
lib/libpcap/gencode.c
2897
a0->regno = s0->s.k = alloc_reg();
lib/libpcap/gencode.c
2949
b->s.k = n;
lib/libpcap/gencode.c
3003
s->s.k = val;
lib/libpcap/gencode.c
305
(root->s.code == (BPF_RET|BPF_K) && root->s.k == 0))
lib/libpcap/gencode.c
3065
s->s.k = 0;
lib/libpcap/gencode.c
3067
b0->s.k = 1;
lib/libpcap/gencode.c
3076
s->s.k = 1;
lib/libpcap/gencode.c
3078
b0->s.k = 1;
lib/libpcap/gencode.c
353
(root->s.code == (BPF_RET|BPF_K) && root->s.k == 0))
lib/libpcap/gencode.c
476
s->s.k = offset;
lib/libpcap/gencode.c
480
b->s.k = v;
lib/libpcap/gencode.c
492
s->s.k = offset;
lib/libpcap/gencode.c
496
b->s.k = v;
lib/libpcap/gencode.c
509
s->s.k = mask;
lib/libpcap/gencode.c
524
s->s.k = mask;
lib/libpcap/gencode.c
590
s->s.k = 0;
lib/libpcap/gencode.c
593
tmp->s.k = 3;
lib/libpcap/gencode.c
597
tmp->s.k = 0xfc;
lib/libpcap/gencode.c
602
tmp->s.k = nl_reg;
lib/libpcap/gencode.c
618
s->s.k = nl_reg;
lib/libpcap/gencode.c
633
tmp->s.k = offset;
lib/libpcap/gencode.c
637
s->s.k = offset + off_nl;
lib/libpcap/gencode.c
641
b->s.k = v;
lib/libpcap/gencode.c
791
s->s.k = !rsense;
lib/libpcap/gencode.c
932
s0->s.k = off_linktype;
lib/libpcap/gencode.c
936
s1->s.k = 4;
lib/libpcap/gencode.c
942
b0->s.k = ipv;
lib/libpcap/gencode.h
82
bpf_int32 k;
lib/libpcap/optimize.c
1007
v = val[s->k];
lib/libpcap/optimize.c
1010
s->k = vmap[v].const_val;
lib/libpcap/optimize.c
1017
vstore(s, &val[s->k], val[A_ATOM], alter);
lib/libpcap/optimize.c
1021
vstore(s, &val[s->k], val[X_ATOM], alter);
lib/libpcap/optimize.c
1129
b->oval = K(b->s.k);
lib/libpcap/optimize.c
1204
int i, k;
lib/libpcap/optimize.c
1232
k = ffs(x) - 1;
lib/libpcap/optimize.c
1233
x &=~ (1 << k);
lib/libpcap/optimize.c
1234
k += i * BITS_PER_WORD;
lib/libpcap/optimize.c
1236
target = fold_edge(ep->succ, edges[k]);
lib/libpcap/optimize.c
1605
if (x->s.code != y->s.code || x->s.k != y->s.k)
lib/libpcap/optimize.c
1616
b0->s.k == b1->s.k &&
lib/libpcap/optimize.c
1922
dst->k = src->s.k;
lib/libpcap/optimize.c
1988
dst->k = p->s.k;
lib/libpcap/optimize.c
2003
dst[extrajmps].k = off - extrajmps;
lib/libpcap/optimize.c
2020
dst[extrajmps].k = off - extrajmps;
lib/libpcap/optimize.c
361
(BPF_MODE(c) == BPF_MEM) ? s->k : -1;
lib/libpcap/optimize.c
406
return s->k;
lib/libpcap/optimize.c
612
s->k = a;
lib/libpcap/optimize.c
661
s->s.k == next->s.k) {
lib/libpcap/optimize.c
729
ild->s.k += s->s.k;
lib/libpcap/optimize.c
748
b->s.k += vmap[val].const_val;
lib/libpcap/optimize.c
754
b->s.k += 0x80000000;
lib/libpcap/optimize.c
758
} else if (b->s.k == 0) {
lib/libpcap/optimize.c
776
b->s.k += last->s.k;
lib/libpcap/optimize.c
783
b->s.k += 0x80000000;
lib/libpcap/optimize.c
792
!ATOMELEM(b->out_use, A_ATOM) && b->s.k == 0) {
lib/libpcap/optimize.c
793
b->s.k = last->s.k;
lib/libpcap/optimize.c
809
v = v == b->s.k;
lib/libpcap/optimize.c
813
v = (unsigned)v > b->s.k;
lib/libpcap/optimize.c
817
v = (unsigned)v >= b->s.k;
lib/libpcap/optimize.c
821
v &= b->s.k;
lib/libpcap/optimize.c
853
v = F(s->code, s->k, 0L);
lib/libpcap/optimize.c
863
s->k += vmap[v].const_val;
lib/libpcap/optimize.c
864
v = F(s->code, s->k, 0L);
lib/libpcap/optimize.c
868
v = F(s->code, s->k, v);
lib/libpcap/optimize.c
879
v = K(s->k);
lib/libpcap/optimize.c
884
v = K(s->k);
lib/libpcap/optimize.c
889
v = F(s->code, s->k, 0L);
lib/libpcap/optimize.c
896
s->k = -vmap[val[A_ATOM]].const_val;
lib/libpcap/optimize.c
897
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
913
if (s->k == 0) {
lib/libpcap/optimize.c
922
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
927
fold_op(s, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
928
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
932
val[A_ATOM] = F(s->code, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
947
val[A_ATOM] = K(s->k);
lib/libpcap/optimize.c
951
s->k = vmap[val[X_ATOM]].const_val;
lib/libpcap/optimize.c
954
F(s->code, val[A_ATOM], K(s->k));
lib/libpcap/optimize.c
976
s->k = 0;
lib/libpcap/optimize.c
977
vstore(s, &val[A_ATOM], K(s->k), alter);
lib/libpcap/optimize.c
993
v = val[s->k];
lib/libpcap/optimize.c
996
s->k = vmap[v].const_val;
lib/libssl/s3_cbc.c
399
num_starting_blocks, k, mac_end_offset, c, index_a, index_b;
lib/libssl/s3_cbc.c
503
k = 0;
lib/libssl/s3_cbc.c
521
k = md_block_size*num_starting_blocks;
lib/libssl/s3_cbc.c
549
if (k > 0) {
lib/libssl/s3_cbc.c
554
for (i = 1; i < k/md_block_size; i++)
lib/libssl/s3_cbc.c
570
if (k < header_length)
lib/libssl/s3_cbc.c
571
b = header[k];
lib/libssl/s3_cbc.c
572
else if (k < data_plus_mac_plus_padding_size + header_length)
lib/libssl/s3_cbc.c
573
b = data[k - header_length];
lib/libssl/s3_cbc.c
574
k++;
lib/libusbhid/parse.c
536
hid_report_size(report_desc_t r, enum hid_kind k, int id)
lib/libusbhid/parse.c
549
for (d = hid_start_parse(r, 1 << k, id); hid_get_item(d, &h); ) {
lib/libusbhid/parse.c
550
if (h.kind == k) {
lib/libusbhid/parse.c
576
hid_locate(report_desc_t desc, unsigned int u, enum hid_kind k,
lib/libusbhid/parse.c
581
for (d = hid_start_parse(desc, 1 << k, id); hid_get_item(d, h); ) {
lib/libusbhid/parse.c
582
if (h->kind == k && !(h->flags & HIO_CONST) && h->usage == u) {
lib/libusbhid/usage.c
210
int k;
lib/libusbhid/usage.c
215
for (k = 0; k < npages; k++)
lib/libusbhid/usage.c
216
if (pages[k].usage == i)
lib/libusbhid/usage.c
217
return pages[k].name;
lib/libusbhid/usage.c
225
int i = HID_USAGE(u), j, k, us;
lib/libusbhid/usage.c
229
for (k = 0; k < npages; k++)
lib/libusbhid/usage.c
230
if (pages[k].usage == page)
lib/libusbhid/usage.c
232
if (k >= npages)
lib/libusbhid/usage.c
234
for (j = 0; j < pages[k].pagesize; j++) {
lib/libusbhid/usage.c
235
us = pages[k].page_contents[j].usage;
lib/libusbhid/usage.c
238
pages[k].page_contents[j].name, i);
lib/libusbhid/usage.c
242
return pages[k].page_contents[j].name;
lib/libusbhid/usage.c
252
int k;
lib/libusbhid/usage.c
257
for (k = 0; k < npages; k++)
lib/libusbhid/usage.c
258
if (strcmp(pages[k].name, name) == 0)
lib/libusbhid/usage.c
259
return pages[k].usage;
lib/libusbhid/usage.c
269
int k, j, us, pu, len;
lib/libusbhid/usage.c
275
for (k = 0; k < npages; k++)
lib/libusbhid/usage.c
276
if (strncmp(pages[k].name, name, l) == 0)
lib/libusbhid/usage.c
281
for (j = 0; j < pages[k].pagesize; j++) {
lib/libusbhid/usage.c
282
us = pages[k].page_contents[j].usage;
lib/libusbhid/usage.c
284
fmtname = pages[k].page_contents[j].name;
lib/libusbhid/usage.c
290
return (pages[k].usage << 16) | pu;
lib/libusbhid/usage.c
293
if (strcmp(pages[k].page_contents[j].name, sep) == 0)
lib/libusbhid/usage.c
294
return (pages[k].usage << 16) |
lib/libusbhid/usage.c
295
pages[k].page_contents[j].usage;
lib/libusbhid/usbhid.h
86
int hid_report_size(report_desc_t d, enum hid_kind k, int id);
lib/libusbhid/usbhid.h
87
int hid_locate(report_desc_t d, unsigned int usage, enum hid_kind k,
lib/libutil/ber.c
428
u_int i, j = 0, k;
lib/libutil/ber.c
436
for (k = 28; k >= 7; k -= 7) {
lib/libutil/ber.c
437
if (v >= (u_int)(1 << k)) {
lib/libutil/ber.c
439
buf[j] = v >> k | BER_TAG_MORE;
lib/libutil/ohash.c
208
uint32_t k;
lib/libutil/ohash.c
213
k = 0;
lib/libutil/ohash.c
215
k = *s++;
lib/libutil/ohash.c
217
k = ((k << 2) | (k >> 30)) ^ *s++;
lib/libutil/ohash.c
218
return k;
lib/libutil/ohash.c
270
ohash_lookup_memory(struct ohash *h, const char *k, size_t size, uint32_t hv)
lib/libutil/ohash.c
289
memcmp(h->t[i].p+h->info.key_offset, k, size) == 0) {
lib/libz/crc32.c
182
local uLong x2nmodp(z_off64_t n, unsigned k) {
lib/libz/crc32.c
188
p = multmodp(x2n_table[k & 31], p);
lib/libz/crc32.c
190
k++;
lib/libz/crc32.c
279
int k, n;
lib/libz/crc32.c
338
for (k = 0; k < 8; k++) {
lib/libz/crc32.c
340
write_table(out, ltl[k], 256);
lib/libz/crc32.c
341
fprintf(out, "}%s", k < 7 ? ",\n" : "");
lib/libz/crc32.c
347
for (k = 0; k < 8; k++) {
lib/libz/crc32.c
349
write_table64(out, big[k], 256);
lib/libz/crc32.c
350
fprintf(out, "}%s", k < 7 ? ",\n" : "");
lib/libz/crc32.c
364
for (k = 0; k < 4; k++) {
lib/libz/crc32.c
366
write_table(out, ltl[k], 256);
lib/libz/crc32.c
367
fprintf(out, "}%s", k < 3 ? ",\n" : "");
lib/libz/crc32.c
373
for (k = 0; k < 4; k++) {
lib/libz/crc32.c
375
write_table32hi(out, big[k], 256);
lib/libz/crc32.c
376
fprintf(out, "}%s", k < 3 ? ",\n" : "");
lib/libz/crc32.c
408
local void write_table(FILE *out, const z_crc_t FAR *table, int k) {
lib/libz/crc32.c
411
for (n = 0; n < k; n++)
lib/libz/crc32.c
414
n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", "));
lib/libz/crc32.c
421
local void write_table32hi(FILE *out, const z_word_t FAR *table, int k) {
lib/libz/crc32.c
424
for (n = 0; n < k; n++)
lib/libz/crc32.c
427
n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", "));
lib/libz/crc32.c
437
local void write_table64(FILE *out, const z_word_t FAR *table, int k) {
lib/libz/crc32.c
440
for (n = 0; n < k; n++)
lib/libz/crc32.c
443
n == k - 1 ? "" : (n % 3 == 2 ? ",\n" : ", "));
lib/libz/crc32.c
460
int k;
lib/libz/crc32.c
462
for (k = 0; k < w; k++) {
lib/libz/crc32.c
463
p = (z_crc_t)x2nmodp((n * w + 3 - k) << 3, 0);
lib/libz/crc32.c
464
ltl[k][0] = 0;
lib/libz/crc32.c
465
big[w - 1 - k][0] = 0;
lib/libz/crc32.c
467
ltl[k][i] = q = (z_crc_t)multmodp(i << 24, p);
lib/libz/crc32.c
468
big[w - 1 - k][i] = byte_swap(q);
lib/libz/crc32.c
607
int k;
lib/libz/crc32.c
608
for (k = 0; k < W; k++)
lib/libz/crc32.c
614
int k;
lib/libz/crc32.c
615
for (k = 0; k < W; k++)
lib/libz/crc32.c
642
int k;
lib/libz/crc32.c
746
for (k = 1; k < W; k++) {
lib/libz/crc32.c
747
crc0 ^= crc_braid_table[k][(word0 >> (k << 3)) & 0xff];
lib/libz/crc32.c
749
crc1 ^= crc_braid_table[k][(word1 >> (k << 3)) & 0xff];
lib/libz/crc32.c
751
crc2 ^= crc_braid_table[k][(word2 >> (k << 3)) & 0xff];
lib/libz/crc32.c
753
crc3 ^= crc_braid_table[k][(word3 >> (k << 3)) & 0xff];
lib/libz/crc32.c
755
crc4 ^= crc_braid_table[k][(word4 >> (k << 3)) & 0xff];
lib/libz/crc32.c
757
crc5 ^= crc_braid_table[k][(word5 >> (k << 3)) & 0xff];
lib/libz/crc32.c
868
for (k = 1; k < W; k++) {
lib/libz/crc32.c
869
crc0 ^= crc_braid_big_table[k][(word0 >> (k << 3)) & 0xff];
lib/libz/crc32.c
871
crc1 ^= crc_braid_big_table[k][(word1 >> (k << 3)) & 0xff];
lib/libz/crc32.c
873
crc2 ^= crc_braid_big_table[k][(word2 >> (k << 3)) & 0xff];
lib/libz/crc32.c
875
crc3 ^= crc_braid_big_table[k][(word3 >> (k << 3)) & 0xff];
lib/libz/crc32.c
877
crc4 ^= crc_braid_big_table[k][(word4 >> (k << 3)) & 0xff];
lib/libz/crc32.c
879
crc5 ^= crc_braid_big_table[k][(word5 >> (k << 3)) & 0xff];
lib/libz/trees.c
507
local void pqdownheap(deflate_state *s, ct_data *tree, int k) {
lib/libz/trees.c
508
int v = s->heap[k];
lib/libz/trees.c
509
int j = k << 1; /* left son of k */
lib/libz/trees.c
520
s->heap[k] = s->heap[j]; k = j;
lib/libz/trees.c
525
s->heap[k] = v;
libexec/ld.so/chacha_private.h
55
chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)
libexec/ld.so/chacha_private.h
59
x->input[4] = U8TO32_LITTLE(k + 0);
libexec/ld.so/chacha_private.h
60
x->input[5] = U8TO32_LITTLE(k + 4);
libexec/ld.so/chacha_private.h
61
x->input[6] = U8TO32_LITTLE(k + 8);
libexec/ld.so/chacha_private.h
62
x->input[7] = U8TO32_LITTLE(k + 12);
libexec/ld.so/chacha_private.h
64
k += 16;
libexec/ld.so/chacha_private.h
69
x->input[8] = U8TO32_LITTLE(k + 0);
libexec/ld.so/chacha_private.h
70
x->input[9] = U8TO32_LITTLE(k + 4);
libexec/ld.so/chacha_private.h
71
x->input[10] = U8TO32_LITTLE(k + 8);
libexec/ld.so/chacha_private.h
72
x->input[11] = U8TO32_LITTLE(k + 12);
libexec/ld.so/ldconfig/ldconfig.c
284
int k = 0;
libexec/ld.so/ldconfig/ldconfig.c
287
k = (((k << 1) + (k >> 14)) ^ (*cp++)) & 0x3fff;
libexec/ld.so/ldconfig/ldconfig.c
289
k = (((k << 1) + (k >> 14)) ^ (vmajor*257)) & 0x3fff;
libexec/ld.so/ldconfig/ldconfig.c
291
k = (((k << 1) + (k >> 14)) ^ (vminor*167)) & 0x3fff;
libexec/ld.so/ldconfig/ldconfig.c
294
return k;
libexec/ld.so/ldconfig/sod.c
263
int k = 0;
libexec/ld.so/ldconfig/sod.c
266
k = (((k << 1) + (k >> 14)) ^ (*cp++)) & 0x3fff;
libexec/ld.so/ldconfig/sod.c
268
k = (((k << 1) + (k >> 14)) ^ (vmajor*257)) & 0x3fff;
libexec/ld.so/ldconfig/sod.c
270
return k;
libexec/ld.so/malloc.c
629
size_t k;
libexec/ld.so/malloc.c
658
k = __builtin_ffs(*lp >> j);
libexec/ld.so/malloc.c
659
if (k != 0) {
libexec/ld.so/malloc.c
660
k += j - 1;
libexec/ld.so/malloc.c
671
k = __builtin_ffs(*lp) - 1;
libexec/ld.so/malloc.c
676
*lp ^= 1 << k;
libexec/ld.so/malloc.c
683
k += (lp - bp->bits) * MALLOC_BITS;
libexec/ld.so/malloc.c
686
bp->bits[bp->offset + k] = size;
libexec/ld.so/malloc.c
688
k <<= bp->shift;
libexec/ld.so/malloc.c
690
p = (char *)bp->page + k;
libexec/ld.so/sod.c
265
int k = 0;
libexec/ld.so/sod.c
268
k = (((k << 1) + (k >> 14)) ^ (*cp++)) & 0x3fff;
libexec/ld.so/sod.c
270
k = (((k << 1) + (k >> 14)) ^ (vmajor*257)) & 0x3fff;
libexec/ld.so/sod.c
272
return k;
libexec/snmpd/snmpd_metrics/kroute.c
1165
strlcpy(kif->k.if_name, ifan->ifan_name,
libexec/snmpd/snmpd_metrics/kroute.c
1166
sizeof(kif->k.if_name));
libexec/snmpd/snmpd_metrics/kroute.c
429
return (a->k.if_index - b->k.if_index);
libexec/snmpd/snmpd_metrics/kroute.c
75
struct kif k;
libexec/snmpd/snmpd_metrics/kroute.c
795
s.k.if_index = if_index;
libexec/snmpd/snmpd_metrics/kroute.c
809
return (&kn->k);
libexec/snmpd/snmpd_metrics/kroute.c
824
return (&kn->k);
libexec/snmpd/snmpd_metrics/kroute.c
835
kif->k.if_index = if_index;
libexec/snmpd/snmpd_metrics/kroute.c
897
kif->k.if_flags = flags;
libexec/snmpd/snmpd_metrics/kroute.c
898
bcopy(ifd, &kif->k.if_data, sizeof(struct if_data));
libexec/snmpd/snmpd_metrics/kroute.c
899
kif->k.if_ticks = smi_getticks();
libexec/snmpd/snmpd_metrics/kroute.c
902
if (sdl->sdl_nlen >= sizeof(kif->k.if_name))
libexec/snmpd/snmpd_metrics/kroute.c
903
memcpy(kif->k.if_name, sdl->sdl_data,
libexec/snmpd/snmpd_metrics/kroute.c
904
sizeof(kif->k.if_name) - 1);
libexec/snmpd/snmpd_metrics/kroute.c
906
memcpy(kif->k.if_name, sdl->sdl_data,
libexec/snmpd/snmpd_metrics/kroute.c
911
bcopy(&ea->ether_addr_octet, kif->k.if_lladdr,
libexec/snmpd/snmpd_metrics/kroute.c
916
strlcpy(ifr.ifr_name, kif->k.if_name, sizeof(ifr.ifr_name));
libexec/snmpd/snmpd_metrics/kroute.c
917
ifr.ifr_data = (caddr_t)&kif->k.if_descr;
libexec/snmpd/snmpd_metrics/kroute.c
919
bzero(&kif->k.if_descr, sizeof(kif->k.if_descr));
libexec/snmpd/snmpd_metrics/kroute.c
921
return (&kif->k);
libexec/snmpd/snmpd_metrics/mib.c
2024
int i, j, k;
libexec/snmpd/snmpd_metrics/mib.c
2057
for (k = 0; k < sensordev.maxnumt[j]; k++) {
libexec/snmpd/snmpd_metrics/mib.c
2058
mib[4] = k;
libexec/spamd/sdl.c
203
int j, k;
libexec/spamd/sdl.c
226
k = 0;
libexec/spamd/sdl.c
230
m->addr32[k++] = 0xffffffffU;
libexec/spamd/sdl.c
234
m->addr32[k] |= (1 << j);
libexec/spamd/sdl.c
236
m->addr32[k] = htonl(m->addr32[k]);
libexec/spamd/sdl.c
298
const struct in_addr *k = vkey;
libexec/spamd/sdl.c
304
kk.s_addr = ntohl(k->s_addr & m->s_addr);
libexec/spamd/sdl.c
321
const struct sdaddr_v6 *k = vkey;
libexec/spamd/sdl.c
327
kk.addr32[0] = ntohl(k->addr32[0] & m->addr32[0]);
libexec/spamd/sdl.c
328
kk.addr32[1] = ntohl(k->addr32[1] & m->addr32[1]);
libexec/spamd/sdl.c
329
kk.addr32[2] = ntohl(k->addr32[2] & m->addr32[2]);
libexec/spamd/sdl.c
330
kk.addr32[3] = ntohl(k->addr32[3] & m->addr32[3]);
libexec/tradcpp/macro.c
393
unsigned oldnum, j, k;
libexec/tradcpp/macro.c
421
for (j=k=0; j<oldnum; j++) {
libexec/tradcpp/macro.c
424
if (k < j) {
libexec/tradcpp/macro.c
425
macroarray_set(oldbucket, k, m);
libexec/tradcpp/macro.c
427
k++;
libexec/tradcpp/macro.c
430
macroarray_setsize(oldbucket, k);
regress/include/bitstring/bitstring_test.c
250
p = &k;
regress/include/bitstring/bitstring_test.c
252
(void) printf("bit_ffc(%d, %ld) -> %d\n", j++, --p - &k, i);
regress/include/bitstring/bitstring_test.c
254
(void) printf("bit_ffs(%d, %ld) -> %d\n", j++, --p - &k, i);
regress/include/bitstring/bitstring_test.c
42
register int i, k;
regress/include/bitstring/bitstring_test.c
57
int i, j, k, *p;
regress/lib/libc/cephes/ieee.c
1411
int i, lost, j, k;
regress/lib/libc/cephes/ieee.c
1450
k = (int )lt;
regress/lib/libc/cephes/ieee.c
1451
lost = eshift( ai, k ); /* shift the smaller number down */
regress/lib/libc/cephes/ieee.c
1734
int denorm, k;
regress/lib/libc/cephes/ieee.c
1800
if( (k = enormlz(yy)) > NBITS )
regress/lib/libc/cephes/ieee.c
1803
yy[E] -= (unsigned short )(k-1);
regress/lib/libc/cephes/ieee.c
1983
int denorm, k;
regress/lib/libc/cephes/ieee.c
2049
if( (k = enormlz(yy)) > NBITS )
regress/lib/libc/cephes/ieee.c
2052
yy[E] -= (unsigned short )(k-1);
regress/lib/libc/cephes/ieee.c
2587
int k;
regress/lib/libc/cephes/ieee.c
2614
if( (k = enormlz( yi )) > NBITS ) /* normalize the significand */
regress/lib/libc/cephes/ieee.c
2617
yi[E] -= (unsigned short )k; /* subtract shift count from exponent */
regress/lib/libc/cephes/ieee.c
2635
int k;
regress/lib/libc/cephes/ieee.c
2655
if( (k = enormlz( yi )) > NBITS ) /* normalize the significand */
regress/lib/libc/cephes/ieee.c
2658
yi[E] -= (unsigned short )k; /* subtract shift count from exponent */
regress/lib/libc/cephes/ieee.c
2679
int j, k;
regress/lib/libc/cephes/ieee.c
2683
k = (int )xi[E] - (EXONE - 1);
regress/lib/libc/cephes/ieee.c
2684
if( k <= 0 )
regress/lib/libc/cephes/ieee.c
2691
if( k > (8 * sizeof(long) - 1) )
regress/lib/libc/cephes/ieee.c
2702
(void )eshift( xi, k );
regress/lib/libc/cephes/ieee.c
2704
if( k > 16 )
regress/lib/libc/cephes/ieee.c
2710
j = k - ((k >> 4) << 4);
regress/lib/libc/cephes/ieee.c
2713
k -= j;
regress/lib/libc/cephes/ieee.c
2719
while ((k -= 16) > 0);
regress/lib/libc/cephes/ieee.c
2727
eshift( xi, k );
regress/lib/libc/cephes/ieee.c
2735
if( (k = enormlz( xi )) > NBITS )
regress/lib/libc/cephes/ieee.c
2738
xi[E] -= (unsigned short )k;
regress/lib/libc/cephes/ieee.c
2760
int j, k;
regress/lib/libc/cephes/ieee.c
2764
k = (int )xi[E] - (EXONE - 1);
regress/lib/libc/cephes/ieee.c
2765
if( k <= 0 )
regress/lib/libc/cephes/ieee.c
2772
if( k > (8 * sizeof(long)) )
regress/lib/libc/cephes/ieee.c
2779
(void )eshift( xi, k );
regress/lib/libc/cephes/ieee.c
2781
else if( k > 16 )
regress/lib/libc/cephes/ieee.c
2787
j = k - ((k >> 4) << 4);
regress/lib/libc/cephes/ieee.c
2790
k -= j;
regress/lib/libc/cephes/ieee.c
2796
while ((k -= 16) > 0);
regress/lib/libc/cephes/ieee.c
2802
eshift( xi, k );
regress/lib/libc/cephes/ieee.c
2812
if( (k = enormlz( xi )) > NBITS )
regress/lib/libc/cephes/ieee.c
2815
xi[E] -= (unsigned short )k;
regress/lib/libc/cephes/ieee.c
3123
int i, j, k, expon, rndsav;
regress/lib/libc/cephes/ieee.c
3152
for( k=0; k<NE-1; k++ )
regress/lib/libc/cephes/ieee.c
3154
if( y[k] != 0 )
regress/lib/libc/cephes/ieee.c
3271
k = -MAXP;
regress/lib/libc/cephes/ieee.c
3282
expon += k;
regress/lib/libc/cephes/ieee.c
3284
k /= 2;
regress/lib/libc/cephes/ieee.c
3285
if( k == 0 )
regress/lib/libc/cephes/ieee.c
3338
for( k=0; k<=ndigs; k++ )
regress/lib/libc/cephes/ieee.c
3367
k = *s & 0x7f;
regress/lib/libc/cephes/ieee.c
3369
if( k == '.' )
regress/lib/libc/cephes/ieee.c
3372
k = *s;
regress/lib/libc/cephes/ieee.c
3373
k += 1;
regress/lib/libc/cephes/ieee.c
3374
*s = (char )k;
regress/lib/libc/cephes/ieee.c
3376
if( k > '9' )
regress/lib/libc/cephes/ieee.c
3384
k += 1;
regress/lib/libc/cephes/ieee.c
3385
*s = (char )k;
regress/lib/libc/cephes/ieee.c
3386
if( k > '9' )
regress/lib/libc/cephes/ieee.c
3482
int k, trail, c, rndsav;
regress/lib/libc/cephes/ieee.c
3492
for( k=0; k<79; k++ )
regress/lib/libc/cephes/ieee.c
3513
k = *s - '0';
regress/lib/libc/cephes/ieee.c
3514
if( (k >= 0) && (k <= 9) )
regress/lib/libc/cephes/ieee.c
3517
if( (prec == 0) && (decflg == 0) && (k == 0) )
regress/lib/libc/cephes/ieee.c
3553
xt[NI-2] = (unsigned short )k;
regress/lib/libc/cephes/ieee.c
3559
lost |= k;
regress/lib/libc/cephes/ieee.c
3671
if( (k = enormlz(yy)) > NBITS )
regress/lib/libc/cephes/ieee.c
3676
lexp = (EXONE - 1 + NBITS) - k;
regress/lib/libc/cephes/ieee.c
3690
k = 0;
regress/lib/libc/cephes/ieee.c
3702
k = edivm( tt, yy );
regress/lib/libc/cephes/ieee.c
3723
k = edivm( tt, yy );
regress/lib/libc/cephes/ieee.c
3729
k = emulm( tt, yy );
regress/lib/libc/cephes/ieee.c
3745
emdnorm( yy, k, 0, lexp, 64 );
regress/lib/libc/cephes/ieee.c
4053
int i, j, k, n, nlups;
regress/lib/libc/cephes/ieee.c
4127
for( k=0; k<NI; k++ )
regress/lib/libc/cephes/ieee.c
4128
temp[k] = sq[k];
regress/lib/libc/cephes/ieee.c
4146
k = 0;
regress/lib/libc/cephes/ieee.c
4148
k |= (int )num[i];
regress/lib/libc/cephes/ieee.c
4151
emdnorm( sq, k, 0, exp, 64 );
regress/lib/libc/cephes/ieee.c
867
int i, j, k;
regress/lib/libc/cephes/ieee.c
875
k = NBITS;
regress/lib/libc/cephes/ieee.c
879
k -= 16;
regress/lib/libc/cephes/ieee.c
884
k -= 8;
regress/lib/libc/cephes/ieee.c
889
for( i=0; i<k; i++ )
regress/lib/libc/qsort/qsort_test.c
288
int i, j, k; \
regress/lib/libc/qsort/qsort_test.c
290
for (i = 0, j = 0, k = 1; i < n; i++) \
regress/lib/libc/qsort/qsort_test.c
291
x[i] = arc4random_uniform(m) ? (j += 2) : (k += 2); \
regress/lib/libc/qsort/qsort_test.c
316
int i, k; \
regress/lib/libc/qsort/qsort_test.c
319
k = n / 2; \
regress/lib/libc/qsort/qsort_test.c
321
if (i < k) \
regress/lib/libc/qsort/qsort_test.c
322
x[i] = k - i; \
regress/lib/libc/qsort/qsort_test.c
323
else if (i > k) \
regress/lib/libc/qsort/qsort_test.c
324
x[i] = n + k + 1 - i; \
regress/lib/libc/qsort/qsort_test.c
326
x[i] = k + 1; \
regress/lib/libc/qsort/qsort_test.c
355
int i, k; \
regress/lib/libc/qsort/qsort_test.c
366
k = n / 2; \
regress/lib/libc/qsort/qsort_test.c
369
x[i] = k + x[i - 1]; \
regress/lib/libc/sys/t_select.c
82
for (size_t k = sizeof(p); k > 0; k--)
regress/lib/libc/sys/t_select.c
83
buf[j++] = xtoa(N(p, k - 1));
regress/lib/libc/sys/t_select.c
87
for (size_t k = sizeof(p); k > 0; k--)
regress/lib/libc/sys/t_select.c
88
buf[j++] = xtoa(N(p, k - 1));
regress/lib/libcrypto/bn/bn_gcd.c
3540
bn_binomial_gcd_test(const struct gcd_test_fn *test, int k, BIGNUM *a,
regress/lib/libcrypto/bn/bn_gcd.c
3563
test->name, k, shift, signs);
regress/lib/libcrypto/bn/bn_gcd.c
3569
test->name, k, shift, signs);
regress/lib/libcrypto/bn/bn_gcd.c
3576
test->name, k, shift, signs);
regress/lib/libcrypto/bn/bn_gcd.c
3602
int k;
regress/lib/libcrypto/bn/bn_gcd.c
3618
for (k = 0; k < 400; k++) {
regress/lib/libcrypto/bn/bn_gcd.c
3623
if (!BN_set_bit(a, 2 * k))
regress/lib/libcrypto/bn/bn_gcd.c
3629
if (!BN_set_bit(b, k))
regress/lib/libcrypto/bn/bn_gcd.c
3634
failed |= bn_binomial_gcd_test(test, k, a, b, ctx);
regress/lib/libcrypto/bn/bn_gcd.c
3640
if (!BN_set_bit(a, 2 * k))
regress/lib/libcrypto/bn/bn_gcd.c
3646
if (!BN_set_bit(b, k))
regress/lib/libcrypto/bn/bn_gcd.c
3651
failed |= bn_binomial_gcd_test(test, k, a, b, ctx);
regress/lib/libcrypto/bn/bn_isqrt.c
128
int j, k;
regress/lib/libcrypto/bn/bn_isqrt.c
139
for (k = 0; k < fill[i]; k++) {
regress/lib/libcrypto/bn/bn_isqrt.c
140
if (j == (k * k) % fill[i])
regress/lib/libcrypto/bn/bn_isqrt.c
144
if (table[j] == 0 && k < fill[i]) {
regress/lib/libcrypto/bn/bn_isqrt.c
145
fprintf(stderr, "%d == %d^2 (mod %d)", j, k,
regress/lib/libcrypto/bn/bn_isqrt.c
149
if (table[j] == 1 && k == fill[i]) {
regress/lib/libcrypto/cast/casttest.c
109
CAST_set_key(&key, k_len[z], k);
regress/lib/libcrypto/cast/casttest.c
65
static const unsigned char k[16] = {
regress/lib/libcrypto/chacha/chachatest.c
317
size_t k;
regress/lib/libcrypto/chacha/chachatest.c
325
for (k = 0; k < sizeof(out); k++)
regress/lib/libcrypto/chacha/chachatest.c
326
printf("%2.2x", out[k]);
regress/lib/libcrypto/chacha/chachatest.c
330
for (k = 0; k < sizeof(result); k++)
regress/lib/libcrypto/chacha/chachatest.c
331
printf("%2.2x", result[k]);
regress/lib/libcrypto/chacha/chachatest.c
436
size_t k;
regress/lib/libcrypto/chacha/chachatest.c
444
for (k = 0; k < sizeof(out); k++)
regress/lib/libcrypto/chacha/chachatest.c
445
printf("%2.2x", out[k]);
regress/lib/libcrypto/chacha/chachatest.c
449
for (k = 0; k < sizeof(cipher); k++)
regress/lib/libcrypto/chacha/chachatest.c
450
printf("%2.2x", cipher[k]);
regress/lib/libcrypto/chacha/chachatest.c
464
size_t i, j, k;
regress/lib/libcrypto/chacha/chachatest.c
485
for (k = 0; k < tv->len; k++)
regress/lib/libcrypto/chacha/chachatest.c
486
printf("%2.2x", out[k]);
regress/lib/libcrypto/chacha/chachatest.c
490
for (k = 0; k < tv->len; k++)
regress/lib/libcrypto/chacha/chachatest.c
491
printf("%2.2x", tv->out[k]);
regress/lib/libcrypto/ec/ectest.c
163
int k;
regress/lib/libcrypto/ec/ectest.c
247
k = 0;
regress/lib/libcrypto/ec/ectest.c
249
fprintf(stderr, " %d - ", k);
regress/lib/libcrypto/ec/ectest.c
267
if (k++ > 99)
regress/lib/libcrypto/ec/ectest.c
271
if (k != 7) {
regress/lib/libcrypto/ec/ectest.c
272
fprintf(stderr, "cycled in %d iterations, want 7\n", k);
regress/lib/libcrypto/idea/ideatest.c
107
idea_set_encrypt_key(k,&key);
regress/lib/libcrypto/idea/ideatest.c
141
memcpy(iv,k,8);
regress/lib/libcrypto/idea/ideatest.c
143
memcpy(iv,k,8);
regress/lib/libcrypto/idea/ideatest.c
65
unsigned char k[16]={
regress/lib/libcrypto/mlkem/mlkem_tests.c
207
CBS dk, c, k;
regress/lib/libcrypto/mlkem/mlkem_tests.c
214
parse_get_cbs(p, NIST_DECAP_K, &k);
regress/lib/libcrypto/mlkem/mlkem_tests.c
223
MLKEM_SHARED_SECRET_LENGTH, CBS_len(&k)))
regress/lib/libcrypto/mlkem/mlkem_tests.c
242
failed = !parse_data_equal(p, "shared secret", &k,
regress/lib/libcrypto/rand/randtest.c
100
for (k=0; k<8; k++)
regress/lib/libcrypto/rand/randtest.c
71
int i,j,k,s,sign,nsign,err=0;
regress/lib/libcrypto/sm4/sm4test.c
44
static const uint8_t k[SM4_BLOCK_SIZE] = {
regress/lib/libcrypto/sm4/sm4test.c
73
if (!SM4_set_key(k, &key))
regress/lib/libcrypto/utf8/utf8test.c
128
for (k = 0; k < 0x100; k++) {
regress/lib/libcrypto/utf8/utf8test.c
129
testbuf[2] = k;
regress/lib/libcrypto/utf8/utf8test.c
140
k < 0x80 || k > 0xBF) {
regress/lib/libcrypto/utf8/utf8test.c
161
ASSERT((value & 0x3F) == (k & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
177
for (k = 0; k < 0x100; k++) {
regress/lib/libcrypto/utf8/utf8test.c
178
testbuf[2] = k;
regress/lib/libcrypto/utf8/utf8test.c
192
k < 0x80 || k > 0xBF ||
regress/lib/libcrypto/utf8/utf8test.c
216
(k & 0x3F));
regress/lib/libcrypto/utf8/utf8test.c
44
unsigned int i, j, k, l;
regress/lib/libm/cephes/testvect.c
410
int i, nerrors, k, ianswer, ntests;
regress/lib/libm/cephes/testvect.c
542
k = (*(fun3)) (x1);
regress/lib/libm/cephes/testvect.c
544
if (k != ianswer)
regress/lib/libm/cephes/testvect.c
547
test3[i].name, x1, k, ianswer);
regress/lib/libm/cephes/testvectl.c
385
int i, nerrors, k, ianswer, ntests;
regress/lib/libm/cephes/testvectl.c
499
k = (*(fun3)) (x1);
regress/lib/libm/cephes/testvectl.c
501
if (k != ianswer)
regress/lib/libm/cephes/testvectl.c
504
test3[i].name, x1, k, ianswer);
regress/lib/libm/cephes/testvectll.c
406
int i, nerrors, k, ianswer, ntests;
regress/lib/libm/cephes/testvectll.c
526
k = (*(fun3)) (x1);
regress/lib/libm/cephes/testvectll.c
528
if (k != ianswer)
regress/lib/libm/cephes/testvectll.c
531
test3[i].name, x1, k, ianswer);
regress/lib/libutil/bcrypt_pbkdf/bcrypt_pbkdf_test.c
113
int k;
regress/lib/libutil/bcrypt_pbkdf/bcrypt_pbkdf_test.c
115
for (k = 0; k < keylen; k++) {
regress/lib/libutil/bcrypt_pbkdf/bcrypt_pbkdf_test.c
116
printf("\\x%.2x", key[k]);
regress/lib/libutil/bcrypt_pbkdf/bcrypt_pbkdf_test.c
117
if (k % 16 == 15)
regress/sys/arch/amd64/dump_tables/dump_tables.c
288
k = kvm_open(NULL, NULL, NULL, O_RDONLY, "foo");
regress/sys/arch/amd64/dump_tables/dump_tables.c
289
if (k == NULL)
regress/sys/arch/amd64/dump_tables/dump_tables.c
294
struct kinfo_proc *kp = kvm_getprocs(k, KERN_PROC_PID, 1,
regress/sys/arch/amd64/dump_tables/dump_tables.c
298
if (kvm_nlist(k, nl) != 0)
regress/sys/arch/amd64/dump_tables/dump_tables.c
76
kvm_t *k;
regress/sys/arch/amd64/dump_tables/dump_tables.c
90
if (kvm_read(k, addr, p, s) != s) \
regress/sys/arch/amd64/dump_tables/dump_tables.c
91
errx(1, "cannot read %s: %s", msg, kvm_geterr(k)); \
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
198
cred_matches_key_ecdsa(const fido_cred_t *cred, const struct sshkey *k)
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
246
key->sk_application = xstrdup(k->sk_application); /* XXX */
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
247
if (!sshkey_equal_public(key, k)) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
264
cred_matches_key_ed25519(const fido_cred_t *cred, const struct sshkey *k)
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
291
key->sk_application = xstrdup(k->sk_application); /* XXX */
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
292
if (!sshkey_equal_public(key, k)) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
304
cred_matches_key(const fido_cred_t *cred, const struct sshkey *k)
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
306
switch (sshkey_type_plain(k->type)) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
308
switch (k->ecdsa_nid) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
310
return cred_matches_key_ecdsa(cred, k);
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
317
return cred_matches_key_ed25519(cred, k);
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
319
error_f("key type %s not supported", sshkey_type(k));
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
329
struct sshkey *k = NULL;
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
372
if ((r = sshkey_load_public(argv[0], &k, NULL)) != 0)
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
374
if ((fp = sshkey_fingerprint(k, SSH_FP_HASH_DEFAULT,
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
377
debug2("key %s: %s %s", argv[2], sshkey_type(k), fp);
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
386
switch (sshkey_type_plain(k->type)) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
388
switch (k->ecdsa_nid) {
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
400
fatal("unsupported key type %s", sshkey_type(k));
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
403
if ((r = prepare_fido_cred(cred, credtype, attfmt, k->sk_application,
regress/usr.bin/ssh/misc/ssh-verify-attestation/ssh-verify-attestation.c
417
if (cred_matches_key(cred, k) != 0)
regress/usr.bin/ssh/unittests/bitmap/tests.c
107
i, j, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
120
if (k >= 0) {
regress/usr.bin/ssh/unittests/bitmap/tests.c
121
bitmap_clear_bit(b, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
122
BN_clear_bit(bn, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
28
int i, j, k, n, ntests = DEFAULT_NTESTS;
regress/usr.bin/ssh/unittests/bitmap/tests.c
47
for (k = -1; k < ntests; k++) {
regress/usr.bin/ssh/unittests/bitmap/tests.c
51
test_subtest_info("set %d/%d/%d", i, j, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
61
if (k >= 0) {
regress/usr.bin/ssh/unittests/bitmap/tests.c
62
ASSERT_INT_EQ(bitmap_set_bit(b, k), 0);
regress/usr.bin/ssh/unittests/bitmap/tests.c
63
ASSERT_INT_EQ(BN_set_bit(bn, k), 1);
regress/usr.bin/ssh/unittests/bitmap/tests.c
67
test_subtest_info("match %d/%d/%d", i, j, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
74
test_subtest_info("length %d/%d/%d", i, j, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
82
i, j, k);
regress/usr.bin/ssh/unittests/bitmap/tests.c
96
i, j, k);
regress/usr.bin/ssh/unittests/crypto/tests.c
64
char *k, *ret;
regress/usr.bin/ssh/unittests/crypto/tests.c
70
ASSERT_INT_GT(asprintf(&k, "\"%s\"", key), 0);
regress/usr.bin/ssh/unittests/crypto/tests.c
71
if (sshbuf_find(tmp, 0, k, strlen(k), &off) != 0) {
regress/usr.bin/ssh/unittests/crypto/tests.c
72
fprintf(stderr, "Key %s not found in JSON\n", k);
regress/usr.bin/ssh/unittests/crypto/tests.c
75
ASSERT_INT_EQ(sshbuf_consume(tmp, off + strlen(k)), 0);
regress/usr.bin/ssh/unittests/crypto/tests.c
76
free(k);
regress/usr.bin/ssh/unittests/sshkey/common.c
101
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
102
ASSERT_PTR_NE(EVP_PKEY_get0_RSA(k->pkey), NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
103
RSA_get0_factors(EVP_PKEY_get0_RSA(k->pkey), &p, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
108
rsa_q(struct sshkey *k)
regress/usr.bin/ssh/unittests/sshkey/common.c
112
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
113
ASSERT_PTR_NE(EVP_PKEY_get0_RSA(k->pkey), NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
114
RSA_get0_factors(EVP_PKEY_get0_RSA(k->pkey), NULL, &q);
regress/usr.bin/ssh/unittests/sshkey/common.c
75
rsa_n(struct sshkey *k)
regress/usr.bin/ssh/unittests/sshkey/common.c
79
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
80
ASSERT_PTR_NE(k->pkey, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
81
RSA_get0_key(EVP_PKEY_get0_RSA(k->pkey), &n, NULL, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
86
rsa_e(struct sshkey *k)
regress/usr.bin/ssh/unittests/sshkey/common.c
90
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
91
ASSERT_PTR_NE(k->pkey, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
92
RSA_get0_key(EVP_PKEY_get0_RSA(k->pkey), NULL, &e, NULL);
regress/usr.bin/ssh/unittests/sshkey/common.c
97
rsa_p(struct sshkey *k)
regress/usr.bin/ssh/unittests/sshkey/common.h
18
const BIGNUM *rsa_n(struct sshkey *k);
regress/usr.bin/ssh/unittests/sshkey/common.h
19
const BIGNUM *rsa_e(struct sshkey *k);
regress/usr.bin/ssh/unittests/sshkey/common.h
20
const BIGNUM *rsa_p(struct sshkey *k);
regress/usr.bin/ssh/unittests/sshkey/common.h
21
const BIGNUM *rsa_q(struct sshkey *k);
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
41
public_fuzz(struct sshkey *k)
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
50
if (test_is_fast() || sshkey_type_plain(k->type) == KEY_MLDSA44_ED25519)
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
56
ASSERT_INT_EQ(sshkey_putb(k, buf), 0);
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
71
sig_fuzz(struct sshkey *k, const char *sig_alg)
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
80
if (test_is_fast() || sshkey_type_plain(k->type) == KEY_MLDSA44_ED25519)
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
85
ASSERT_INT_EQ(sshkey_sign(k, &sig, &l, c, sizeof(c),
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
89
ASSERT_INT_EQ(sshkey_verify(k, sig, l, c, sizeof(c), NULL, 0, NULL), 0);
regress/usr.bin/ssh/unittests/sshkey/test_fuzz.c
96
ASSERT_INT_NE(sshkey_verify(k, fuzz_ptr(fuzz), fuzz_len(fuzz),
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
108
signature_test(struct sshkey *k, struct sshkey *bad, const char *sig_alg,
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
114
ASSERT_INT_EQ(sshkey_sign(k, &sig, &len, d, l, sig_alg,
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
118
ASSERT_INT_EQ(sshkey_verify(k, sig, len, d, l, NULL, 0, NULL), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
122
ASSERT_INT_NE(sshkey_verify(k, sig, len, d, l, NULL, 0, NULL), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
130
struct sshkey *k;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
137
ASSERT_INT_EQ(sshkey_generate(ktype, bits, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
138
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
141
ASSERT_INT_EQ(sshkey_sign(k, &sig, &len, d, l, sig_alg,
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
146
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
154
struct sshkey *k;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
161
ASSERT_INT_EQ(sshkey_generate(ktype, bits, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
162
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
164
ASSERT_INT_EQ(sshkey_sign(k, &sig, &len, d, l, sig_alg,
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
167
ASSERT_INT_EQ(sshkey_verify(k, sig, len, d, l, NULL, 0, NULL), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
171
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
191
signature_tests(struct sshkey *k, struct sshkey *bad, const char *sig_alg)
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
201
sshkey_type(k), lens[i]);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
203
signature_test(k, bad, sig_alg, buf, lens[i]);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
47
build_cert(struct sshbuf *b, struct sshkey *k, const char *type,
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
627
struct sshkey *k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
632
ASSERT_INT_EQ(sshkey_generate(KEY_RSA, 1024, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
633
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
634
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
635
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
641
ASSERT_INT_EQ(sshkey_generate(KEY_RSA, 2048, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
642
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
643
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
644
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
65
ASSERT_INT_EQ(sshkey_putb_plain(k, pk), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
650
ASSERT_INT_EQ(sshkey_generate(KEY_ECDSA, 256, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
651
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
652
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
653
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
659
ASSERT_INT_EQ(sshkey_generate(KEY_ECDSA, 384, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
660
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
661
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
662
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
668
ASSERT_INT_EQ(sshkey_generate(KEY_ECDSA, 521, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
669
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
670
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
671
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
678
ASSERT_INT_EQ(sshkey_generate(KEY_ED25519, 256, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
679
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
680
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
681
k = NULL;
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
687
ASSERT_INT_EQ(sshkey_generate(KEY_MLDSA44_ED25519, 256, &k), 0);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
688
ASSERT_PTR_NE(k, NULL);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
689
sshkey_free(k);
regress/usr.bin/ssh/unittests/sshkey/test_sshkey.c
690
k = NULL;
regress/usr.bin/ssh/unittests/sshsig/tests.c
53
struct sshkey *k, *sign_key;
regress/usr.bin/ssh/unittests/sshsig/tests.c
57
k = load_key(keyname);
regress/usr.bin/ssh/unittests/sshsig/tests.c
65
ASSERT_INT_EQ(sshkey_equal(k, sign_key), 1);
regress/usr.bin/ssh/unittests/sshsig/tests.c
66
sshkey_free(k);
sbin/atactl/atactl.c
1635
int i, k, threshold_exceeded = 0;
sbin/atactl/atactl.c
1676
for (k = 0; k < 6; k++) {
sbin/atactl/atactl.c
1678
b = attr[i].raw[6 - k];
sbin/atactl/atactl.c
1679
raw[k + k] = hex[b >> 4];
sbin/atactl/atactl.c
1680
raw[k + k + 1] = hex[b & 0x0f];
sbin/atactl/atactl.c
1682
raw[k + k] = '\0';
sbin/dhcp6leased/parse.y
233
kw_cmp(const void *k, const void *e)
sbin/dhcp6leased/parse.y
235
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/dhcpleased/bpf.c
170
if (dhcp_bpf_wfilter[7].k == 0x1fff)
sbin/dhcpleased/bpf.c
171
dhcp_bpf_wfilter[7].k = htons(IP_MF|IP_OFFMASK);
sbin/dhcpleased/parse.y
354
kw_cmp(const void *k, const void *e)
sbin/dhcpleased/parse.y
356
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/fsck_ffs/utilities.c
445
int j, k, cg;
sbin/fsck_ffs/utilities.c
455
for (k = 1; k < frags; k++)
sbin/fsck_ffs/utilities.c
456
if (testbmap(i + j + k))
sbin/fsck_ffs/utilities.c
458
if (k < frags) {
sbin/fsck_ffs/utilities.c
459
j += k;
sbin/fsck_ffs/utilities.c
469
for (k = 0; k < frags; k++) {
sbin/fsck_ffs/utilities.c
470
setbmap(i + j + k);
sbin/fsck_ffs/utilities.c
471
clrbit(cg_blksfree(cgp), baseblk + k);
sbin/fsck_msdos/dir.c
418
int i, j, k, last;
sbin/fsck_msdos/dir.c
531
for (k = 1; k < 11 && t < longName + sizeof(longName); k += 2) {
sbin/fsck_msdos/dir.c
532
if (!p[k] && !p[k + 1])
sbin/fsck_msdos/dir.c
534
*t++ = p[k];
sbin/fsck_msdos/dir.c
538
if (p[k + 1])
sbin/fsck_msdos/dir.c
541
if (k >= 11)
sbin/fsck_msdos/dir.c
542
for (k = 14; k < 26 && t < longName + sizeof(longName); k += 2) {
sbin/fsck_msdos/dir.c
543
if (!p[k] && !p[k + 1])
sbin/fsck_msdos/dir.c
545
*t++ = p[k];
sbin/fsck_msdos/dir.c
546
if (p[k + 1])
sbin/fsck_msdos/dir.c
549
if (k >= 26)
sbin/fsck_msdos/dir.c
550
for (k = 28; k < 32 && t < longName + sizeof(longName); k += 2) {
sbin/fsck_msdos/dir.c
551
if (!p[k] && !p[k + 1])
sbin/fsck_msdos/dir.c
553
*t++ = p[k];
sbin/fsck_msdos/dir.c
554
if (p[k + 1])
sbin/fsck_msdos/dir.c
594
for (k = 7; k >= 0 && dirent.name[k] == ' '; k--)
sbin/fsck_msdos/dir.c
595
dirent.name[k] = '\0';
sbin/fsck_msdos/dir.c
596
if (k < 0)
sbin/fsck_msdos/dir.c
597
k = 0;
sbin/fsck_msdos/dir.c
598
if (dirent.name[k] != '\0')
sbin/fsck_msdos/dir.c
599
k++;
sbin/fsck_msdos/dir.c
616
dirent.name[k++] = '.';
sbin/fsck_msdos/dir.c
618
dirent.name[k++] = p[j+8];
sbin/fsck_msdos/dir.c
619
dirent.name[k] = '\0';
sbin/fsck_msdos/dir.c
620
for (k--; k >= 0 && dirent.name[k] == ' '; k--)
sbin/fsck_msdos/dir.c
621
dirent.name[k] = '\0';
sbin/fsck_msdos/dir.c
644
mod |= k = removede(f, boot, fat,
sbin/fsck_msdos/dir.c
653
if (k & FSDIRMOD)
sbin/fsck_msdos/dir.c
817
mod |= k = checksize(boot, fat, p, &dirent);
sbin/fsck_msdos/dir.c
818
if (k & FSDIRMOD)
sbin/growfs/growfs.c
628
int i, k;
sbin/growfs/growfs.c
733
k = rounddown(osblock.fs_size-cbase,
sbin/growfs/growfs.c
741
k = 0;
sbin/growfs/growfs.c
746
k++;
sbin/growfs/growfs.c
748
if (k)
sbin/growfs/growfs.c
749
acg.cg_frsum[k]--;
sbin/growfs/growfs.c
750
acg.cg_frsum[k + j]++;
sbin/growfs/growfs.c
766
k = 0;
sbin/growfs/growfs.c
771
k++;
sbin/growfs/growfs.c
773
if (k)
sbin/growfs/growfs.c
774
acg.cg_frsum[k]--;
sbin/growfs/growfs.c
775
acg.cg_frsum[k + j]++;
sbin/iked/crypto_api.h
37
int crypto_kem_sntrup761_enc(unsigned char *cstr, unsigned char *k,
sbin/iked/crypto_api.h
39
int crypto_kem_sntrup761_dec(unsigned char *k,
sbin/iked/parse.y
1555
kw_cmp(const void *k, const void *e)
sbin/iked/parse.y
1557
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/iked/sntrup761.c
1168
static void HashSession(unsigned char *k,int b,const unsigned char *y,const unsigned char *z)
sbin/iked/sntrup761.c
1183
Hash_prefix(k,b,x,sizeof x);
sbin/iked/sntrup761.c
1208
static void Encap(unsigned char *c,unsigned char *k,const unsigned char *pk)
sbin/iked/sntrup761.c
1217
HashSession(k,1,r_enc,c);
sbin/iked/sntrup761.c
1231
static void Decap(unsigned char *k,const unsigned char *c,const unsigned char *sk)
sbin/iked/sntrup761.c
1246
HashSession(k,1+mask,r_enc,c);
sbin/iked/sntrup761.c
1258
int crypto_kem_sntrup761_enc(unsigned char *c,unsigned char *k,const unsigned char *pk)
sbin/iked/sntrup761.c
1260
Encap(c,k,pk);
sbin/iked/sntrup761.c
1264
int crypto_kem_sntrup761_dec(unsigned char *k,const unsigned char *c,const unsigned char *sk)
sbin/iked/sntrup761.c
1266
Decap(k,c,sk);
sbin/iked/sntrup761.c
841
static void Expand(uint32 *L,const unsigned char *k)
sbin/iked/sntrup761.c
844
crypto_stream_aes256ctr((unsigned char *) L,4*p,aes_nonce,k);
sbin/iked/sntrup761.c
874
static void Generator(Fq *G,const unsigned char *k)
sbin/iked/sntrup761.c
879
Expand(L,k);
sbin/ipsecctl/parse.y
1037
kw_cmp(const void *k, const void *e)
sbin/ipsecctl/parse.y
1039
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/isakmpd/message.c
1968
u_int32_t i, j, k = 0;
sbin/isakmpd/message.c
1978
if (++k % 32 == 0) {
sbin/isakmpd/message.c
1982
} else if (k % 4 == 0)
sbin/ncheck_ffs/ncheck_ffs.c
132
ufsino_t k = *(ufsino_t *)key;
sbin/ncheck_ffs/ncheck_ffs.c
135
if (k < v)
sbin/ncheck_ffs/ncheck_ffs.c
137
else if (k > v)
sbin/pfctl/parse.y
5473
kw_cmp(const void *k, const void *e)
sbin/pfctl/parse.y
5475
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/pfctl/parse.y
6344
kw_casecmp(const void *k, const void *e)
sbin/pfctl/parse.y
6346
return (strcasecmp(k, ((const struct keywords *)e)->k_name));
sbin/unwind/libunbound/dnscrypt/dnscrypt.h
137
size_t dnsc_shared_secrets_sizefunc(void *k, void *d);
sbin/unwind/libunbound/dnscrypt/dnscrypt.h
147
void dnsc_shared_secrets_delkeyfunc(void *k, void* arg);
sbin/unwind/libunbound/dnscrypt/dnscrypt.h
157
size_t dnsc_nonces_sizefunc(void *k, void *d);
sbin/unwind/libunbound/dnscrypt/dnscrypt.h
167
void dnsc_nonces_delkeyfunc(void *k, void* arg);
sbin/unwind/libunbound/iterator/iter_scrub.c
846
struct ub_packed_rrset_key* k;
sbin/unwind/libunbound/iterator/iter_scrub.c
851
k = alloc_special_obtain(env->alloc);
sbin/unwind/libunbound/iterator/iter_scrub.c
852
if(!k)
sbin/unwind/libunbound/iterator/iter_scrub.c
854
k->entry.data = NULL;
sbin/unwind/libunbound/iterator/iter_scrub.c
855
if(!parse_copy_decompress_rrset(pkt, msg, rrset, NULL, k)) {
sbin/unwind/libunbound/iterator/iter_scrub.c
856
alloc_special_release(env->alloc, k);
sbin/unwind/libunbound/iterator/iter_scrub.c
859
d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/iterator/iter_scrub.c
861
ref.key = k;
sbin/unwind/libunbound/iterator/iter_scrub.c
862
ref.id = k->id;
sbin/unwind/libunbound/services/authzone.c
164
get_rrset_ttl(struct ub_packed_rrset_key* k)
sbin/unwind/libunbound/services/authzone.c
167
k->entry.data;
sbin/unwind/libunbound/services/authzone.c
213
struct ub_packed_rrset_key* k = msg->rep->rrsets[i];
sbin/unwind/libunbound/services/authzone.c
214
if(ntohs(k->rk.type) == type && k->rk.dname_len == nmlen &&
sbin/unwind/libunbound/services/authzone.c
215
ntohs(k->rk.rrset_class) == dclass &&
sbin/unwind/libunbound/services/authzone.c
216
query_dname_compare(k->rk.dname, nm) == 0)
sbin/unwind/libunbound/services/cache/dns.c
1027
struct dns_msg* msg = rrset_msg(rrset, region, now, &k);
sbin/unwind/libunbound/services/cache/dns.c
1054
struct dns_msg* msg = rrset_msg(rrset, region, now, &k);
sbin/unwind/libunbound/services/cache/dns.c
1068
while(!dname_is_root(k.qname)) {
sbin/unwind/libunbound/services/cache/dns.c
1070
&& !dname_strict_subdomain_c(k.qname, dpname))
sbin/unwind/libunbound/services/cache/dns.c
1072
dname_remove_label(&k.qname, &k.qname_len);
sbin/unwind/libunbound/services/cache/dns.c
1073
h = query_info_hash(&k, flags);
sbin/unwind/libunbound/services/cache/dns.c
1074
e = slabhash_lookup(env->msg_cache, h, &k, 0);
sbin/unwind/libunbound/services/cache/dns.c
1075
if(!e && k.qtype != LDNS_RR_TYPE_A &&
sbin/unwind/libunbound/services/cache/dns.c
1077
k.qtype = LDNS_RR_TYPE_A;
sbin/unwind/libunbound/services/cache/dns.c
1078
h = query_info_hash(&k, flags);
sbin/unwind/libunbound/services/cache/dns.c
1079
e = slabhash_lookup(env->msg_cache, h, &k, 0);
sbin/unwind/libunbound/services/cache/dns.c
1088
&& (msg=tomsg(env, &k, data, region, now, 0, scratch))) {
sbin/unwind/libunbound/services/cache/dns.c
1099
k.qtype = qtype;
sbin/unwind/libunbound/services/cache/dns.c
151
struct query_info k;
sbin/unwind/libunbound/services/cache/dns.c
154
k.qname = qname;
sbin/unwind/libunbound/services/cache/dns.c
155
k.qname_len = qnamelen;
sbin/unwind/libunbound/services/cache/dns.c
156
k.qtype = qtype;
sbin/unwind/libunbound/services/cache/dns.c
157
k.qclass = qclass;
sbin/unwind/libunbound/services/cache/dns.c
158
k.local_alias = NULL;
sbin/unwind/libunbound/services/cache/dns.c
159
h = query_info_hash(&k, flags);
sbin/unwind/libunbound/services/cache/dns.c
160
slabhash_remove(env->msg_cache, h, &k);
sbin/unwind/libunbound/services/cache/dns.c
308
struct query_info k;
sbin/unwind/libunbound/services/cache/dns.c
311
k.qname = qname;
sbin/unwind/libunbound/services/cache/dns.c
312
k.qname_len = qnamelen;
sbin/unwind/libunbound/services/cache/dns.c
313
k.qtype = qtype;
sbin/unwind/libunbound/services/cache/dns.c
314
k.qclass = qclass;
sbin/unwind/libunbound/services/cache/dns.c
315
k.local_alias = NULL;
sbin/unwind/libunbound/services/cache/dns.c
316
h = query_info_hash(&k, flags);
sbin/unwind/libunbound/services/cache/dns.c
317
e = slabhash_lookup(env->msg_cache, h, &k, wr);
sbin/unwind/libunbound/services/cache/dns.c
950
struct query_info k;
sbin/unwind/libunbound/services/cache/dns.c
956
k.qname = qname;
sbin/unwind/libunbound/services/cache/dns.c
957
k.qname_len = qnamelen;
sbin/unwind/libunbound/services/cache/dns.c
958
k.qtype = qtype;
sbin/unwind/libunbound/services/cache/dns.c
959
k.qclass = qclass;
sbin/unwind/libunbound/services/cache/dns.c
960
k.local_alias = NULL;
sbin/unwind/libunbound/services/cache/dns.c
961
h = query_info_hash(&k, flags);
sbin/unwind/libunbound/services/cache/dns.c
962
e = slabhash_lookup(env->msg_cache, h, &k, 0);
sbin/unwind/libunbound/services/cache/dns.c
984
struct dns_msg* msg = synth_dname_msg(rrset, region, now, &k,
sbin/unwind/libunbound/services/cache/infra.c
1002
k->namelen = namelen;
sbin/unwind/libunbound/services/cache/infra.c
1003
k->name = memdup(name, namelen);
sbin/unwind/libunbound/services/cache/infra.c
1004
if(!k->name) {
sbin/unwind/libunbound/services/cache/infra.c
1005
free(k);
sbin/unwind/libunbound/services/cache/infra.c
1009
lock_rw_init(&k->entry.lock);
sbin/unwind/libunbound/services/cache/infra.c
1010
k->entry.hash = h;
sbin/unwind/libunbound/services/cache/infra.c
1011
k->entry.key = k;
sbin/unwind/libunbound/services/cache/infra.c
1012
k->entry.data = d;
sbin/unwind/libunbound/services/cache/infra.c
1015
slabhash_insert(infra->domain_rates, h, &k->entry, d, NULL);
sbin/unwind/libunbound/services/cache/infra.c
1024
struct ip_rate_key* k = (struct ip_rate_key*)calloc(1, sizeof(*k));
sbin/unwind/libunbound/services/cache/infra.c
1026
if(!k || !d) {
sbin/unwind/libunbound/services/cache/infra.c
1027
free(k);
sbin/unwind/libunbound/services/cache/infra.c
1031
k->addr = *addr;
sbin/unwind/libunbound/services/cache/infra.c
1032
k->addrlen = addrlen;
sbin/unwind/libunbound/services/cache/infra.c
1033
lock_rw_init(&k->entry.lock);
sbin/unwind/libunbound/services/cache/infra.c
1034
k->entry.hash = h;
sbin/unwind/libunbound/services/cache/infra.c
1035
k->entry.key = k;
sbin/unwind/libunbound/services/cache/infra.c
1036
k->entry.data = d;
sbin/unwind/libunbound/services/cache/infra.c
1040
slabhash_insert(infra->client_ip_rates, h, &k->entry, d, NULL);
sbin/unwind/libunbound/services/cache/infra.c
106
infra_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
sbin/unwind/libunbound/services/cache/infra.c
108
struct infra_key* key = (struct infra_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
124
rate_sizefunc(void* k, void* ATTR_UNUSED(d))
sbin/unwind/libunbound/services/cache/infra.c
126
struct rate_key* key = (struct rate_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
145
rate_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
sbin/unwind/libunbound/services/cache/infra.c
147
struct rate_key* key = (struct rate_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
515
struct infra_key k;
sbin/unwind/libunbound/services/cache/infra.c
516
k.addrlen = addrlen;
sbin/unwind/libunbound/services/cache/infra.c
517
memcpy(&k.addr, addr, addrlen);
sbin/unwind/libunbound/services/cache/infra.c
518
k.namelen = namelen;
sbin/unwind/libunbound/services/cache/infra.c
519
k.zonename = name;
sbin/unwind/libunbound/services/cache/infra.c
520
k.entry.hash = hash_infra(addr, addrlen, name);
sbin/unwind/libunbound/services/cache/infra.c
521
k.entry.key = (void*)&k;
sbin/unwind/libunbound/services/cache/infra.c
522
k.entry.data = NULL;
sbin/unwind/libunbound/services/cache/infra.c
523
return slabhash_lookup(infra->hosts, k.entry.hash, &k, wr);
sbin/unwind/libunbound/services/cache/infra.c
82
infra_sizefunc(void* k, void* ATTR_UNUSED(d))
sbin/unwind/libunbound/services/cache/infra.c
84
struct infra_key* key = (struct infra_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
940
size_t ip_rate_sizefunc(void* k, void* ATTR_UNUSED(d))
sbin/unwind/libunbound/services/cache/infra.c
942
struct ip_rate_key* key = (struct ip_rate_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
955
void ip_rate_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
sbin/unwind/libunbound/services/cache/infra.c
957
struct ip_rate_key* key = (struct ip_rate_key*)k;
sbin/unwind/libunbound/services/cache/infra.c
995
struct rate_key* k = (struct rate_key*)calloc(1, sizeof(*k));
sbin/unwind/libunbound/services/cache/infra.c
997
if(!k || !d) {
sbin/unwind/libunbound/services/cache/infra.c
998
free(k);
sbin/unwind/libunbound/services/cache/infra.h
471
size_t infra_sizefunc(void* k, void* d);
sbin/unwind/libunbound/services/cache/infra.h
477
void infra_delkeyfunc(void* k, void* arg);
sbin/unwind/libunbound/services/cache/infra.h
483
size_t rate_sizefunc(void* k, void* d);
sbin/unwind/libunbound/services/cache/infra.h
489
void rate_delkeyfunc(void* k, void* arg);
sbin/unwind/libunbound/services/cache/infra.h
495
size_t ip_rate_sizefunc(void* k, void* d);
sbin/unwind/libunbound/services/cache/rrset.c
212
struct ub_packed_rrset_key* k = ref->key;
sbin/unwind/libunbound/services/cache/rrset.c
213
hashvalue_type h = k->entry.hash;
sbin/unwind/libunbound/services/cache/rrset.c
214
uint16_t rrset_type = ntohs(k->rk.type);
sbin/unwind/libunbound/services/cache/rrset.c
216
log_assert(ref->id != 0 && k->id != 0);
sbin/unwind/libunbound/services/cache/rrset.c
217
log_assert(k->rk.dname != NULL);
sbin/unwind/libunbound/services/cache/rrset.c
219
if((e=slabhash_lookup(&r->table, h, k, 0)) != 0) {
sbin/unwind/libunbound/services/cache/rrset.c
229
equal = rrsetdata_equal((struct packed_rrset_data*)k->entry.
sbin/unwind/libunbound/services/cache/rrset.c
231
if(!need_to_update_rrset(k->entry.data, e->data, timenow,
sbin/unwind/libunbound/services/cache/rrset.c
236
ub_packed_rrset_parsedelete(k, alloc);
sbin/unwind/libunbound/services/cache/rrset.c
250
slabhash_insert(&r->table, h, &k->entry, k->entry.data, alloc);
sbin/unwind/libunbound/services/cache/rrset.c
355
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)e->key;
sbin/unwind/libunbound/services/cache/rrset.c
359
(k->rk.flags & PACKED_RRSET_UPSTREAM_0TTL) &&
sbin/unwind/libunbound/services/cache/rrset.c
368
return k;
sbin/unwind/libunbound/services/outside_network.c
1733
size_t k;
sbin/unwind/libunbound/services/outside_network.c
1813
for(k=0; k<num_ports; k++) {
sbin/unwind/libunbound/services/outside_network.c
1932
int i, k;
sbin/unwind/libunbound/services/outside_network.c
1934
for(k=0; k<outnet->ip4_ifs[i].inuse; k++) {
sbin/unwind/libunbound/services/outside_network.c
1936
out[k];
sbin/unwind/libunbound/services/outside_network.c
1945
int i, k;
sbin/unwind/libunbound/services/outside_network.c
1947
for(k=0; k<outnet->ip6_ifs[i].inuse; k++) {
sbin/unwind/libunbound/services/outside_network.c
1949
out[k];
sbin/unwind/libunbound/services/outside_network.c
3965
int k;
sbin/unwind/libunbound/services/outside_network.c
3978
for(k=0; k<outnet->num_ip4; k++)
sbin/unwind/libunbound/services/outside_network.c
3979
s += if_get_mem(&outnet->ip4_ifs[k]);
sbin/unwind/libunbound/services/outside_network.c
3980
for(k=0; k<outnet->num_ip6; k++)
sbin/unwind/libunbound/services/outside_network.c
3981
s += if_get_mem(&outnet->ip6_ifs[k]);
sbin/unwind/libunbound/util/data/msgreply.c
718
msgreply_sizefunc(void* k, void* d)
sbin/unwind/libunbound/util/data/msgreply.c
720
struct msgreply_entry* q = (struct msgreply_entry*)k;
sbin/unwind/libunbound/util/data/msgreply.c
731
query_entry_delete(void *k, void* ATTR_UNUSED(arg))
sbin/unwind/libunbound/util/data/msgreply.c
733
struct msgreply_entry* q = (struct msgreply_entry*)k;
sbin/unwind/libunbound/util/data/msgreply.h
373
size_t msgreply_sizefunc(void* k, void* d);
sbin/unwind/libunbound/util/data/packed_rrset.c
130
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)key;
sbin/unwind/libunbound/util/data/packed_rrset.c
132
k->id = 0;
sbin/unwind/libunbound/util/data/packed_rrset.c
133
free(k->rk.dname);
sbin/unwind/libunbound/util/data/packed_rrset.c
134
k->rk.dname = NULL;
sbin/unwind/libunbound/util/data/packed_rrset.c
135
alloc_special_release(a, k);
sbin/unwind/libunbound/util/data/packed_rrset.c
72
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)key;
sbin/unwind/libunbound/util/data/packed_rrset.c
74
size_t s = sizeof(struct ub_packed_rrset_key) + k->rk.dname_len;
sbin/unwind/libunbound/util/data/packed_rrset.c
75
s += packed_rrset_sizeof(d) + lock_get_mem(&k->entry.lock);
sbin/unwind/libunbound/util/data/packed_rrset.h
285
struct packed_rrset_key* k;
sbin/unwind/libunbound/util/siphash.c
90
int siphash(const uint8_t *in, const size_t inlen, const uint8_t *k,
sbin/unwind/libunbound/util/siphash.c
97
uint64_t k0 = U8TO64_LE(k);
sbin/unwind/libunbound/util/siphash.c
98
uint64_t k1 = U8TO64_LE(k + 8);
sbin/unwind/libunbound/util/siphash.h
41
int siphash(const uint8_t *in, const size_t inlen, const uint8_t *k,
sbin/unwind/libunbound/util/storage/lookup3.c
1013
uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;
sbin/unwind/libunbound/util/storage/lookup3.c
1032
for (k=0; k<MAXPAIR; k+=2)
sbin/unwind/libunbound/util/storage/lookup3.c
1038
a[i] ^= (k<<j);
sbin/unwind/libunbound/util/storage/lookup3.c
1039
a[i] ^= (k>>(8-j));
sbin/unwind/libunbound/util/storage/lookup3.c
1041
b[i] ^= ((k+1)<<j);
sbin/unwind/libunbound/util/storage/lookup3.c
1042
b[i] ^= ((k+1)>>(8-j));
sbin/unwind/libunbound/util/storage/lookup3.c
1057
if (k>z) z=k;
sbin/unwind/libunbound/util/storage/lookup3.c
1058
if (k==MAXPAIR)
sbin/unwind/libunbound/util/storage/lookup3.c
118
#define rot(x,k) (((x)<<(k)) | ((x)>>(32-(k))))
sbin/unwind/libunbound/util/storage/lookup3.c
233
const uint32_t *k, /* the key, an array of uint32_t values */
sbin/unwind/libunbound/util/storage/lookup3.c
245
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
246
b += k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
247
c += k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
250
k += 3;
sbin/unwind/libunbound/util/storage/lookup3.c
256
case 3 : c+=k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
259
case 2 : b+=k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
262
case 1 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
285
const uint32_t *k, /* the key, an array of uint32_t values */
sbin/unwind/libunbound/util/storage/lookup3.c
299
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
300
b += k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
301
c += k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
304
k += 3;
sbin/unwind/libunbound/util/storage/lookup3.c
310
case 3 : c+=k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
313
case 2 : b+=k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
316
case 1 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
366
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
sbin/unwind/libunbound/util/storage/lookup3.c
374
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
375
b += k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
376
c += k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
379
k += 3;
sbin/unwind/libunbound/util/storage/lookup3.c
396
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
397
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
398
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
399
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
400
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
401
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
402
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
403
case 5 : b+=k[1]&0xff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
404
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
405
case 3 : a+=k[0]&0xffffff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
406
case 2 : a+=k[0]&0xffff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
407
case 1 : a+=k[0]&0xff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
413
k8 = (const uint8_t *)k;
sbin/unwind/libunbound/util/storage/lookup3.c
416
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
426
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
436
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
450
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
sbin/unwind/libunbound/util/storage/lookup3.c
456
a += k[0] + (((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
457
b += k[2] + (((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
458
c += k[4] + (((uint32_t)k[5])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
461
k += 6;
sbin/unwind/libunbound/util/storage/lookup3.c
465
k8 = (const uint8_t *)k;
sbin/unwind/libunbound/util/storage/lookup3.c
468
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
469
b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
470
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
475
case 10: c+=k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
476
b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
477
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
482
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
483
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
488
case 6 : b+=k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
489
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
494
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
499
case 2 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
507
const uint8_t *k = (const uint8_t *)key;
sbin/unwind/libunbound/util/storage/lookup3.c
512
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
513
a += ((uint32_t)k[1])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
514
a += ((uint32_t)k[2])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
515
a += ((uint32_t)k[3])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
516
b += k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
517
b += ((uint32_t)k[5])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
518
b += ((uint32_t)k[6])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
519
b += ((uint32_t)k[7])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
520
c += k[8];
sbin/unwind/libunbound/util/storage/lookup3.c
521
c += ((uint32_t)k[9])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
522
c += ((uint32_t)k[10])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
523
c += ((uint32_t)k[11])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
526
k += 12;
sbin/unwind/libunbound/util/storage/lookup3.c
532
case 12: c+=((uint32_t)k[11])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
535
case 11: c+=((uint32_t)k[10])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
538
case 10: c+=((uint32_t)k[9])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
541
case 9 : c+=k[8];
sbin/unwind/libunbound/util/storage/lookup3.c
544
case 8 : b+=((uint32_t)k[7])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
547
case 7 : b+=((uint32_t)k[6])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
550
case 6 : b+=((uint32_t)k[5])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
553
case 5 : b+=k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
556
case 4 : a+=((uint32_t)k[3])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
559
case 3 : a+=((uint32_t)k[2])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
562
case 2 : a+=((uint32_t)k[1])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
565
case 1 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
602
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
sbin/unwind/libunbound/util/storage/lookup3.c
610
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
611
b += k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
612
c += k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
615
k += 3;
sbin/unwind/libunbound/util/storage/lookup3.c
632
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
633
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
634
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
635
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
636
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
637
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
638
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
639
case 5 : b+=k[1]&0xff; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
640
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
641
case 3 : a+=k[0]&0xffffff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
642
case 2 : a+=k[0]&0xffff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
643
case 1 : a+=k[0]&0xff; break;
sbin/unwind/libunbound/util/storage/lookup3.c
649
k8 = (const uint8_t *)k;
sbin/unwind/libunbound/util/storage/lookup3.c
652
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
662
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
672
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
686
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
sbin/unwind/libunbound/util/storage/lookup3.c
692
a += k[0] + (((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
693
b += k[2] + (((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
694
c += k[4] + (((uint32_t)k[5])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
697
k += 6;
sbin/unwind/libunbound/util/storage/lookup3.c
701
k8 = (const uint8_t *)k;
sbin/unwind/libunbound/util/storage/lookup3.c
704
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
705
b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
706
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
711
case 10: c+=k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
712
b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
713
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
718
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
719
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
724
case 6 : b+=k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
725
a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
730
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
sbin/unwind/libunbound/util/storage/lookup3.c
735
case 2 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
743
const uint8_t *k = (const uint8_t *)key;
sbin/unwind/libunbound/util/storage/lookup3.c
748
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
749
a += ((uint32_t)k[1])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
750
a += ((uint32_t)k[2])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
751
a += ((uint32_t)k[3])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
752
b += k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
753
b += ((uint32_t)k[5])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
754
b += ((uint32_t)k[6])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
755
b += ((uint32_t)k[7])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
756
c += k[8];
sbin/unwind/libunbound/util/storage/lookup3.c
757
c += ((uint32_t)k[9])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
758
c += ((uint32_t)k[10])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
759
c += ((uint32_t)k[11])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
762
k += 12;
sbin/unwind/libunbound/util/storage/lookup3.c
768
case 12: c+=((uint32_t)k[11])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
771
case 11: c+=((uint32_t)k[10])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
774
case 10: c+=((uint32_t)k[9])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
777
case 9 : c+=k[8];
sbin/unwind/libunbound/util/storage/lookup3.c
780
case 8 : b+=((uint32_t)k[7])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
783
case 7 : b+=((uint32_t)k[6])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
786
case 6 : b+=((uint32_t)k[5])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
789
case 5 : b+=k[4];
sbin/unwind/libunbound/util/storage/lookup3.c
792
case 4 : a+=((uint32_t)k[3])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
795
case 3 : a+=((uint32_t)k[2])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
798
case 2 : a+=((uint32_t)k[1])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
801
case 1 : a+=k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
831
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
sbin/unwind/libunbound/util/storage/lookup3.c
839
a += k[0];
sbin/unwind/libunbound/util/storage/lookup3.c
840
b += k[1];
sbin/unwind/libunbound/util/storage/lookup3.c
841
c += k[2];
sbin/unwind/libunbound/util/storage/lookup3.c
844
k += 3;
sbin/unwind/libunbound/util/storage/lookup3.c
861
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
862
case 11: c+=k[2]&0xffffff00; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
863
case 10: c+=k[2]&0xffff0000; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
864
case 9 : c+=k[2]&0xff000000; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
865
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
866
case 7 : b+=k[1]&0xffffff00; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
867
case 6 : b+=k[1]&0xffff0000; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
868
case 5 : b+=k[1]&0xff000000; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
869
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
870
case 3 : a+=k[0]&0xffffff00; break;
sbin/unwind/libunbound/util/storage/lookup3.c
871
case 2 : a+=k[0]&0xffff0000; break;
sbin/unwind/libunbound/util/storage/lookup3.c
872
case 1 : a+=k[0]&0xff000000; break;
sbin/unwind/libunbound/util/storage/lookup3.c
878
k8 = (const uint8_t *)k;
sbin/unwind/libunbound/util/storage/lookup3.c
881
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
891
case 8 : b+=k[1]; a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
901
case 4 : a+=k[0]; break;
sbin/unwind/libunbound/util/storage/lookup3.c
915
const uint8_t *k = (const uint8_t *)key;
sbin/unwind/libunbound/util/storage/lookup3.c
920
a += ((uint32_t)k[0])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
921
a += ((uint32_t)k[1])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
922
a += ((uint32_t)k[2])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
923
a += ((uint32_t)k[3]);
sbin/unwind/libunbound/util/storage/lookup3.c
924
b += ((uint32_t)k[4])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
925
b += ((uint32_t)k[5])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
926
b += ((uint32_t)k[6])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
927
b += ((uint32_t)k[7]);
sbin/unwind/libunbound/util/storage/lookup3.c
928
c += ((uint32_t)k[8])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
929
c += ((uint32_t)k[9])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
930
c += ((uint32_t)k[10])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
931
c += ((uint32_t)k[11]);
sbin/unwind/libunbound/util/storage/lookup3.c
934
k += 12;
sbin/unwind/libunbound/util/storage/lookup3.c
940
case 12: c+=k[11];
sbin/unwind/libunbound/util/storage/lookup3.c
943
case 11: c+=((uint32_t)k[10])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
946
case 10: c+=((uint32_t)k[9])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
949
case 9 : c+=((uint32_t)k[8])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
952
case 8 : b+=k[7];
sbin/unwind/libunbound/util/storage/lookup3.c
955
case 7 : b+=((uint32_t)k[6])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
958
case 6 : b+=((uint32_t)k[5])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
961
case 5 : b+=((uint32_t)k[4])<<24;
sbin/unwind/libunbound/util/storage/lookup3.c
964
case 4 : a+=k[3];
sbin/unwind/libunbound/util/storage/lookup3.c
967
case 3 : a+=((uint32_t)k[2])<<8;
sbin/unwind/libunbound/util/storage/lookup3.c
970
case 2 : a+=((uint32_t)k[1])<<16;
sbin/unwind/libunbound/util/storage/lookup3.c
973
case 1 : a+=((uint32_t)k[0])<<24;
sbin/unwind/libunbound/util/storage/lookup3.h
53
uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);
sbin/unwind/libunbound/util/storage/lookup3.h
62
uint32_t hashlittle(const void *k, size_t length, uint32_t initval);
sbin/unwind/libunbound/util/storage/slabhash.c
193
static void delkey(struct slabhash_testkey* k) {
sbin/unwind/libunbound/util/storage/slabhash.c
194
lock_rw_destroy(&k->entry.lock); free(k);}
sbin/unwind/libunbound/validator/autotrust.c
1476
key_ttl(struct ub_packed_rrset_key* k)
sbin/unwind/libunbound/validator/autotrust.c
1478
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/autotrust.c
635
struct ub_packed_rrset_key* k;
sbin/unwind/libunbound/validator/autotrust.c
638
k = (struct ub_packed_rrset_key*)calloc(1, sizeof(*k));
sbin/unwind/libunbound/validator/autotrust.c
639
if(!k)
sbin/unwind/libunbound/validator/autotrust.c
641
k->rk.type = htons(sldns_wirerr_get_type(rr, rr_len, dname_len));
sbin/unwind/libunbound/validator/autotrust.c
642
k->rk.rrset_class = htons(sldns_wirerr_get_class(rr, rr_len, dname_len));
sbin/unwind/libunbound/validator/autotrust.c
643
k->rk.dname_len = dname_len;
sbin/unwind/libunbound/validator/autotrust.c
644
k->rk.dname = memdup(rr, dname_len);
sbin/unwind/libunbound/validator/autotrust.c
645
if(!k->rk.dname) {
sbin/unwind/libunbound/validator/autotrust.c
646
free(k);
sbin/unwind/libunbound/validator/autotrust.c
649
return k;
sbin/unwind/libunbound/validator/val_anchor.c
1197
struct ta_key *k;
sbin/unwind/libunbound/validator/val_anchor.c
1206
for(k = ta->keylist; k; k = k->next) {
sbin/unwind/libunbound/validator/val_anchor.c
1207
s += sizeof(*k) + k->len;
sbin/unwind/libunbound/validator/val_anchor.c
263
struct ta_key* k;
sbin/unwind/libunbound/validator/val_anchor.c
264
for(k = ta->keylist; k; k = k->next) {
sbin/unwind/libunbound/validator/val_anchor.c
265
if(k->type == type && k->len == rdata_len &&
sbin/unwind/libunbound/validator/val_anchor.c
266
memcmp(k->data, rdata, rdata_len) == 0)
sbin/unwind/libunbound/validator/val_anchor.c
267
return k;
sbin/unwind/libunbound/validator/val_anchor.c
276
struct ta_key* k = (struct ta_key*)malloc(sizeof(*k));
sbin/unwind/libunbound/validator/val_anchor.c
277
if(!k)
sbin/unwind/libunbound/validator/val_anchor.c
279
memset(k, 0, sizeof(*k));
sbin/unwind/libunbound/validator/val_anchor.c
280
k->data = memdup(rdata, rdata_len);
sbin/unwind/libunbound/validator/val_anchor.c
281
if(!k->data) {
sbin/unwind/libunbound/validator/val_anchor.c
282
free(k);
sbin/unwind/libunbound/validator/val_anchor.c
285
k->len = rdata_len;
sbin/unwind/libunbound/validator/val_anchor.c
286
k->type = type;
sbin/unwind/libunbound/validator/val_anchor.c
287
return k;
sbin/unwind/libunbound/validator/val_anchor.c
307
struct ta_key* k;
sbin/unwind/libunbound/validator/val_anchor.c
333
k = anchor_new_ta_key(rdata, rdata_len, type);
sbin/unwind/libunbound/validator/val_anchor.c
334
if(!k) {
sbin/unwind/libunbound/validator/val_anchor.c
342
k->next = ta->keylist;
sbin/unwind/libunbound/validator/val_anchor.c
343
ta->keylist = k;
sbin/unwind/libunbound/validator/val_kcache.c
128
struct key_entry_key* k = key_cache_search(kcache, name,
sbin/unwind/libunbound/validator/val_kcache.c
130
if(k) {
sbin/unwind/libunbound/validator/val_kcache.c
133
k->entry.data;
sbin/unwind/libunbound/validator/val_kcache.c
137
key_entry_copy_toregion(k, region);
sbin/unwind/libunbound/validator/val_kcache.c
138
lock_rw_unlock(&k->entry.lock);
sbin/unwind/libunbound/validator/val_kcache.c
141
lock_rw_unlock(&k->entry.lock);
sbin/unwind/libunbound/validator/val_kcache.c
86
struct key_entry_key* k = key_entry_copy(kkey, copy_reason);
sbin/unwind/libunbound/validator/val_kcache.c
87
if(!k)
sbin/unwind/libunbound/validator/val_kcache.c
89
key_entry_hash(k);
sbin/unwind/libunbound/validator/val_kcache.c
90
slabhash_insert(kcache->slab, k->entry.hash, &k->entry,
sbin/unwind/libunbound/validator/val_kcache.c
91
k->entry.data, NULL);
sbin/unwind/libunbound/validator/val_kentry.c
261
struct key_entry_key** k, struct key_entry_data** d)
sbin/unwind/libunbound/validator/val_kentry.c
263
*k = regional_alloc(region, sizeof(**k));
sbin/unwind/libunbound/validator/val_kentry.c
264
if(!*k)
sbin/unwind/libunbound/validator/val_kentry.c
266
memset(*k, 0, sizeof(**k));
sbin/unwind/libunbound/validator/val_kentry.c
267
(*k)->entry.key = *k;
sbin/unwind/libunbound/validator/val_kentry.c
268
(*k)->name = regional_alloc_init(region, name, namelen);
sbin/unwind/libunbound/validator/val_kentry.c
269
if(!(*k)->name)
sbin/unwind/libunbound/validator/val_kentry.c
271
(*k)->namelen = namelen;
sbin/unwind/libunbound/validator/val_kentry.c
272
(*k)->key_class = dclass;
sbin/unwind/libunbound/validator/val_kentry.c
276
(*k)->entry.data = *d;
sbin/unwind/libunbound/validator/val_kentry.c
286
struct key_entry_key* k;
sbin/unwind/libunbound/validator/val_kentry.c
288
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
sbin/unwind/libunbound/validator/val_kentry.c
299
return k;
sbin/unwind/libunbound/validator/val_kentry.c
309
struct key_entry_key* k;
sbin/unwind/libunbound/validator/val_kentry.c
313
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
sbin/unwind/libunbound/validator/val_kentry.c
332
return k;
sbin/unwind/libunbound/validator/val_kentry.c
341
struct key_entry_key* k;
sbin/unwind/libunbound/validator/val_kentry.c
343
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
sbin/unwind/libunbound/validator/val_kentry.c
354
return k;
sbin/unwind/libunbound/validator/val_neg.c
1044
static int nsec3_no_type(struct ub_packed_rrset_key* k, uint16_t t)
sbin/unwind/libunbound/validator/val_neg.c
1046
int count = (int)((struct packed_rrset_data*)k->entry.data)->count;
sbin/unwind/libunbound/validator/val_neg.c
1049
if(nsec3_has_type(k, i, t))
sbin/unwind/libunbound/validator/val_neg.c
1076
struct ub_packed_rrset_key* r, *k = rrset_cache_lookup(rrset_cache,
sbin/unwind/libunbound/validator/val_neg.c
1079
if(!k) return NULL;
sbin/unwind/libunbound/validator/val_neg.c
1080
d = k->entry.data;
sbin/unwind/libunbound/validator/val_neg.c
1085
lock_rw_unlock(&k->entry.lock);
sbin/unwind/libunbound/validator/val_neg.c
1090
(qtype == LDNS_RR_TYPE_NSEC && nsec_has_type(k, checktype)) ||
sbin/unwind/libunbound/validator/val_neg.c
1091
(qtype == LDNS_RR_TYPE_NSEC3 && !nsec3_no_type(k, checktype))
sbin/unwind/libunbound/validator/val_neg.c
1093
lock_rw_unlock(&k->entry.lock);
sbin/unwind/libunbound/validator/val_neg.c
1097
r = packed_rrset_copy_region(k, region, now);
sbin/unwind/libunbound/validator/val_neg.c
1099
lock_rw_unlock(&k->entry.lock);
sbin/unwind/libunbound/validator/val_nsec.c
54
rrset_get_ttl(struct ub_packed_rrset_key* k)
sbin/unwind/libunbound/validator/val_nsec.c
56
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
100
rrset_get_sigcount(struct ub_packed_rrset_key* k)
sbin/unwind/libunbound/validator/val_sigcrypt.c
102
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1056
insert_can_owner(sldns_buffer* buf, struct ub_packed_rrset_key* k,
sbin/unwind/libunbound/validator/val_sigcrypt.c
1060
int fqdn_labels = dname_signame_label_count(k->rk.dname);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1064
sldns_buffer_write(buf, k->rk.dname, k->rk.dname_len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1066
*can_owner_len = k->rk.dname_len;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1073
uint8_t* nm = k->rk.dname;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1074
size_t len = k->rk.dname_len;
sbin/unwind/libunbound/validator/val_sigcrypt.c
113
rrset_get_sig_keytag(struct ub_packed_rrset_key* k, size_t sig_idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
116
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1271
struct ub_packed_rrset_key* k, uint8_t* sig, size_t siglen,
sbin/unwind/libunbound/validator/val_sigcrypt.c
1275
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1294
canonical_sort(k, d, *sortree, rrs);
sbin/unwind/libunbound/validator/val_sigcrypt.c
131
rrset_get_sig_algo(struct ub_packed_rrset_key* k, size_t sig_idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
1312
else insert_can_owner(buf, k, sig, &can_owner,
sbin/unwind/libunbound/validator/val_sigcrypt.c
1314
sldns_buffer_write(buf, &k->rk.type, 2);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1315
sldns_buffer_write(buf, &k->rk.rrset_class, 2);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1319
canonicalize_rdata(buf, k, d->rr_len[walk->rr_idx]);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1326
if(ntohs(k->rk.type) == LDNS_RR_TYPE_NSEC &&
sbin/unwind/libunbound/validator/val_sigcrypt.c
1328
k->rk.dname = regional_alloc_init(qstate->region, can_owner,
sbin/unwind/libunbound/validator/val_sigcrypt.c
133
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1330
if(!k->rk.dname)
sbin/unwind/libunbound/validator/val_sigcrypt.c
1332
k->rk.dname_len = can_owner_len;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1341
struct ub_packed_rrset_key* k)
sbin/unwind/libunbound/validator/val_sigcrypt.c
1344
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1361
canonical_sort(k, d, sortree, rrs);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1377
sldns_buffer_write(buf, k->rk.dname, k->rk.dname_len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1379
can_owner_len = k->rk.dname_len;
sbin/unwind/libunbound/validator/val_sigcrypt.c
1381
sldns_buffer_write(buf, &k->rk.type, 2);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1382
sldns_buffer_write(buf, &k->rk.rrset_class, 2);
sbin/unwind/libunbound/validator/val_sigcrypt.c
1386
canonicalize_rdata(buf, k, d->rr_len[walk->rr_idx]);
sbin/unwind/libunbound/validator/val_sigcrypt.c
142
rrset_get_rdata(struct ub_packed_rrset_key* k, size_t idx, uint8_t** rdata,
sbin/unwind/libunbound/validator/val_sigcrypt.c
145
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
sbin/unwind/libunbound/validator/val_sigcrypt.c
152
dnskey_get_flags(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
157
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
172
dnskey_get_protocol(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
176
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
183
dnskey_get_algo(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
187
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
195
dnskey_get_pubkey(struct ub_packed_rrset_key* k, size_t idx,
sbin/unwind/libunbound/validator/val_sigcrypt.c
200
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
211
ds_get_key_algo(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
215
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
222
ds_get_digest_algo(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
226
rrset_get_rdata(k, idx, &rdata, &len);
sbin/unwind/libunbound/validator/val_sigcrypt.c
255
ds_get_sigdata(struct ub_packed_rrset_key* k, size_t idx, uint8_t** digest,
sbin/unwind/libunbound/validator/val_sigcrypt.c
260
rrset_get_rdata(k, idx, &rdata, &rdlen);
sbin/unwind/libunbound/validator/val_sigcrypt.c
277
ds_digest_size_algo(struct ub_packed_rrset_key* k, size_t idx)
sbin/unwind/libunbound/validator/val_sigcrypt.c
279
return ds_digest_size_supported(ds_get_digest_algo(k, idx));
sbin/unwind/libunbound/validator/val_sigcrypt.h
235
int ds_get_key_algo(struct ub_packed_rrset_key* k, size_t idx);
sbin/unwind/libunbound/validator/val_sigcrypt.h
243
int dnskey_get_algo(struct ub_packed_rrset_key* k, size_t idx);
sbin/unwind/libunbound/validator/val_sigcrypt.h
251
uint16_t dnskey_get_flags(struct ub_packed_rrset_key* k, size_t idx);
sbin/unwind/libunbound/validator/val_sigcrypt.h
354
struct sldns_buffer* buf, struct ub_packed_rrset_key* k);
sbin/unwind/parse.y
410
kw_cmp(const void *k, const void *e)
sbin/unwind/parse.y
412
return (strcmp(k, ((const struct keywords *)e)->k_name));
sbin/wsconsctl/keysym.c
120
ksym2name(int k)
sbin/wsconsctl/keysym.c
129
key.value = k;
sbin/wsconsctl/keysym.c
143
snprintf(tmp, sizeof(tmp), "unknown_%d", k);
sbin/wsconsctl/mousecfg.c
127
enum wsmousecfg k;
sbin/wsconsctl/mousecfg.c
152
for (k = range[i][0]; k <= range[i][1]; k++, param++) {
sbin/wsconsctl/mousecfg.c
153
param->key = k;
sbin/wsconsctl/wsconsctl.c
177
int k;
sbin/wsconsctl/wsconsctl.c
180
k = c - argv[i];
sbin/wsconsctl/wsconsctl.c
182
k, k, argv[i]);
sys/arch/alpha/include/bus.h
627
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/alpha/include/bus.h
628
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/alpha/include/bus.h
629
#define bus_dmamem_unmap(t, k, s) \
sys/arch/alpha/include/bus.h
630
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/amd64/amd64/powernow-k8.c
316
int j, k, n;
sys/arch/amd64/amd64/powernow-k8.c
319
k = -1;
sys/arch/amd64/amd64/powernow-k8.c
324
k = n;
sys/arch/amd64/amd64/powernow-k8.c
341
return k;
sys/arch/amd64/include/bus.h
637
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/amd64/include/bus.h
638
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/amd64/include/bus.h
639
#define bus_dmamem_unmap(t, k, s) \
sys/arch/amd64/include/bus.h
640
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/amd64/stand/libsa/exec_i386.c
327
int i, j, k, kern_pml4, kern_pml3, kern_pml2, kern_pml1;
sys/arch/amd64/stand/libsa/exec_i386.c
349
k = kern_pml1;
sys/arch/amd64/stand/libsa/exec_i386.c
351
k = 0;
sys/arch/amd64/stand/libsa/exec_i386.c
356
for (j = k; j < NPDPG; j++)
sys/arch/arm/include/bus.h
740
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/arm/include/bus.h
741
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/arm/include/bus.h
742
#define bus_dmamem_unmap(t, k, s) \
sys/arch/arm/include/bus.h
743
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/arm64/arm64/pmap.c
1025
int j, k, l;
sys/arch/arm64/arm64/pmap.c
1033
for (k = 0; k < VP_IDX2_CNT; k++) {
sys/arch/arm64/arm64/pmap.c
1034
vp3 = vp2->vp[k];
sys/arch/arm64/arm64/pmap.c
1037
vp2->vp[k] = NULL;
sys/arch/arm64/arm64/pmap.c
1191
int i, j, k;
sys/arch/arm64/arm64/pmap.c
1237
for (k = 0; k <= VP_IDX3_CNT - 1; k++) {
sys/arch/arm64/arm64/pmap.c
1238
if (vp3->vp[k] == NULL) {
sys/arch/arm64/arm64/pmap.c
1242
vp3->vp[k] = pted;
sys/arch/arm64/arm64/pmap.c
1283
int i, j, k;
sys/arch/arm64/arm64/pmap.c
1377
for (k = 0; k <= VP_IDX3_CNT - 1; k++) {
sys/arch/arm64/arm64/pmap.c
1382
vp3->vp[k] = pted;
sys/arch/arm64/dev/aplcpu.c
301
int i, j, k;
sys/arch/arm64/dev/aplcpu.c
321
for (k = 0; k < ot->ot_nopp; k++) {
sys/arch/arm64/dev/aplcpu.c
322
if (ot->ot_opp[k].opp_level != opp_level)
sys/arch/arm64/dev/aplcpu.c
324
opp_hz = MAX(opp_hz, ot->ot_opp[k].opp_hz);
sys/arch/arm64/dev/aplcpu.c
345
int i, j, k, timo;
sys/arch/arm64/dev/aplcpu.c
382
for (k = 0; k < ot->ot_nopp; k++) {
sys/arch/arm64/dev/aplcpu.c
383
if (ot->ot_opp[k].opp_hz <= level_hz &&
sys/arch/arm64/dev/aplcpu.c
384
ot->ot_opp[k].opp_level >= opp_level)
sys/arch/arm64/dev/aplcpu.c
385
opp_level = ot->ot_opp[k].opp_level;
sys/arch/arm64/include/bus.h
449
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/arm64/include/bus.h
450
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/arm64/include/bus.h
451
#define bus_dmamem_unmap(t, k, s) \
sys/arch/arm64/include/bus.h
452
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/armv7/exynos/exclock.c
335
exclock_decode_pll_clk(enum clocks pll, unsigned int r, unsigned int k)
sys/arch/armv7/exynos/exclock.c
369
k = k & 0xffff;
sys/arch/armv7/exynos/exclock.c
371
fout = (m + k / 65536) * (freq / (p * (1 << s)));
sys/arch/armv7/exynos/exclock.c
373
k = k & 0xfff;
sys/arch/armv7/exynos/exclock.c
375
fout = (m + k / 1024) * (freq / (p * (1 << s)));
sys/arch/hppa/hppa/machdep.c
732
int i, j, k;
sys/arch/hppa/hppa/machdep.c
739
for (k = 0; k < pdc_cache.it_loop; k++)
sys/arch/hppa/hppa/machdep.c
751
for (k = 0; k < pdc_cache.dt_loop; k++)
sys/arch/hppa/include/bus.h
395
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/hppa/include/bus.h
396
(*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
sys/arch/hppa/include/bus.h
397
#define bus_dmamem_unmap(t, k, s) \
sys/arch/hppa/include/bus.h
398
(*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
sys/arch/i386/i386/powernow-k7.c
303
int j, k, n;
sys/arch/i386/i386/powernow-k7.c
306
k = -1;
sys/arch/i386/i386/powernow-k7.c
309
k = n;
sys/arch/i386/i386/powernow-k7.c
329
return k;
sys/arch/i386/i386/powernow-k8.c
369
int j, k, n;
sys/arch/i386/i386/powernow-k8.c
372
k = -1;
sys/arch/i386/i386/powernow-k8.c
377
k = n;
sys/arch/i386/i386/powernow-k8.c
394
return k;
sys/arch/i386/include/bus.h
637
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/i386/include/bus.h
638
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/i386/include/bus.h
639
#define bus_dmamem_unmap(t, k, s) \
sys/arch/i386/include/bus.h
640
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/landisk/include/bus.h
537
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/landisk/include/bus.h
538
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/landisk/include/bus.h
539
#define bus_dmamem_unmap(t, k, s) \
sys/arch/landisk/include/bus.h
540
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/loongson/include/bus.h
456
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/loongson/include/bus.h
457
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/loongson/include/bus.h
458
#define bus_dmamem_unmap(t, k, s) \
sys/arch/loongson/include/bus.h
459
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/macppc/dev/xlights.c
234
int k, nsamp;
sys/arch/macppc/dev/xlights.c
254
for (k = 0; k < nsamp;) {
sys/arch/macppc/dev/xlights.c
258
if ((k % 4) == 0)
sys/arch/macppc/dev/xlights.c
260
if ((k % 16) == 0)
sys/arch/macppc/dev/xlights.c
265
k++;
sys/arch/macppc/include/bus.h
587
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/macppc/include/bus.h
588
(*(t)->_dmamem_map)((t)->_cookie, (sg), (n), (s), (k), (f))
sys/arch/macppc/include/bus.h
589
#define bus_dmamem_unmap(t, k, s) \
sys/arch/macppc/include/bus.h
590
(*(t)->_dmamem_unmap)((t)->_cookie, (k), (s))
sys/arch/mips64/mips64/pmap.c
541
unsigned int k;
sys/arch/mips64/mips64/pmap.c
559
for (k = 0; k < NPTEPG; k++) {
sys/arch/mips64/mips64/pmap.c
560
if (pte[k] != PG_NV)
sys/arch/mips64/mips64/pmap.c
563
"index %u", pmap, pte, k);
sys/arch/octeon/include/bus.h
422
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/octeon/include/bus.h
423
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/octeon/include/bus.h
424
#define bus_dmamem_unmap(t, k, s) \
sys/arch/octeon/include/bus.h
425
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/powerpc/powerpc/pmap.c
1097
int first, i, k, try, tblidx, tbloff;
sys/arch/powerpc/powerpc/pmap.c
1127
for (k = 0; k < 16; k++)
sys/arch/powerpc/powerpc/pmap.c
1128
pm->pm_sr[k] = (seg + k) | SR_NOEXEC;
sys/arch/powerpc/powerpc/pmap.c
1438
int i, k;
sys/arch/powerpc/powerpc/pmap.c
1505
for (k = 0; k < VP_IDX2_SIZE; k++) {
sys/arch/powerpc/powerpc/pmap.c
1509
vp2->vp[k] = pted;
sys/arch/powerpc/powerpc/pmap.c
1531
for (k = 0; k < VP_IDX2_SIZE; k++) {
sys/arch/powerpc/powerpc/pmap.c
1535
vp2->vp[k] = pted;
sys/arch/powerpc64/include/bus.h
433
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/powerpc64/include/bus.h
434
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/powerpc64/include/bus.h
435
#define bus_dmamem_unmap(t, k, s) \
sys/arch/powerpc64/include/bus.h
436
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/riscv64/include/bus.h
459
#define bus_dmamem_map(t, sg, n, s, k, f) \
sys/arch/riscv64/include/bus.h
460
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
sys/arch/riscv64/include/bus.h
461
#define bus_dmamem_unmap(t, k, s) \
sys/arch/riscv64/include/bus.h
462
(*(t)->_dmamem_unmap)((t), (k), (s))
sys/arch/riscv64/riscv64/pmap.c
1113
int i, j, k;
sys/arch/riscv64/riscv64/pmap.c
1152
for (k = 0; k <= VP_IDX3_CNT - 1; k++) {
sys/arch/riscv64/riscv64/pmap.c
1153
if (vp3->vp[k] == NULL) {
sys/arch/riscv64/riscv64/pmap.c
1157
vp3->vp[k] = pted;
sys/arch/riscv64/riscv64/pmap.c
1228
int i, j, k;
sys/arch/riscv64/riscv64/pmap.c
1330
for (k = 0; k <= VP_IDX3_CNT - 1; k++) {
sys/arch/riscv64/riscv64/pmap.c
1335
vp3->vp[k] = pted;
sys/arch/riscv64/riscv64/pmap.c
967
int j, k, l;
sys/arch/riscv64/riscv64/pmap.c
980
for (k = 0; k < VP_IDX2_CNT; k++) {
sys/arch/riscv64/riscv64/pmap.c
981
vp3 = vp2->vp[k];
sys/arch/riscv64/riscv64/pmap.c
984
vp2->vp[k] = NULL;
sys/arch/sh/sh/pmap.c
1054
int i, j, k, n, map, asid;
sys/arch/sh/sh/pmap.c
1060
k = i & 0x7;
sys/arch/sh/sh/pmap.c
1061
map = __pmap_asid.map[k];
sys/arch/sh/sh/pmap.c
1063
if ((map & (1 << j)) == 0 && (k + j) != 0) {
sys/arch/sh/sh/pmap.c
1064
__pmap_asid.map[k] |= (1 << j);
sys/arch/sh/sh/pmap.c
1065
__pmap_asid.hint = (k << 5) + j;
sys/arch/sparc64/dev/ebus.c
311
int i, j, k;
sys/arch/sparc64/dev/ebus.c
338
for (k = 0; k < sc->sc_nintmap; k++) {
sys/arch/sparc64/dev/ebus.c
341
sc->sc_intmap[k].hi, sc->sc_intmap[k].lo,
sys/arch/sparc64/dev/ebus.c
342
sc->sc_intmap[k].intr));
sys/arch/sparc64/dev/ebus.c
343
if (hi == sc->sc_intmap[k].hi &&
sys/arch/sparc64/dev/ebus.c
344
lo == sc->sc_intmap[k].lo &&
sys/arch/sparc64/dev/ebus.c
345
intr == sc->sc_intmap[k].intr) {
sys/arch/sparc64/dev/ebus.c
347
sc->sc_intmap[k].cintr;
sys/arch/sparc64/dev/ebus.c
350
sc->sc_intmap[k].cintr));
sys/arch/sparc64/dev/lom.c
818
int i, j, k;
sys/arch/sparc64/dev/lom.c
834
k = LOM_IDX4_TEMP_NAME_START;
sys/arch/sparc64/dev/lom.c
835
while (k <= LOM_IDX4_TEMP_NAME_END) {
sys/arch/sparc64/dev/lom.c
836
error = lom_read(sc, k++, &val);
sys/arch/sparc64/dev/lom.c
865
k = LOM_IDX5_FAN_NAME_START;
sys/arch/sparc64/dev/lom.c
866
while (k <= LOM_IDX5_FAN_NAME_END) {
sys/arch/sparc64/dev/lom.c
867
error = lom_read(sc, k++, &val);
sys/arch/sparc64/dev/pcons.c
104
#define cn_check_magic(d, k, s) \
sys/arch/sparc64/dev/pcons.c
108
if ((k) == CNS_MAGIC_VAL(v)) { \
sys/arch/sparc64/fpu/fpu_explode.c
206
fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l)
sys/arch/sparc64/fpu/fpu_explode.c
218
f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
sys/arch/sparc64/fpu/fpu_explode.c
219
f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
sys/arch/sparc64/fpu/fpu_explode.c
221
frac |= j | k | l;
sys/arch/sparc64/include/bus.h
583
caddr_t *k, int f)
sys/arch/sparc64/include/bus.h
588
r = _BD_CALL(t, _dmamem_map)(t, t0, sg, n, s, k, f);
sys/arch/sparc64/include/bus.h
593
bus_dmamem_unmap(bus_dma_tag_t t, caddr_t k, size_t s)
sys/arch/sparc64/include/bus.h
597
_BD_CALL(t, _dmamem_unmap)(t, t0, k, s);
sys/arch/sparc64/sparc64/db_interface.c
747
long i, j, k, n;
sys/arch/sparc64/sparc64/db_interface.c
754
for (k=0; k<PDSZ; k++) {
sys/arch/sparc64/sparc64/db_interface.c
755
if ((ptbl = (paddr_t *)(u_long)ldxa((vaddr_t)&pdir[k], ASI_PHYS_CACHED))) {
sys/arch/sparc64/sparc64/db_interface.c
756
db_printf("\tptable %ld:%ld at %lx:\n", i, k, (long)ptbl);
sys/arch/sparc64/sparc64/db_interface.c
764
(unsigned long long)(((u_int64_t)i<<STSHIFT)|(k<<PDSHIFT)|((j-1)<<PTSHIFT)),
sys/arch/sparc64/sparc64/db_interface.c
767
(unsigned long long)(((u_int64_t)i<<STSHIFT)|(k<<PDSHIFT)|(j<<PTSHIFT)),
sys/arch/sparc64/sparc64/pmap.c
1069
int k;
sys/arch/sparc64/sparc64/pmap.c
1072
for (k = 0; page_size_map[k].mask; k++) {
sys/arch/sparc64/sparc64/pmap.c
1075
page_size_map[k].mask) == 0 &&
sys/arch/sparc64/sparc64/pmap.c
1076
page_size_map[k].mask <
sys/arch/sparc64/sparc64/pmap.c
1088
(tte + j) | data | page_size_map[k].code);
sys/arch/sparc64/sparc64/pmap.c
1488
int i, j, k;
sys/arch/sparc64/sparc64/pmap.c
1501
for (k=0; k<PDSZ; k++) {
sys/arch/sparc64/sparc64/pmap.c
1502
paddr_t pdirentp = (paddr_t)(u_long)&pdir[k];
sys/arch/sparc64/sparc64/pmap.c
1518
(unsigned long long)(((u_int64_t)i<<STSHIFT)|((u_int64_t)k<<PDSHIFT)|((u_int64_t)j<<PTSHIFT)));
sys/crypto/aes.c
337
int i, j, k, nk, nkf;
sys/crypto/aes.c
360
for (i = nk, j = 0, k = 0; i < nkf; i ++) {
sys/crypto/aes.c
363
tmp = sub_word(tmp) ^ Rcon[k];
sys/crypto/aes.c
371
k ++;
sys/crypto/blf.c
410
u_int16_t k;
sys/crypto/blf.c
432
for (k = 0; k < 256; k += 2) {
sys/crypto/blf.c
435
c->S[i][k] = data[0];
sys/crypto/blf.c
436
c->S[i][k + 1] = data[1];
sys/crypto/blf.c
448
u_int16_t k;
sys/crypto/blf.c
472
for (k = 0; k < 256; k += 2) {
sys/crypto/blf.c
477
c->S[i][k] = d[0];
sys/crypto/blf.c
478
c->S[i][k + 1] = d[1];
sys/crypto/blf.c
485
blf_key(blf_ctx *c, const u_int8_t *k, u_int16_t len)
sys/crypto/blf.c
491
Blowfish_expand0state(c, k, len);
sys/crypto/chacha_private.h
100
x->input[6] = U8TO32_LITTLE(k + 8);
sys/crypto/chacha_private.h
101
x->input[7] = U8TO32_LITTLE(k + 12);
sys/crypto/chacha_private.h
103
k += 16;
sys/crypto/chacha_private.h
108
x->input[8] = U8TO32_LITTLE(k + 0);
sys/crypto/chacha_private.h
109
x->input[9] = U8TO32_LITTLE(k + 4);
sys/crypto/chacha_private.h
110
x->input[10] = U8TO32_LITTLE(k + 8);
sys/crypto/chacha_private.h
111
x->input[11] = U8TO32_LITTLE(k + 12);
sys/crypto/chacha_private.h
94
chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)
sys/crypto/chacha_private.h
98
x->input[4] = U8TO32_LITTLE(k + 0);
sys/crypto/chacha_private.h
99
x->input[5] = U8TO32_LITTLE(k + 4);
sys/crypto/cryptosoft.c
105
int i, k, j, blks, ind, count, ivlen;
sys/crypto/cryptosoft.c
155
m = m_getptr(m, crd->crd_skip, &k);
sys/crypto/cryptosoft.c
166
if (m->m_len < k + blks && m->m_len != k) {
sys/crypto/cryptosoft.c
167
m_copydata(m, k, blks, blk);
sys/crypto/cryptosoft.c
208
m_copyback(m, k, blks, blk, M_NOWAIT);
sys/crypto/cryptosoft.c
211
m = m_getptr(m, k + blks, &k);
sys/crypto/cryptosoft.c
223
if (k == m->m_len) {
sys/crypto/cryptosoft.c
227
k = 0;
sys/crypto/cryptosoft.c
239
idat = mtod(m, unsigned char *) + k;
sys/crypto/cryptosoft.c
241
while (m->m_len >= k + blks && i > 0) {
sys/crypto/cryptosoft.c
274
k += blks;
sys/crypto/cryptosoft.c
281
ind = cuio_getptr(uio, count, &k);
sys/crypto/cryptosoft.c
292
if (uio->uio_iov[ind].iov_len < k + blks &&
sys/crypto/cryptosoft.c
293
uio->uio_iov[ind].iov_len != k) {
sys/crypto/cryptosoft.c
340
ind = cuio_getptr(uio, count, &k);
sys/crypto/cryptosoft.c
356
idat = (char *)uio->uio_iov[ind].iov_base + k;
sys/crypto/cryptosoft.c
358
while (uio->uio_iov[ind].iov_len >= k + blks &&
sys/crypto/cryptosoft.c
393
k += blks;
sys/crypto/cryptosoft.c
403
if (i > 0 && k == uio->uio_iov[ind].iov_len) {
sys/crypto/cryptosoft.c
404
k = 0;
sys/crypto/cryptosoft.c
752
int k;
sys/crypto/cryptosoft.c
890
for (k = 0; k < cri->cri_klen / 8; k++)
sys/crypto/cryptosoft.c
891
cri->cri_key[k] ^= HMAC_IPAD_VAL;
sys/crypto/cryptosoft.c
899
for (k = 0; k < cri->cri_klen / 8; k++)
sys/crypto/cryptosoft.c
900
cri->cri_key[k] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
sys/crypto/cryptosoft.c
908
for (k = 0; k < cri->cri_klen / 8; k++)
sys/crypto/cryptosoft.c
909
cri->cri_key[k] ^= HMAC_OPAD_VAL;
sys/crypto/idgen.c
67
idgen32_g(u_int8_t *key, int k, u_int16_t w)
sys/crypto/idgen.c
70
u_int o = k * 4;
sys/crypto/set_key.c
144
register u_int32_t *k;
sys/crypto/set_key.c
155
k = (u_int32_t *) schedule;
sys/crypto/set_key.c
207
*(k++) = ((t << 16L) | (s & 0x0000ffffL)) & 0xffffffffL;
sys/crypto/set_key.c
211
*(k++) = s & 0xffffffffL;
sys/dev/acpi/acpitz.c
37
#define KTOC(k) ((k - 2732) / 10)
sys/dev/acpi/dsdt.c
112
#define HASH_KEY(k) (((k) ^ HASH_OFF) % HASH_SIZE)
sys/dev/eisa/if_ep_eisa.c
113
u_int16_t k;
sys/dev/eisa/if_ep_eisa.c
133
k = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG);
sys/dev/eisa/if_ep_eisa.c
134
k = (k & 0x1f) * 0x10 + 0x200;
sys/dev/fdt/amliic.c
177
int timo, k;
sys/dev/fdt/amliic.c
190
for (k = 0; k < cmdlen; k++) {
sys/dev/fdt/amliic.c
192
SET_DATA(j++, ((uint8_t *)cmd)[k]);
sys/dev/fdt/amliic.c
211
for (k = 0; k < len; k++)
sys/dev/fdt/amliic.c
215
for (k = 0; k < len; k++) {
sys/dev/fdt/qcpwm.c
218
int i, j, k, m;
sys/dev/fdt/qcpwm.c
242
for (k = 0; k < nitems(qcpwm_pre_divs); k++) {
sys/dev/fdt/qcpwm.c
244
NS_PER_S * qcpwm_pre_divs[k] * res[i])
sys/dev/fdt/qcpwm.c
248
(NS_PER_S * qcpwm_pre_divs[k] * res[i]))
sys/dev/fdt/qcpwm.c
253
acycles = (NS_PER_S * qcpwm_pre_divs[k] *
sys/dev/fdt/qcpwm.c
260
divsel = k;
sys/dev/fdt/rkclock.c
5009
uint32_t p, m, s, k;
sys/dev/fdt/rkclock.c
5038
p = 2; m = 198; s = 1; k = 0;
sys/dev/fdt/rkclock.c
5041
p = 3; m = 550; s = 2; k = 0;
sys/dev/fdt/rkclock.c
5044
p = 3; m = 425; s = 2; k = 0;
sys/dev/fdt/rkclock.c
5047
p = 2; m = 262; s = 2; k = 9437;
sys/dev/fdt/rkclock.c
5050
p = 3; m = 400; s = 5; k = 0;
sys/dev/fdt/rkclock.c
5075
RK3588_CRU_PLL_K_MASK << 16 | k << RK3588_CRU_PLL_K_SHIFT);
sys/dev/fdt/rkclock.c
5095
uint32_t k, m, p, s;
sys/dev/fdt/rkclock.c
5104
k = (reg & RK3588_CRU_PLL_K_MASK) >> RK3588_CRU_PLL_K_SHIFT;
sys/dev/fdt/rkclock.c
5107
if (k) {
sys/dev/fdt/rkclock.c
5108
frac = ((24000000ULL * k) / (p * 65535));
sys/dev/fdt/ssdfb.c
482
int i, j, k;
sys/dev/fdt/ssdfb.c
501
for (k = 0; k < 8; k++) {
sys/dev/fdt/ssdfb.c
502
off = ri->ri_stride * (y1 + i + k);
sys/dev/fdt/ssdfb.c
506
*bit |= !!val << k;
sys/dev/fdt/sxiccmu.c
1009
uint32_t k, m, n, p;
sys/dev/fdt/sxiccmu.c
1018
k = A10_PLL1_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1022
return (24000000 * n * k) / (m * p);
sys/dev/fdt/sxiccmu.c
1139
uint32_t k, m, n, p;
sys/dev/fdt/sxiccmu.c
1144
k = A64_PLL_CPUX_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1148
return (24000000 * n * k) / (m * p);
sys/dev/fdt/sxiccmu.c
1349
uint32_t k, m, n, p;
sys/dev/fdt/sxiccmu.c
1358
k = H3_PLL_CPUX_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
1362
return (24000000 * n * k) / (m * p);
sys/dev/fdt/sxiccmu.c
1692
int k, n;
sys/dev/fdt/sxiccmu.c
1697
k = 1; n = 32;
sys/dev/fdt/sxiccmu.c
1698
while (k <= 4 && (24000000 * n * k) < freq)
sys/dev/fdt/sxiccmu.c
1699
k++;
sys/dev/fdt/sxiccmu.c
1700
while (n >= 1 && (24000000 * n * k) > freq)
sys/dev/fdt/sxiccmu.c
1709
reg |= ((k - 1) << A10_PLL1_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1753
int k, n;
sys/dev/fdt/sxiccmu.c
1758
k = 1; n = 32;
sys/dev/fdt/sxiccmu.c
1759
while (k <= 4 && (24000000 * n * k) < freq)
sys/dev/fdt/sxiccmu.c
1760
k++;
sys/dev/fdt/sxiccmu.c
1761
while (n >= 1 && (24000000 * n * k) > freq)
sys/dev/fdt/sxiccmu.c
1770
reg |= ((k - 1) << A10_PLL1_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1834
int k, n;
sys/dev/fdt/sxiccmu.c
1839
k = 1; n = 32;
sys/dev/fdt/sxiccmu.c
1840
while (k <= 4 && (24000000 * n * k) < freq)
sys/dev/fdt/sxiccmu.c
1841
k++;
sys/dev/fdt/sxiccmu.c
1842
while (n >= 1 && (24000000 * n * k) > freq)
sys/dev/fdt/sxiccmu.c
1851
reg |= ((k - 1) << A64_PLL_CPUX_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
1989
int k, n;
sys/dev/fdt/sxiccmu.c
1994
k = 1; n = 32;
sys/dev/fdt/sxiccmu.c
1995
while (k <= 4 && (24000000 * n * k) < freq)
sys/dev/fdt/sxiccmu.c
1996
k++;
sys/dev/fdt/sxiccmu.c
1997
while (n >= 1 && (24000000 * n * k) > freq)
sys/dev/fdt/sxiccmu.c
2011
reg |= ((k - 1) << H3_PLL_CPUX_FACTOR_K_SHIFT);
sys/dev/fdt/sxiccmu.c
663
uint32_t reg, k, m, n, freq;
sys/dev/fdt/sxiccmu.c
668
k = CCU_PLL6_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
675
return (freq * n * k) / m / 6; /* pll6_sata */
sys/dev/fdt/sxiccmu.c
677
return (freq * n * k) / 2; /* pll6_other */
sys/dev/fdt/sxiccmu.c
679
return (freq * n * k); /* pll6 */
sys/dev/fdt/sxiccmu.c
681
return (freq * n * k) / 4; /* pll6_div_4 */
sys/dev/fdt/sxiccmu.c
950
uint32_t k, m, n, p;
sys/dev/fdt/sxiccmu.c
959
k = A10_PLL1_FACTOR_K(reg) + 1;
sys/dev/fdt/sxiccmu.c
963
return (24000000 * n * k) / (m * p);
sys/dev/hid/hid.c
511
hid_report_size(const void *buf, int len, enum hid_kind k, u_int8_t id)
sys/dev/hid/hid.c
519
DPRINTF("hid_report_size: kind=%d id=%d\n", k, id);
sys/dev/hid/hid.c
520
for (d = hid_start_parse(buf, len, k); hid_get_item(d, &h); ) {
sys/dev/hid/hid.c
525
if (h.report_ID == id && h.kind == k) {
sys/dev/hid/hid.c
544
hid_locate(const void *desc, int size, uint32_t u, uint8_t id, enum hid_kind k,
sys/dev/hid/hid.c
551
DPRINTF("hid_locate: enter usage=0x%x kind=%d id=%d\n", u, k, id);
sys/dev/hid/hid.c
552
for (d = hid_start_parse(desc, size, k); hid_get_item(d, &h); ) {
sys/dev/hid/hid.c
555
if (h.kind == k && !(h.flags & HIO_CONST) &&
sys/dev/i2c/i2c_scan.c
1057
int i, j, k;
sys/dev/i2c/i2c_scan.c
1074
for (k = 0; k < sizeof(ignore_addrs); k++)
sys/dev/i2c/i2c_scan.c
1075
if (ignore_addrs[k] == addr)
sys/dev/i2c/i2c_scan.c
1077
if (k < sizeof(ignore_addrs))
sys/dev/ic/acx.c
1001
struct ieee80211_key *k;
sys/dev/ic/acx.c
1003
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/acx.c
1004
if ((m = ieee80211_encrypt(ic, m, k)) == NULL) {
sys/dev/ic/acx.c
509
struct ieee80211_key *k = &ic->ic_nw_keys[i];
sys/dev/ic/acx.c
511
if (k->k_len == 0)
sys/dev/ic/acx.c
515
error = sc->chip_set_wepkey(sc, k, i);
sys/dev/ic/acx100.c
689
acx100_set_wepkey(struct acx_softc *sc, struct ieee80211_key *k, int k_idx)
sys/dev/ic/acx100.c
694
if (k->k_len > ACX100_WEPKEY_LEN) {
sys/dev/ic/acx100.c
701
conf_wk.key_len = k->k_len;
sys/dev/ic/acx100.c
703
bcopy(k->k_key, conf_wk.key, k->k_len);
sys/dev/ic/ar5008.c
1446
ar5008_ccmp_encap(struct mbuf *m, u_int hdrlen, struct ieee80211_key *k)
sys/dev/ic/ar5008.c
1459
k->k_tsc++;
sys/dev/ic/ar5008.c
1460
ivp[0] = k->k_tsc;
sys/dev/ic/ar5008.c
1461
ivp[1] = k->k_tsc >> 8;
sys/dev/ic/ar5008.c
1463
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/ic/ar5008.c
1464
ivp[4] = k->k_tsc >> 16;
sys/dev/ic/ar5008.c
1465
ivp[5] = k->k_tsc >> 24;
sys/dev/ic/ar5008.c
1466
ivp[6] = k->k_tsc >> 32;
sys/dev/ic/ar5008.c
1467
ivp[7] = k->k_tsc >> 40;
sys/dev/ic/ar5008.c
1477
struct ieee80211_key *k = NULL;
sys/dev/ic/ar5008.c
1514
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/ar5008.c
1515
if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/ic/ar5008.c
1517
if (ar5008_ccmp_encap(m, hdrlen, k) != 0)
sys/dev/ic/ar5008.c
1520
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/ar5008.c
1522
k = NULL; /* skip hardware crypto further below */
sys/dev/ic/ar5008.c
1648
if (k != NULL) {
sys/dev/ic/ar5008.c
1650
if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/ic/ar5008.c
1659
entry = (uintptr_t)k->k_priv;
sys/dev/ic/ar5008.c
793
struct ieee80211_key *k;
sys/dev/ic/ar5008.c
807
k = ieee80211_get_rxkey(ic, m, ni);
sys/dev/ic/ar5008.c
808
if (k == NULL || k->k_cipher != IEEE80211_CIPHER_CCMP)
sys/dev/ic/ar5008.c
812
entry = (uintptr_t)k->k_priv;
sys/dev/ic/ar5008.c
813
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/ar5008.c
814
if (k->k_id >= IEEE80211_WEP_NKID ||
sys/dev/ic/ar5008.c
815
entry != k->k_id)
sys/dev/ic/ar5008.c
836
prsc = &k->k_rsc[tid];
sys/dev/ic/ar9003.c
1396
struct ieee80211_key *k = NULL;
sys/dev/ic/ar9003.c
1435
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/ar9003.c
1436
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/ar9003.c
1565
if (0 && k != NULL) {
sys/dev/ic/ar9003.c
1570
switch (k->k_cipher) {
sys/dev/ic/ar9003.c
1591
entry = (uintptr_t)k->k_priv;
sys/dev/ic/ath.c
1040
struct ieee80211_key *k = &ic->ic_nw_keys[i];
sys/dev/ic/ath.c
1041
if (k->k_len == 0)
sys/dev/ic/ath.c
1054
if (k->k_cipher == IEEE80211_CIPHER_WEP40)
sys/dev/ic/ath.c
1056
else if (k->k_cipher == IEEE80211_CIPHER_WEP104)
sys/dev/ic/ath.c
1060
bcopy(k->k_key, hk.wk_key, hk.wk_len);
sys/dev/ic/ath.c
1996
struct ieee80211_key *k;
sys/dev/ic/ath.c
2014
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/ath.c
2015
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/ic/athn.c
1018
struct ieee80211_key *k)
sys/dev/ic/athn.c
1025
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/ic/athn.c
1027
return ieee80211_set_key(ic, ni, k);
sys/dev/ic/athn.c
1030
if (!(k->k_flags & IEEE80211_KEY_GROUP)) {
sys/dev/ic/athn.c
1040
entry = k->k_id;
sys/dev/ic/athn.c
1044
k->k_priv = (void *)entry;
sys/dev/ic/athn.c
1047
key = k->k_key;
sys/dev/ic/athn.c
1059
if (!(k->k_flags & IEEE80211_KEY_GROUP)) {
sys/dev/ic/athn.c
1101
struct ieee80211_key *k)
sys/dev/ic/athn.c
1106
if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/ic/athn.c
1107
entry = (uintptr_t)k->k_priv;
sys/dev/ic/athn.c
1109
explicit_bzero(k, sizeof(*k));
sys/dev/ic/athn.c
1111
ieee80211_delete_key(ic, ni, k);
sys/dev/ic/atw.c
3556
struct ieee80211_key *k;
sys/dev/ic/atw.c
3614
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/atw.c
3615
m0 = ieee80211_encrypt(ic, m0, k);
sys/dev/ic/bwfm.c
2835
struct ieee80211_key *k)
sys/dev/ic/bwfm.c
2841
cmd.k = k;
sys/dev/ic/bwfm.c
2851
struct ieee80211_key *k = cmd->k;
sys/dev/ic/bwfm.c
2860
if ((k->k_flags & IEEE80211_KEY_GROUP) == 0 &&
sys/dev/ic/bwfm.c
2861
k->k_cipher != IEEE80211_CIPHER_WEP40 &&
sys/dev/ic/bwfm.c
2862
k->k_cipher != IEEE80211_CIPHER_WEP104)
sys/dev/ic/bwfm.c
2868
key.index = htole32(k->k_id);
sys/dev/ic/bwfm.c
2869
key.len = htole32(k->k_len);
sys/dev/ic/bwfm.c
2870
memcpy(key.data, k->k_key, sizeof(key.data));
sys/dev/ic/bwfm.c
2874
switch (k->k_cipher) {
sys/dev/ic/bwfm.c
2893
k->k_cipher);
sys/dev/ic/bwfm.c
2917
struct ieee80211_key *k)
sys/dev/ic/bwfm.c
2923
cmd.k = k;
sys/dev/ic/bwfm.c
2931
struct ieee80211_key *k = cmd->k;
sys/dev/ic/bwfm.c
2935
key.index = htole32(k->k_id);
sys/dev/ic/bwfmvar.h
132
struct ieee80211_key *k;
sys/dev/ic/bwi.c
7177
struct ieee80211_key *k;
sys/dev/ic/bwi.c
7227
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/bwi.c
7228
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/bwi.c
7812
int i, j, k, error;
sys/dev/ic/bwi.c
7832
for (k = 0; k < j; ++k) {
sys/dev/ic/bwi.c
7834
tbd->tbd_buf[k].tb_dmap);
sys/dev/ic/bwi.c
7859
for (k = 0; k < j; ++k) {
sys/dev/ic/bwi.c
7861
tbd->tbd_buf[k].tb_dmap);
sys/dev/ic/bwi.c
7933
int i, j, k, ntx, error;
sys/dev/ic/bwi.c
7951
for (k = 0; k < j; ++k) {
sys/dev/ic/bwi.c
7953
tbd->tbd_buf[k].tb_dmap);
sys/dev/ic/bwi.c
7979
for (k = 0; k < j; ++k) {
sys/dev/ic/bwi.c
7981
rbd->rbd_buf[k].rb_dmap);
sys/dev/ic/ciss.c
1296
int i, j, k = 0;
sys/dev/ic/ciss.c
1303
buf[k++] = i;
sys/dev/ic/ciss.c
1310
buf[k++] = drv;
sys/dev/ic/ciss.c
1313
if (!k)
sys/dev/ic/ciss.c
1316
ldp = malloc(sizeof(*ldp) + (k-1), M_DEVBUF, M_NOWAIT);
sys/dev/ic/ciss.c
1321
ldp->ndrives = k;
sys/dev/ic/ciss.c
1322
bcopy(buf, ldp->tgts, k);
sys/dev/ic/malo.c
1473
struct ieee80211_key *k;
sys/dev/ic/malo.c
1492
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/malo.c
1493
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/ic/qwx.c
1009
err = qwx_add_sta_key(sc, a->ni, a->k);
sys/dev/ic/qwx.c
1011
err = qwx_del_sta_key(sc, a->ni, a->k);
sys/dev/ic/qwx.c
1015
a->k = NULL;
sys/dev/ic/qwx.c
25238
struct ieee80211_node *ni, struct ieee80211_key *k, int delete_key)
sys/dev/ic/qwx.c
25254
switch (k->k_cipher) {
sys/dev/ic/qwx.c
25269
sc->sc_dev.dv_xname, k->k_cipher);
sys/dev/ic/qwx.c
25395
struct ieee80211_key *k = NULL;
sys/dev/ic/qwx.c
25444
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/qwx.c
25448
switch (k->k_cipher) {
sys/dev/ic/qwx.c
25474
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/qwx.c
25687
struct ieee80211_key *k;
sys/dev/ic/qwx.c
25690
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/qwx.c
25691
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/qwx.c
26347
struct ieee80211_key *k;
sys/dev/ic/qwx.c
26354
k = &ic->ic_nw_keys[ic->ic_def_txkey];
sys/dev/ic/qwx.c
26355
if ((k->k_flags & IEEE80211_KEY_GROUP) &&
sys/dev/ic/qwx.c
26356
k->k_cipher == IEEE80211_CIPHER_CCMP)
sys/dev/ic/qwx.c
26357
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/ic/qwx.c
26361
k = &ic->ic_nw_keys[ic->ic_igtk_kid];
sys/dev/ic/qwx.c
26362
if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/ic/qwx.c
26363
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/ic/qwx.c
728
struct ieee80211_key *k, int cmd)
sys/dev/ic/qwx.c
734
k->k_id > WMI_MAX_KEY_INDEX)
sys/dev/ic/qwx.c
739
a->k = k;
sys/dev/ic/qwx.c
749
struct ieee80211_key *k)
sys/dev/ic/qwx.c
754
k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/ic/qwx.c
755
k->k_cipher == IEEE80211_CIPHER_WEP104 ||
sys/dev/ic/qwx.c
756
k->k_cipher == IEEE80211_CIPHER_BIP)
sys/dev/ic/qwx.c
757
return ieee80211_set_key(ic, ni, k);
sys/dev/ic/qwx.c
759
return qwx_queue_setkey_cmd(ic, ni, k, QWX_ADD_KEY);
sys/dev/ic/qwx.c
764
struct ieee80211_key *k)
sys/dev/ic/qwx.c
769
k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/ic/qwx.c
770
k->k_cipher == IEEE80211_CIPHER_WEP104 ||
sys/dev/ic/qwx.c
771
k->k_cipher == IEEE80211_CIPHER_BIP) {
sys/dev/ic/qwx.c
772
ieee80211_delete_key(ic, ni, k);
sys/dev/ic/qwx.c
788
qwx_queue_setkey_cmd(ic, ni, k, QWX_DEL_KEY);
sys/dev/ic/qwx.c
793
uint8_t *macaddr, struct ieee80211_key *k, uint32_t flags,
sys/dev/ic/qwx.c
799
.key_idx = k->k_id,
sys/dev/ic/qwx.c
800
.key_len = k->k_len,
sys/dev/ic/qwx.c
801
.key_data = k->k_key,
sys/dev/ic/qwx.c
818
switch (k->k_cipher) {
sys/dev/ic/qwx.c
842
sc->sc_dev.dv_xname, k->k_cipher);
sys/dev/ic/qwx.c
899
struct ieee80211_key *k)
sys/dev/ic/qwx.c
921
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/qwx.c
923
peer->sec_type_grp = qwx_dp_tx_get_encrypt_type(k->k_cipher);
sys/dev/ic/qwx.c
926
peer->sec_type = qwx_dp_tx_get_encrypt_type(k->k_cipher);
sys/dev/ic/qwx.c
929
ret = qwx_wmi_install_key_cmd(sc, arvif, ni->ni_macaddr, k, flags, 0);
sys/dev/ic/qwx.c
936
ret = qwx_dp_peer_rx_pn_replay_config(sc, arvif, ni, k, 0);
sys/dev/ic/qwx.c
943
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/qwx.c
945
WMI_VDEV_PARAM_DEF_KEYID, k->k_id);
sys/dev/ic/qwx.c
948
sc->sc_dev.dv_xname, arvif->vdev_id, k->k_id, ret);
sys/dev/ic/qwx.c
966
struct ieee80211_key *k)
sys/dev/ic/qwx.c
972
ret = qwx_wmi_install_key_cmd(sc, arvif, ni->ni_macaddr, k, 0, 1);
sys/dev/ic/qwx.c
979
ret = qwx_dp_peer_rx_pn_replay_config(sc, arvif, ni, k, 1);
sys/dev/ic/qwx.c
986
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/qwxvar.h
1776
struct ieee80211_key *k;
sys/dev/ic/qwz.c
23066
struct ieee80211_node *ni, struct ieee80211_key *k, int delete_key)
sys/dev/ic/qwz.c
23080
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/qwz.c
23090
switch (k->k_cipher) {
sys/dev/ic/qwz.c
23105
sc->sc_dev.dv_xname, k->k_cipher);
sys/dev/ic/qwz.c
23258
struct ieee80211_key *k = NULL;
sys/dev/ic/qwz.c
23337
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/qwz.c
23341
switch (k->k_cipher) {
sys/dev/ic/qwz.c
23369
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/ic/qwz.c
575
struct ieee80211_key *k, int cmd)
sys/dev/ic/qwz.c
581
k->k_id > WMI_MAX_KEY_INDEX)
sys/dev/ic/qwz.c
586
a->k = k;
sys/dev/ic/qwz.c
596
struct ieee80211_key *k)
sys/dev/ic/qwz.c
601
k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/ic/qwz.c
602
k->k_cipher == IEEE80211_CIPHER_WEP104)
sys/dev/ic/qwz.c
603
return ieee80211_set_key(ic, ni, k);
sys/dev/ic/qwz.c
605
return qwz_queue_setkey_cmd(ic, ni, k, QWZ_ADD_KEY);
sys/dev/ic/qwz.c
610
struct ieee80211_key *k)
sys/dev/ic/qwz.c
615
k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/ic/qwz.c
616
k->k_cipher == IEEE80211_CIPHER_WEP104) {
sys/dev/ic/qwz.c
617
ieee80211_delete_key(ic, ni, k);
sys/dev/ic/qwz.c
633
qwz_queue_setkey_cmd(ic, ni, k, QWZ_DEL_KEY);
sys/dev/ic/qwz.c
638
uint8_t *macaddr, struct ieee80211_key *k, uint32_t flags,
sys/dev/ic/qwz.c
644
.key_idx = k->k_id,
sys/dev/ic/qwz.c
645
.key_len = k->k_len,
sys/dev/ic/qwz.c
646
.key_data = k->k_key,
sys/dev/ic/qwz.c
663
switch (k->k_cipher) {
sys/dev/ic/qwz.c
687
sc->sc_dev.dv_xname, k->k_cipher);
sys/dev/ic/qwz.c
717
struct ieee80211_key *k)
sys/dev/ic/qwz.c
734
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/qwz.c
739
ret = qwz_wmi_install_key_cmd(sc, arvif, ni->ni_macaddr, k, flags, 0);
sys/dev/ic/qwz.c
746
ret = qwz_dp_peer_rx_pn_replay_config(sc, arvif, ni, k, 0);
sys/dev/ic/qwz.c
753
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/qwz.c
779
struct ieee80211_key *k)
sys/dev/ic/qwz.c
785
ret = qwz_wmi_install_key_cmd(sc, arvif, ni->ni_macaddr, k, 0, 1);
sys/dev/ic/qwz.c
792
ret = qwz_dp_peer_rx_pn_replay_config(sc, arvif, ni, k, 1);
sys/dev/ic/qwz.c
799
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/qwz.c
822
err = qwz_add_sta_key(sc, a->ni, a->k);
sys/dev/ic/qwz.c
824
err = qwz_del_sta_key(sc, a->ni, a->k);
sys/dev/ic/qwz.c
828
a->k = NULL;
sys/dev/ic/qwzvar.h
1907
struct ieee80211_key *k;
sys/dev/ic/rt2560.c
1692
struct ieee80211_key *k;
sys/dev/ic/rt2560.c
1701
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/rt2560.c
1703
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/ic/rt2661.c
1692
struct ieee80211_key *k;
sys/dev/ic/rt2661.c
1702
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/ic/rt2661.c
1704
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/ic/rt2860.c
192
uint8_t n, r, k;
sys/dev/ic/rt2860.c
2294
rf = (rf & ~0x0f) | rt3090_freqs[i].k;
sys/dev/ic/rt2860.c
2359
rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
sys/dev/ic/rt2860.c
2978
struct ieee80211_key *k)
sys/dev/ic/rt2860.c
2991
switch (k->k_cipher) {
sys/dev/ic/rt2860.c
3008
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/rt2860.c
3010
base = RT2860_SKEY(0, k->k_id);
sys/dev/ic/rt2860.c
3016
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/ic/rt2860.c
3017
RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
sys/dev/ic/rt2860.c
3020
RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
sys/dev/ic/rt2860.c
3021
RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
sys/dev/ic/rt2860.c
3025
RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
sys/dev/ic/rt2860.c
3026
RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
sys/dev/ic/rt2860.c
3029
RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
sys/dev/ic/rt2860.c
3031
if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/ic/rt2860.c
3032
(k->k_flags & IEEE80211_KEY_TX)) {
sys/dev/ic/rt2860.c
3034
if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/ic/rt2860.c
3035
k->k_cipher == IEEE80211_CIPHER_WEP104) {
sys/dev/ic/rt2860.c
3043
iv[3] = k->k_id << 6;
sys/dev/ic/rt2860.c
3046
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/ic/rt2860.c
3047
iv[0] = k->k_tsc >> 8;
sys/dev/ic/rt2860.c
3049
iv[2] = k->k_tsc;
sys/dev/ic/rt2860.c
3051
iv[0] = k->k_tsc;
sys/dev/ic/rt2860.c
3052
iv[1] = k->k_tsc >> 8;
sys/dev/ic/rt2860.c
3055
iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/ic/rt2860.c
3056
iv[4] = k->k_tsc >> 16;
sys/dev/ic/rt2860.c
3057
iv[5] = k->k_tsc >> 24;
sys/dev/ic/rt2860.c
3058
iv[6] = k->k_tsc >> 32;
sys/dev/ic/rt2860.c
3059
iv[7] = k->k_tsc >> 40;
sys/dev/ic/rt2860.c
3064
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/rt2860.c
3067
attr &= ~(0xf << (k->k_id * 4));
sys/dev/ic/rt2860.c
3068
attr |= mode << (k->k_id * 4);
sys/dev/ic/rt2860.c
3081
struct ieee80211_key *k)
sys/dev/ic/rt2860.c
3087
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/rt2860.c
3090
attr &= ~(0xf << (k->k_id * 4));
sys/dev/ic/rtw.c
2713
struct ieee80211_key *k;
sys/dev/ic/rtw.c
2793
k = ieee80211_get_txkey(ic, wh, *nip);
sys/dev/ic/rtw.c
2794
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/ic/rtwn.c
1337
struct ieee80211_key *k)
sys/dev/ic/rtwn.c
1351
switch (k->k_cipher) {
sys/dev/ic/rtwn.c
1366
return (ieee80211_set_key(ic, ni, k));
sys/dev/ic/rtwn.c
1368
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/ic/rtwn.c
1370
entry = k->k_id;
sys/dev/ic/rtwn.c
1377
memcpy(keybuf, k->k_key, MIN(k->k_len, sizeof(keybuf)));
sys/dev/ic/rtwn.c
1387
SM(R92C_CAM_KEYID, k->k_id) |
sys/dev/ic/rtwn.c
1396
struct ieee80211_key *k)
sys/dev/ic/rtwn.c
1405
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/ic/rtwn.c
1406
entry = k->k_id;
sys/dev/ic/smc93cx6.c
107
for (k = start_addr; k < count + start_addr; k++) {
sys/dev/ic/smc93cx6.c
129
if ((k & (1 << i)) != 0)
sys/dev/ic/smc93cx6.c
135
if ((k & (1 << i)) != 0)
sys/dev/ic/smc93cx6.c
156
buf[k - start_addr] = v;
sys/dev/ic/smc93cx6.c
169
for (k = 0; k < count; k = k + 1) {
sys/dev/ic/smc93cx6.c
170
if (((k % 8) == 0) && (k != 0)) {
sys/dev/ic/smc93cx6.c
173
printf (" 0x%04x", buf[k]);
sys/dev/ic/smc93cx6.c
99
u_int k = 0;
sys/dev/isa/sch311x.c
100
#define SCHSIO_VOLT_MUV(x, k) (1000000 * (x) / 2560000 * (k))
sys/dev/pci/azalia.c
1919
int i, j, k;
sys/dev/pci/azalia.c
2041
for (k = this->nopins; k > j; k--)
sys/dev/pci/azalia.c
2042
this->opins[k] = this->opins[k - 1];
sys/dev/pci/azalia.c
2059
for (k = this->nopins_d; k > j; k--)
sys/dev/pci/azalia.c
2060
this->opins_d[k] = this->opins_d[k - 1];
sys/dev/pci/azalia.c
2077
for (k = this->nipins; k > j; k--)
sys/dev/pci/azalia.c
2078
this->ipins[k] = this->ipins[k - 1];
sys/dev/pci/azalia.c
2095
for (k = this->nipins_d; k > j; k--)
sys/dev/pci/azalia.c
2096
this->ipins_d[k] = this->ipins_d[k - 1];
sys/dev/pci/azalia.c
2137
int i, j, k, err;
sys/dev/pci/azalia.c
2172
for (k = 0; k < nconv; k++) {
sys/dev/pci/azalia.c
2173
if (conv == convs[k])
sys/dev/pci/azalia.c
2176
if (k == nconv)
sys/dev/pci/azalia.c
3363
int i, j, k;
sys/dev/pci/azalia.c
3395
for (k = 0; i < length && (k < 32 / bits); k++) {
sys/dev/pci/azalia.c
3396
conn = (result >> (k * bits)) & ((1 << bits) - 1);
sys/dev/pci/azalia.c
3419
for (k = 0; i < nconn && (k < 32 / bits); k++) {
sys/dev/pci/azalia.c
3420
conn = (result >> (k * bits)) & ((1 << bits) - 1);
sys/dev/pci/azalia_codec.c
1014
for (j = 0, k = 0;
sys/dev/pci/azalia_codec.c
1015
j < w->nconnections && k < 32; j++) {
sys/dev/pci/azalia_codec.c
1022
d->un.s.member[k].mask = 1 << j;
sys/dev/pci/azalia_codec.c
1023
strlcpy(d->un.s.member[k].label.name,
sys/dev/pci/azalia_codec.c
1026
k++;
sys/dev/pci/azalia_codec.c
1028
d->un.s.num_mem = k;
sys/dev/pci/azalia_codec.c
1029
if (k != 0)
sys/dev/pci/azalia_codec.c
1095
for (j = 0, k = 0;
sys/dev/pci/azalia_codec.c
1096
j < w->nconnections && k < 32; j++) {
sys/dev/pci/azalia_codec.c
1103
d->un.s.member[k].mask = 1 << j;
sys/dev/pci/azalia_codec.c
1104
strlcpy(d->un.s.member[k].label.name,
sys/dev/pci/azalia_codec.c
1107
k++;
sys/dev/pci/azalia_codec.c
1109
d->un.s.num_mem = k;
sys/dev/pci/azalia_codec.c
1110
if (k != 0)
sys/dev/pci/azalia_codec.c
1127
k = 0;
sys/dev/pci/azalia_codec.c
1128
d->un.e.member[k].ord = 0;
sys/dev/pci/azalia_codec.c
1129
strlcpy(d->un.e.member[k].label.name, "none",
sys/dev/pci/azalia_codec.c
1131
k++;
sys/dev/pci/azalia_codec.c
1134
d->un.e.member[k].ord = 1;
sys/dev/pci/azalia_codec.c
1135
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1137
k++;
sys/dev/pci/azalia_codec.c
1141
d->un.e.member[k].ord = 2;
sys/dev/pci/azalia_codec.c
1142
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1144
k++;
sys/dev/pci/azalia_codec.c
1149
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1154
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1159
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1164
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
1170
d->un.e.member[k].ord = j + 3;
sys/dev/pci/azalia_codec.c
1171
k++;
sys/dev/pci/azalia_codec.c
1175
d->un.e.num_mem = k;
sys/dev/pci/azalia_codec.c
622
int i, j, k;
sys/dev/pci/azalia_codec.c
646
for (k = 0; k < nconvs; k++) {
sys/dev/pci/azalia_codec.c
647
if (convs[k] == conv)
sys/dev/pci/azalia_codec.c
650
if (k < nconvs)
sys/dev/pci/azalia_codec.c
653
k = azalia_codec_fnode(this, conv,
sys/dev/pci/azalia_codec.c
655
if (k < 0)
sys/dev/pci/azalia_codec.c
660
k = azalia_codec_fnode(this, pins[i].nid,
sys/dev/pci/azalia_codec.c
662
if (k < 0)
sys/dev/pci/azalia_codec.c
848
int err, i, j, k, bits;
sys/dev/pci/azalia_codec.c
926
for (j = 0, k = 0; j < w->nconnections && k < 32; j++) {
sys/dev/pci/azalia_codec.c
930
d->un.e.member[k].ord = j;
sys/dev/pci/azalia_codec.c
931
strlcpy(d->un.e.member[k].label.name,
sys/dev/pci/azalia_codec.c
934
k++;
sys/dev/pci/azalia_codec.c
936
d->un.e.num_mem = k;
sys/dev/pci/cz.c
839
int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK;
sys/dev/pci/cz.c
843
k = j;
sys/dev/pci/cz.c
857
return (&cz->cz_ports[u - k]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
323
int i, j, k, path_size, device_support;
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
393
for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
394
u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
398
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
421
for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
422
u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
426
le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c
434
le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1354
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1466
for (k = 0; k < num_base_address; k++) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1481
ip->base_address[k] =
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1482
lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1484
ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c
1485
DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
127
unsigned int i, j, k;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
141
for (k = 0; k < src->num_types; ++k) {
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
142
r = src->funcs->set(adev, src, k,
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
570
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
584
for (k = 0; k < src->num_types; k++)
sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c
585
amdgpu_irq_update(adev, src, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
10119
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
10152
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4754
int i, j, k, r, ring_id = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4923
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4924
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4928
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4940
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4942
k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
4946
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5256
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5294
for (k = 0; k < max_wgp_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5295
if (!(wgp_active_bitmap & (1 << k))) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5296
gcrd_targets_disable_tcp |= 3 << (2 * k);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5297
gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5298
utcl_invreq_disable |= (3 << (2 * k)) |
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
5299
(3 << (2 * (max_wgp_per_sh + k)));
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9652
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9675
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9676
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9705
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9706
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9721
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9741
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9743
nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9772
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
9773
nv_grbm_select(adev, i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1580
int i, j, k, r, ring_id;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1784
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1785
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1789
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1803
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1805
k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
1809
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5005
int r, i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5020
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5021
soc21_grbm_select(adev, i, k, j, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5030
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
5031
soc21_grbm_select(adev, i, k, j, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7042
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7065
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7066
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7095
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7096
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7111
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7131
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7133
soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7164
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7165
soc21_grbm_select(adev, i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7496
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
7536
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1392
int i, j, k, r, ring_id = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1506
for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1507
if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1511
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1525
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1527
0, i, k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
1531
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5105
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5128
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5129
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5153
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5154
drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5169
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5189
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5191
soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5215
for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5216
soc24_grbm_select(adev, i, j, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5719
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v12_0.c
5759
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1548
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1560
for (k = 0; k < 16; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
1561
mask <<= k;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3611
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v6_0.c
3639
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3267
u32 i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3274
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
3288
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4313
int i, j, k, r, ring_id;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4382
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4384
k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
4389
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
5023
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v7_0.c
5051
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1888
int i, j, k, r, ring_id;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1989
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1991
k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
1996
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3807
u32 i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3814
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3819
if (k == adev->usec_timeout) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
3836
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7047
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c
7075
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1670
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
1688
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2214
int i, j, k, r, ring_id;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2391
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2393
k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2398
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2714
u32 i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2721
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2726
if (k == adev->usec_timeout) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
2743
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6987
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6996
for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
6997
amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7045
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7058
for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7059
amdgpu_gfx_select_se_sh(adev, j, 0, k, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7065
j, k, reg_value,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7249
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7272
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7273
drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7294
uint32_t i, j, k, reg, index = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7314
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7316
soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7757
int i, j, k, counter, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
7800
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
870
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
883
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
884
k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
885
gfx_v9_4_select_se_sh(adev, j, 0, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
891
j, k, reg_value, &sec_count,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
909
int i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
917
for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
918
k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4.c
919
gfx_v9_4_select_se_sh(adev, j, 0x0, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1504
uint32_t i, j, k, data;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1516
for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1517
k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1518
gfx_v9_4_2_select_se_sh(adev, j, 0, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_2.c
1535
j, k, data, &sec_cnt, &ded_cnt);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1040
int i, j, k, r, ring_id, xcc_id, num_xcc;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1111
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1112
k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1114
adev, xcc_id, i, k, j))
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1120
i, k, j);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1466
u32 i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1474
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1479
if (k == adev->usec_timeout) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
1498
for (k = 0; k < adev->usec_timeout; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3149
int i, j, k, num_xcc;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3160
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3162
mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3189
int i, j, k, num_xcc;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3200
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
3202
mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4390
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4402
for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4406
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4432
for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4436
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4464
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4470
for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4474
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4492
for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4496
gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4578
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4616
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4619
xcc_id, i, j, k);
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4647
uint32_t i, j, k;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4678
for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4680
soc15_grbm_select(adev, 1 + i, j, k, 0,
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4907
int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;
sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c
4943
for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1007
WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1020
WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1021
WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1023
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1024
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1025
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1026
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1027
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1028
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1031
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1036
WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1040
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1044
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1051
status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1060
DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1061
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1065
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1072
DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1076
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1081
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1092
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1095
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1098
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1102
WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1104
WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1108
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1110
ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1111
WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1114
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1117
ring = &adev->uvd.inst[k].ring_enc[0];
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1118
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1119
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1120
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1121
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1122
WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1124
ring = &adev->uvd.inst[k].ring_enc[1];
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1125
WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1126
WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1127
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1128
WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
1129
WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
960
int i, j, k, r;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
962
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
963
if (adev->uvd.harvest_config & (1 << k))
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
966
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
976
for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
977
if (adev->uvd.harvest_config & (1 << k))
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
979
ring = &adev->uvd.inst[k].ring;
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
981
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
985
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
989
WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
sys/dev/pci/drm/amd/amdgpu/uvd_v7_0.c
995
WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1170
int j, k, r;
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1257
for (k = 0; k < 10; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1200
int j, k, r;
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1289
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1143
int j, k, r;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1234
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1192
int j, k, r, vcn_inst;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
1278
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1055
int j, k, r;
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
1146
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
812
int j, k, r;
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
874
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
1040
for (k = 0; k < 100; ++k) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
985
int j, k, r, vcn_inst;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1570
uint32_t k;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1573
k = 0;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1575
k++;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1576
if (k < 2)
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1583
k--;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1586
ret = kfd_create_indirect_link_prop(new_dev, k);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1603
ret = kfd_add_peer_prop(new_dev, dev, i, k);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1607
ret = kfd_add_peer_prop(dev, new_dev, k, i);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1691
int i, j, k, xcc, start, end;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1759
k = 0;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1764
pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1765
pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1766
pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1767
pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1768
k += 4;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1775
pcache->sibling_map_size = k;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1790
int i, j, k, xcc, start, end;
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1832
for (k = 0; k < gfx_info->max_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1836
cu_processor_id, k);
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1847
num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
sys/dev/pci/drm/amd/amdkfd/kfd_topology.c
1850
(gfx_info->max_cu_per_sh - k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3357
int k, m;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3366
for (k = 0; k < dc_state->stream_count; k++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3367
bundle->stream_update.stream = dc_state->streams[k];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3369
for (m = 0; m < dc_state->stream_status[k].plane_count; m++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3371
dc_state->stream_status[k].plane_states[m];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3378
dc_state->stream_status[k].plane_count,
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3379
dc_state->streams[k],
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
136
uint8_t i, j, k;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
165
for (k = 0; k < mstb_lct - 1; k++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
166
int shift = (k % 2) ? 0 : 4;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
167
int port_num = (rad[k / 2] >> shift) & 0xf;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
168
int next_port_num = (next_rad[k / 2] >> shift) & 0xf;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1009
if (vars[i + k].dsc_enabled) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1011
kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1038
link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div));
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1098
int k)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1111
if (vars[i + k].dsc_enabled
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1112
&& vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1177
static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1183
i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1198
int i, k, ret;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1273
k = *link_vars_start_index;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1280
vars[i + k].aconnector = params[i].aconnector;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1281
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1282
vars[i + k].dsc_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1283
vars[i + k].bpp_x16 = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1285
vars[i + k].pbn);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1291
set_dsc_configs_from_fairness_vars(params, vars, count, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1297
log_dsc_params(count, vars, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1303
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1304
vars[i + k].dsc_enabled = true;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1305
vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1307
params[i].port, vars[i + k].pbn);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1311
vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1312
vars[i + k].dsc_enabled = false;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1313
vars[i + k].bpp_x16 = 0;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1315
params[i].port, vars[i + k].pbn);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1324
log_dsc_params(count, vars, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1328
ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1334
log_dsc_params(count, vars, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1337
ret = try_disable_dsc(state, dc_link, params, vars, count, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1343
log_dsc_params(count, vars, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1345
set_dsc_configs_from_fairness_vars(params, vars, count, k);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
912
int k)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
925
if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
938
params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
948
params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
962
vars[i + k].pbn);
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
995
int k)
sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h
186
int i, j, k;
sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h
538
for (k = 0; k < 8; k++) {
sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h
541
i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k]));
sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h
543
i, j, k,
sys/dev/pci/drm/amd/display/dc/basics/calcs_logger.h
544
bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1205
for (k = 0; k <= 7; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1211
data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1258
data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1261
data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1267
data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1288
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1289
if (data->enable[k]) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1292
data->display_pstate_change_enable[k] = 0;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1328
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1329
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1330
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1331
data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1332
data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1336
else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1337
data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1341
data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1342
data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1346
else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1347
data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1389
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1390
if (data->enable[k]) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1391
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1392
data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1397
data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1399
data->display_pstate_change_enable[k] = 1;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1406
data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1411
data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1413
data->display_pstate_change_enable[k] = 1;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1424
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1425
if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1433
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1434
if (data->enable[k]) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1435
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1436
data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1437
data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1440
data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1441
data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1798
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1799
if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1800
if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1802
if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1803
data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1808
if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
1809
data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2012
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2013
data->output_bpphdmi[k] = bw_def_na;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2014
data->output_bppdp4_lane_hbr[k] = bw_def_na;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2015
data->output_bppdp4_lane_hbr2[k] = bw_def_na;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2016
data->output_bppdp4_lane_hbr3[k] = bw_def_na;
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2017
if (data->enable[k]) {
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2018
data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2020
data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2023
data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
2026
data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
98
int32_t i, j, k;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
133
int k;
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
140
for (k = 0; k < MAX_PIPES; k++)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
141
if (stream == context->res_ctx.pipe_ctx[k].stream) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
142
pipe_ctx = &context->res_ctx.pipe_ctx[k];
sys/dev/pci/drm/amd/display/dc/core/dc.c
1615
int i, j, k;
sys/dev/pci/drm/amd/display/dc/core/dc.c
1688
for (k = 0; k < group_size; k++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
1689
struct dc_stream_status *status = dc_state_get_stream_status(ctx, pipe_set[k]->stream);
sys/dev/pci/drm/amd/display/dc/core/dc.c
1696
if (k == 0)
sys/dev/pci/drm/amd/display/dc/core/dc.c
2115
int i, k, l;
sys/dev/pci/drm/amd/display/dc/core/dc.c
2255
for (k = 0; k < MAX_PIPES; k++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
2256
pipe = &context->res_ctx.pipe_ctx[k];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4089
int i, j, k;
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4178
for (k = 0; k < del_streams[i]->num_wb_info; k++)
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4179
add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
442
int i = 0, k = 0;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
477
for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
488
config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
489
config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
490
config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
491
config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
492
dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
493
k++;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
503
int k;
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
510
for (k = 0; k < MAX_PIPES; k++)
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
511
if (stream == context->res_ctx.pipe_ctx[k].stream) {
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
512
pipe_ctx = &context->res_ctx.pipe_ctx[k];
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
346
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
386
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
387
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
388
hw_points += (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
392
for (k = 0; k < (region_end - region_start); k++) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
393
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
394
start_index = (region_start + k + MAX_LOW_POINT) *
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
474
k = 0;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
476
if (seg_distr[k] != -1) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
477
lut_params->arr_curve_points[k].segments_num =
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
478
seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
480
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
482
k++;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
485
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
486
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
551
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
575
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
576
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
577
hw_points += (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
581
for (k = 0; k < (region_end - region_start); k++) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
582
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
583
start_index = (region_start + k + MAX_LOW_POINT) *
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
651
k = 0;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
653
if (seg_distr[k] != -1) {
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
654
lut_params->arr_curve_points[k].segments_num =
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
655
seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
657
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
659
k++;
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
662
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_cm_common.c
663
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
123
uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
164
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
165
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
166
hw_points += (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
175
for (k = 0; k < (region_end - region_start); k++) {
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
176
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
177
start_index = (region_start + k + MAX_LOW_POINT) *
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
236
k = 0;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
238
if (seg_distr[k] != -1) {
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
239
lut_params->arr_curve_points[k].segments_num =
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
240
seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
242
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
244
k++;
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
247
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_cm_common.c
248
lut_params->arr_curve_points[k].segments_num = seg_distr[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1010
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1011
v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
102
v->vtaps[k] = v->acceptable_quality_vta_ps;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1020
int k;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1025
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1026
v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1037
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1038
v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
104
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1040
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1041
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1045
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1049
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
105
v->vta_pschroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1053
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
106
v->hta_pschroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1061
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1062
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1065
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1076
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1080
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1091
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1099
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
110
v->vta_pschroma[k] = v->override_vta_pschroma[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1100
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1109
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
111
v->hta_pschroma[k] = v->override_hta_pschroma[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1113
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1122
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1136
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1137
v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
114
v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1140
v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1144
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
115
v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1150
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1155
v->swath_height_y[k] = v->maximum_swath_height_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1156
v->swath_height_c[k] = v->maximum_swath_height_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1159
v->swath_height_y[k] = v->minimum_swath_height_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1160
v->swath_height_c[k] = v->minimum_swath_height_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1162
if (v->swath_height_c[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1163
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1164
v->det_buffer_size_c[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1166
else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1167
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1168
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1171
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1172
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1178
int k;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1183
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1184
if (v->h_ratio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1185
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1188
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1190
v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1191
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1192
v->pscl_throughput_chroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1196
if (v->h_ratio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1197
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1200
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1202
v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1206
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1207
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1210
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1211
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1228
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1229
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1249
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
125
int k;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1250
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1251
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1254
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1257
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1258
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1259
v->byte_per_pixel_dety[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1260
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1262
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1263
v->byte_per_pixel_dety[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1264
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1266
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1267
v->byte_per_pixel_dety[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1268
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1270
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1271
v->byte_per_pixel_dety[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1272
v->byte_per_pixel_detc[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1275
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1276
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1280
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1281
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1282
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1283
v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1287
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1288
v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1289
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1290
v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1295
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1296
if (v->v_ratio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1297
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1300
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1302
v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1303
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1304
if (v->byte_per_pixel_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1305
v->display_pipe_line_delivery_time_chroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1308
if (v->v_ratio[k] / 2.0 <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1309
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
131
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1312
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1314
v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1315
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
132
if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1328
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1329
if (v->output[k] == dcn_bw_writeback) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1341
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1342
v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1343
v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1344
v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1345
if (v->byte_per_pixel_detc[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1346
v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1347
v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1348
v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1351
v->lines_in_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1352
v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1353
v->full_det_buffering_time_c[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1357
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1358
if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1359
v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1360
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1362
if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1363
v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1364
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1368
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1369
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1370
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1373
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1375
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1376
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1379
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
139
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1391
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1393
v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
140
if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1403
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1404
if (v->byte_per_pixel_detc[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1405
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1408
v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1410
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1413
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1414
v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1422
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1423
v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1424
v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1425
if (v->byte_per_pixel_detc[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1426
v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1427
v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1428
v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1431
v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1435
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1436
v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1443
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1444
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1445
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1448
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1457
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
146
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1461
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
147
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1470
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1471
v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1472
v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1473
v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1475
v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
148
v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1480
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1481
v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1484
v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1492
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1496
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1500
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
151
v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1514
v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1515
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1516
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1518
else if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1519
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1522
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1528
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1529
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
153
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1530
v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1531
v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1532
v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1534
v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1539
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
154
v->byte_per_pixel_in_dety[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1540
v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1543
v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
155
v->byte_per_pixel_in_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1551
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1555
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1559
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
157
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1573
v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1574
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1575
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1577
else if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1578
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
158
v->byte_per_pixel_in_dety[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1581
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
159
v->byte_per_pixel_in_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1593
v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1594
v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1595
v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1596
v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1597
v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1598
if (v->v_init_pre_fill_y[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1599
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1602
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1605
v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1606
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1607
v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1608
v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1609
if (v->v_init_pre_fill_c[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
161
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1610
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1613
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1618
v->max_num_swath_c[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
162
v->byte_per_pixel_in_dety[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1621
v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1624
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1626
v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1629
v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
163
v->byte_per_pixel_in_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1642
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1643
v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1644
if (v->dpp_per_plane[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1645
v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1647
if (v->output_format[k] == dcn_bw_420) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
165
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1653
v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1655
v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1656
v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1657
v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1658
v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
166
v->byte_per_pixel_in_dety[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1668
v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1669
if (v->destination_lines_for_prefetch[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
167
v->byte_per_pixel_in_detc[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1670
v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1673
v->prefetch_bandwidth[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1677
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1678
v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1681
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1682
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1683
v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1687
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1688
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1689
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1690
v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1693
v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1697
v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1699
v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
170
v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1700
if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1701
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1702
v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1705
v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1709
v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
171
v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1711
v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1712
v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1714
v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1715
if ((v->swath_height_y[k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1716
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1717
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1720
v->v_ratio_prefetch_y[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1725
v->v_ratio_prefetch_y[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1727
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1729
v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1730
if ((v->swath_height_c[k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1731
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1732
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1735
v->v_ratio_prefetch_c[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1740
v->v_ratio_prefetch_c[k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1742
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1744
v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1749
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
175
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1750
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1751
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k]));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1753
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1756
if (v->destination_lines_for_prefetch[k] < 2.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1759
if (v->max_vstartup_lines[k] > v->v_startup_lines) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
176
v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1760
if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1763
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1766
if (v->destination_lines_for_prefetch[k] < 2.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
177
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
178
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1781
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1782
if (v->v_ratio_prefetch_y[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1783
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1786
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1788
if (v->byte_per_pixel_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1789
v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1792
if (v->v_ratio_prefetch_c[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1793
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1796
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
180
if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1802
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1804
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1805
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1806
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1809
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
181
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1810
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1811
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1814
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1815
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1816
v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1822
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1823
v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1825
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1826
v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1827
v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1828
v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1829
v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
183
else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1830
if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1831
v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1833
else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1839
if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
184
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1840
v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1842
else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1848
v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1849
v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1852
v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1854
if (v->byte_per_pixel_detc[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1855
v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1856
v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1859
v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1861
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1864
v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1866
if (v->output_format[k] == dcn_bw_444) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1867
v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
187
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1870
v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1872
if (v->output[k] == dcn_bw_writeback) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1873
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1876
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1877
if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1878
v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1881
v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1887
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1888
if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
189
v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1890
v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1891
v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1893
else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1894
v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1898
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1899
if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1900
v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
192
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1924
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1925
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1926
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1928
else if (v->output[k] == dcn_bw_writeback) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1929
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
193
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
194
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
196
else if (v->output[k] == dcn_bw_writeback) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
197
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
200
v->write_bandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
202
v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
206
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
207
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
241
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
242
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
245
else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
262
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
263
if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
264
if (v->output_format[k] == dcn_bw_420) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
265
v->required_output_bw = v->pixel_clock[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
268
v->required_output_bw = v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
271
else if (v->output_format[k] == dcn_bw_420) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
272
v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
275
v->required_output_bw = v->pixel_clock[k] * 3.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
277
if (v->output[k] == dcn_bw_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
278
v->required_phyclk[k] = v->required_output_bw;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
279
switch (v->output_deep_color[k]) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
281
v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
284
v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
289
v->required_phyclk[k] = v->required_phyclk[k] / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
291
else if (v->output[k] == dcn_bw_dp) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
292
v->required_phyclk[k] = v->required_output_bw / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
295
v->required_phyclk[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
300
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
301
if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
309
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
310
if (v->output[k] == dcn_bw_writeback) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
322
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
323
if (v->h_ratio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
324
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
327
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
329
if (v->byte_per_pixel_in_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
330
v->pscl_factor_chroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
331
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
334
if (v->h_ratio[k] / 2.0 > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
335
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
338
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
340
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
343
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
344
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
345
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
346
v->read256_block_height_y[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
348
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
349
v->read256_block_height_y[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
352
v->read256_block_height_y[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
354
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
355
v->read256_block_height_c[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
356
v->read256_block_width_c[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
359
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
360
v->read256_block_height_y[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
361
v->read256_block_height_c[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
363
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
364
v->read256_block_height_y[k] = 16.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
365
v->read256_block_height_c[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
368
v->read256_block_height_y[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
369
v->read256_block_height_c[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
371
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
372
v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
374
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
375
v->max_swath_height_y[k] = v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
376
v->max_swath_height_c[k] = v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
379
v->max_swath_height_y[k] = v->read256_block_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
380
v->max_swath_height_c[k] = v->read256_block_width_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
382
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
383
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
384
v->min_swath_height_y[k] = v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
387
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
389
v->min_swath_height_c[k] = v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
392
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
393
v->min_swath_height_y[k] = v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
394
v->min_swath_height_c[k] = v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
396
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
397
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
399
v->min_swath_height_c[k] = v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
402
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
405
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
406
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
408
v->min_swath_height_y[k] = v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
411
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
415
v->min_swath_height_y[k] = v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
416
v->min_swath_height_c[k] = v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
419
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
42
int k;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
425
v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
426
if (v->byte_per_pixel_in_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
427
v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
43
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
430
v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
432
v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
439
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
440
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
442
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
445
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
45
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
451
if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
452
v->no_of_dpp[i][j][k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
456
v->no_of_dpp[i][j][k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
46
v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
460
v->no_of_dpp[i][j][k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
464
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
47
v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
470
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
471
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
472
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
477
if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
478
v->no_of_dpp[i][j][k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
485
v->no_of_dpp[i][j][k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
491
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
499
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
50
v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
500
if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
51
v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
518
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
521
v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
522
v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
523
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
524
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
527
if (v->max_swath_height_c[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
528
v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
529
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
530
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
535
v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
536
v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
539
v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
540
v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
542
if (v->byte_per_pixel_in_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
543
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
546
else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
547
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
548
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
55
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
551
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
552
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
554
v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
555
v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
556
if (v->byte_per_pixel_in_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
557
v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
56
v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
560
v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 / dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
561
v->effective_detlb_lines_chroma = dcn_bw_floor2(v->lines_in_det_chroma + dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
562
v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
570
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
571
if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
582
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
583
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
584
v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
59
v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
592
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
593
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
594
if (v->byte_per_pixel_in_detc[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
595
if (v->v_ratio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
596
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
599
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
603
if (v->v_ratio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
604
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
607
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
609
if (v->v_ratio[k] / 2.0 <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
61
v->v_ratio[k] = v->h_ratio[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
610
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
613
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
617
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
618
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
619
v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
620
v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
621
v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
622
v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
624
v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
629
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
63
if (v->interlace_output[k] == 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
630
v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
633
v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
64
v->v_ratio[k] = 2.0 * v->v_ratio[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
641
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
645
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
647
v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
649
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
651
v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
655
v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
66
if (v->underscan_output[k] == 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
661
v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
663
v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
664
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
665
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
667
else if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
668
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
67
v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
671
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
677
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
678
if (v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
679
v->meta_req_height_c = 8.0 * v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
68
v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
680
v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
681
v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
682
v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
684
v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
689
if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
690
v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
693
v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
701
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
705
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
707
v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
709
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
711
v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
715
v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
717
v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
722
v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
724
v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
725
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
726
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
728
else if (v->source_scan[k] == dcn_bw_hor) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
729
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
73
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
732
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
74
if (v->h_ratio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
744
v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
745
v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
746
v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
747
v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
748
v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
749
v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
75
v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
750
if (v->prefill_y[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
751
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
754
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
757
v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
758
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
759
v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
760
v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
761
v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
762
if (v->prefill_c[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
763
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
766
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
769
v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
77
else if (v->h_ratio[k] < 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
772
v->prefetch_lines_c[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
774
v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
775
if (v->no_of_dpp[i][j][k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
776
v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
778
if (v->output_format[k] == dcn_bw_420) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
785
v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
787
v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
788
v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
789
v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
795
v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
798
v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
802
v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
803
v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
804
v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
806
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
808
v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
810
v->htotal[k] / v->pixel_clock[k] / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
812
v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
815
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
817
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
818
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
822
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
826
v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
827
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
830
if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
836
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
837
v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
839
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
84
v->htaps[k] = v->override_hta_ps[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
840
v->total_immediate_flip_bytes[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
841
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
842
v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
845
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
846
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
847
v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
850
v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
852
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
853
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
856
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
858
v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
859
v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
860
v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
861
v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
863
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
864
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
865
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
866
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
869
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
87
v->htaps[k] = v->acceptable_quality_hta_ps;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
872
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
873
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
874
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
875
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
878
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
881
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
884
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
885
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
886
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
889
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
89
if (v->v_ratio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
890
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
891
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
892
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
895
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
898
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
899
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
90
v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
900
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
901
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
904
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
907
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
910
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
911
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
912
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
916
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
917
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
918
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]));
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
92
else if (v->v_ratio[k] < 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
921
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
925
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
926
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
932
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
933
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
941
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
942
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
951
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
952
if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
957
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
958
if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
99
v->vtaps[k] = v->override_vta_ps[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1085
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1086
if (v->source_scan[k] == dcn_bw_hor)
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1087
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1089
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1091
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1092
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1093
v->byte_per_pixel_dety[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1094
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1095
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1096
v->byte_per_pixel_dety[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1097
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1098
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1099
v->byte_per_pixel_dety[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1100
v->byte_per_pixel_detc[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1101
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1102
v->byte_per_pixel_dety[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1103
v->byte_per_pixel_detc[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1105
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1106
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1111
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1112
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1113
dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1114
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1115
dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1117
v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
761
int i, input_idx, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1034
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1038
for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1039
wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
1040
wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2406
unsigned int i, closest_clk_lvl = 0, k = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2430
k++;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2432
s[k].state = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2433
s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2434
s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2435
s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2436
s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2438
s[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2439
s[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2440
s[k].dram_bw_per_chan_gbps =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2442
s[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2443
s[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2444
s[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2445
s[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2447
k++;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1085
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1094
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1095
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1100
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1101
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1102
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1103
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1104
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1105
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1106
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1107
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1108
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1109
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1114
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1115
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1116
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1119
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1121
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1125
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1131
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1133
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1136
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1138
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1139
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1140
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1143
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1145
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1146
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1149
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1150
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1151
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1152
mode_lib->vba.DPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1155
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1156
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1160
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1163
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1167
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1172
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1174
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1178
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1181
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1182
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1184
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1187
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1189
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1191
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1194
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1200
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1201
if (mode_lib->vba.BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1203
if (mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1207
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1217
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1221
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1225
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1235
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1272
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1273
if (mode_lib->vba.DPPPerPlane[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1274
mode_lib->vba.DPPCLK_calculated[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1276
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1277
/ mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1282
mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1287
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1288
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1290
mode_lib->vba.DPPCLK_calculated[k] * 255
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1293
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1298
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1299
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1328
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1331
if (mode_lib->vba.SourceScan[k] == dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1332
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1334
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1336
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1339
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1340
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1344
mode_lib->vba.SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1345
(double) mode_lib->vba.SwathWidthSingleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1347
mode_lib->vba.HActive[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1348
* mode_lib->vba.HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1350
if (mode_lib->vba.DPPPerPlane[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1351
mode_lib->vba.SwathWidthY[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1353
mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1354
/ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1359
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1360
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1361
mode_lib->vba.BytePerPixelDETY[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1362
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1363
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1364
mode_lib->vba.BytePerPixelDETY[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1365
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1366
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1367
mode_lib->vba.BytePerPixelDETY[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1368
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1369
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1370
mode_lib->vba.BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1371
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1372
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1373
mode_lib->vba.BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1374
mode_lib->vba.BytePerPixelDETC[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1376
mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1377
mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1382
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1383
mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1384
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1385
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1386
* mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1387
mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1388
/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1389
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1390
* mode_lib->vba.VRatio[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1393
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1394
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1395
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1396
mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1397
+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1402
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1404
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1405
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1407
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1417
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1420
if (mode_lib->vba.VRatio[k] <= 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1421
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1422
(double) mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1423
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1424
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1425
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1427
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1428
(double) mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1429
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1430
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1432
DataFabricLineDeliveryTimeLuma = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1433
* mode_lib->vba.SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1434
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1435
/ (mode_lib->vba.ReturnBW * mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1440
- mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1442
if (mode_lib->vba.BytePerPixelDETC[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1443
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1444
else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1445
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1446
mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1447
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1448
/ (mode_lib->vba.HRatio[k] / 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1449
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1451
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1452
mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1453
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1454
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1456
DataFabricLineDeliveryTimeChroma = mode_lib->vba.SwathWidthSingleDPPY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1457
* mode_lib->vba.SwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1458
* dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1460
* mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1466
- mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1489
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1490
if (mode_lib->vba.WritebackEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1491
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1527
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1528
mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1529
/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1530
mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1531
mode_lib->vba.LinesInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1532
mode_lib->vba.SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1533
mode_lib->vba.FullDETBufferingTimeY[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1534
mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1535
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1536
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1537
/ mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1538
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1539
mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1540
/ mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1541
/ (mode_lib->vba.SwathWidthY[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1542
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1543
mode_lib->vba.LinesInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1544
mode_lib->vba.SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1545
mode_lib->vba.FullDETBufferingTimeC[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1546
mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1547
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1548
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1549
/ (mode_lib->vba.VRatio[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1551
mode_lib->vba.LinesInDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1552
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1553
mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1558
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1559
if (mode_lib->vba.FullDETBufferingTimeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1562
mode_lib->vba.FullDETBufferingTimeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1564
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1565
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1567
if (mode_lib->vba.FullDETBufferingTimeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1570
mode_lib->vba.FullDETBufferingTimeC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1572
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1573
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1578
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1579
if (mode_lib->vba.DCCEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1582
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1583
/ mode_lib->vba.DCCRate[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1585
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1586
/ mode_lib->vba.DCCRate[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1591
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1593
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1596
if (mode_lib->vba.DCCEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1599
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1601
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1607
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1609
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1638
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1640
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1641
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1642
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1660
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1661
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1662
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1664
1.1 * mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1666
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1668
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1669
1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1671
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1673
/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1675
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1676
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1677
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1678
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1679
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1680
mode_lib->vba.PixelClock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1683
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1687
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1688
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1705
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1708
mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1710
mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1711
* mode_lib->vba.DPPCLK[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1712
* mode_lib->vba.BytePerPixelDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1713
* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1715
/ mode_lib->vba.DPPPerPlane[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1717
mode_lib->vba.SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1720
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1721
/ mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1723
* mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1724
* mode_lib->vba.BytePerPixelDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1726
/ mode_lib->vba.DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1728
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1731
mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1733
mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1734
* mode_lib->vba.DPPCLK[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1735
* mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1736
* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1738
/ mode_lib->vba.DPPPerPlane[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1740
mode_lib->vba.SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1743
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1744
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1745
/ (mode_lib->vba.VRatio[k] / 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1747
* (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1749
* mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1751
/ mode_lib->vba.DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1752
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1756
mode_lib->vba.UrgentLatencySupportUs[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1762
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1765
mode_lib->vba.UrgentLatencySupportUs[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1773
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1774
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1775
mode_lib->vba.DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1777
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1778
|| mode_lib->vba.OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1782
if (mode_lib->vba.ODMCombineEnabled[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1783
mode_lib->vba.DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1784
mode_lib->vba.PixelClockBackEnd[k] / 6
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1790
mode_lib->vba.DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1791
mode_lib->vba.PixelClockBackEnd[k] / 3
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1801
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1802
double bpp = mode_lib->vba.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1803
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1805
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1806
if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1807
mode_lib->vba.DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1809
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1812
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1813
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1816
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1818
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1820
mode_lib->vba.DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1823
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1826
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1827
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1830
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1832
mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1834
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1835
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1836
/ mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1838
mode_lib->vba.DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1842
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1844
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1846
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1849
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1858
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1859
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1860
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1861
dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1862
&mode_lib->vba.BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1863
&mode_lib->vba.BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1864
&mode_lib->vba.BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1865
&mode_lib->vba.BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1868
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1869
mode_lib->vba.BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1870
mode_lib->vba.BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1871
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1872
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1873
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1874
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1875
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1876
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1877
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1882
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1883
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1884
&mode_lib->vba.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1888
&mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1889
&mode_lib->vba.meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1890
mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1892
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1893
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1894
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1896
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1897
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1898
&mode_lib->vba.VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1899
&mode_lib->vba.MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1901
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1902
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1903
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1904
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1908
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1909
mode_lib->vba.BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1910
mode_lib->vba.BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1911
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1912
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1914
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1916
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1917
mode_lib->vba.ViewportWidth[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1918
mode_lib->vba.ViewportHeight[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1919
mode_lib->vba.SwathWidthY[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1924
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1926
&mode_lib->vba.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1930
&mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1931
&mode_lib->vba.meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1932
mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1934
mode_lib->vba.VRatio[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1935
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1936
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1938
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1939
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1940
&mode_lib->vba.VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1941
&mode_lib->vba.MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1946
mode_lib->vba.MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1947
mode_lib->vba.PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1950
mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1951
mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1953
mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1957
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1958
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1959
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1960
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1963
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1964
mode_lib->vba.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1967
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1968
mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1969
&mode_lib->vba.meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1970
&mode_lib->vba.dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1971
&mode_lib->vba.qual_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1976
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1977
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1978
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1979
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1982
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1983
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1984
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1985
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1986
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1987
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1988
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1989
mode_lib->vba.WritebackDestinationWidth[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1992
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1994
if (mode_lib->vba.BlendingAndTiming[j] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1996
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
1998
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2015
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2017
if (mode_lib->vba.BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2018
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2022
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2023
mode_lib->vba.MaxVStartupLines[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2024
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2028
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2029
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2030
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2034
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2037
mode_lib->vba.MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2039
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2040
mode_lib->vba.cursor_bw[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2041
for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2042
mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2043
* mode_lib->vba.CursorBPP[k][j] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2044
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2045
* mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2060
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2061
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2065
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2066
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2068
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2070
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2071
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2087
mode_lib->vba.ErrorResult[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2090
mode_lib->vba.DPPCLK[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2092
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2094
mode_lib->vba.DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2095
mode_lib->vba.DPPPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2096
mode_lib->vba.ScalerEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2097
mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2104
(unsigned int) (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2105
/ mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2106
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2107
mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2108
- mode_lib->vba.VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2109
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2113
mode_lib->vba.MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2116
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2117
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2118
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2119
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2123
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2124
mode_lib->vba.MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2125
mode_lib->vba.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2126
mode_lib->vba.PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2127
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2128
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2129
mode_lib->vba.VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2130
mode_lib->vba.MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2131
mode_lib->vba.PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2132
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2133
mode_lib->vba.VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2134
mode_lib->vba.MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2135
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2136
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2138
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2140
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2142
&mode_lib->vba.DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2143
&mode_lib->vba.DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2144
&mode_lib->vba.DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2145
&mode_lib->vba.PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2146
&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2147
&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2148
&mode_lib->vba.VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2149
&mode_lib->vba.VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2150
&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2152
&mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2153
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2154
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2155
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2156
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2157
mode_lib->vba.VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2159
mode_lib->vba.MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2162
mode_lib->vba.VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2166
mode_lib->vba.VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2169
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2173
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2175
if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2176
mode_lib->vba.prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2177
else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2178
mode_lib->vba.prefetch_vm_bw[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2179
(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2180
/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2181
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2182
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2184
mode_lib->vba.prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2187
if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2189
mode_lib->vba.prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2190
else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2191
mode_lib->vba.prefetch_row_bw[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2192
(double) (mode_lib->vba.MetaRowByte[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2193
+ mode_lib->vba.PixelPTEBytesPerRow[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2194
/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2195
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2196
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2198
mode_lib->vba.prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2203
MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2205
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2207
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2209
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2210
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2211
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2212
+ mode_lib->vba.meta_row_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2213
+ mode_lib->vba.dpte_row_bw[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2215
if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2217
if (mode_lib->vba.VRatioPrefetchY[k] > 4
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2218
|| mode_lib->vba.VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2238
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2241
- mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2243
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2244
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2245
+ mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2246
mode_lib->vba.PrefetchBandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2249
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2250
ImmediateFlipBytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2251
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2252
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2253
ImmediateFlipBytes[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2254
mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2255
+ mode_lib->vba.MetaRowByte[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2256
+ mode_lib->vba.PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2260
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2261
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2262
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2265
+ ImmediateFlipBytes[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2268
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2277
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2278
ImmediateFlipBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2279
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2280
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2281
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2282
mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2283
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2284
mode_lib->vba.MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2285
mode_lib->vba.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2286
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2287
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2288
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2289
mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2290
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2291
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2292
&final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2293
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2295
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2298
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2300
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2302
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2303
final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2305
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2306
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2307
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2313
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2314
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2322
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2323
if (mode_lib->vba.ErrorResult[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2337
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2338
if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2339
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2340
mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2341
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2342
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2344
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2345
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2346
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2347
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2349
if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2350
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2352
if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2353
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2354
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2355
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2356
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2357
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2359
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2360
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2361
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2362
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2368
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2370
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2371
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2372
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2378
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2379
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2380
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2384
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2385
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2386
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2388
if (!mode_lib->vba.DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2389
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2390
+ mode_lib->vba.MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2396
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2397
mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2400
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2414
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2415
/ (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2417
mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2419
1)) - (mode_lib->vba.vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2426
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2427
/ (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2430
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2434
- (mode_lib->vba.VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2437
/ mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2438
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2441
/ (mode_lib->vba.VRatio[k] / 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2442
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2444
if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2446
/ mode_lib->vba.SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2447
} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2453
if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2455
/ (mode_lib->vba.SwathWidthY[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2456
} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2462
DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2464
MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2465
+ (mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2466
- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2467
/ mode_lib->vba.SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2468
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2469
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2478
* mode_lib->vba.SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2479
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2480
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2483
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2484
double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2485
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2489
mode_lib->vba.FullDETBufferingTimeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2490
+ (mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2491
- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2492
/ mode_lib->vba.SwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2493
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2494
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2506
* mode_lib->vba.SwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2507
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2508
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2510
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2514
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2518
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2521
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2525
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2526
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2527
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2528
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2529
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2532
} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2540
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2541
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2542
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2543
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2544
/ mode_lib->vba.PixelClock[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2552
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2553
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2554
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2555
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2556
/ mode_lib->vba.PixelClock[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2559
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2560
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2566
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2567
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2570
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2585
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2586
if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2595
for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2597
mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2600
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2601
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2604
mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2605
mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2606
mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2614
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2615
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2616
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2617
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2630
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2633
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2634
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2636
mode_lib->vba.XFCTransferDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2639
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2640
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2642
mode_lib->vba.XFCPrechargeDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2647
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2648
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2653
(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2654
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2655
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2656
/ mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2668
mode_lib->vba.XFCPrefetchMargin[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2671
+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2672
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2673
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2674
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2676
mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2677
mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2678
mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2679
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2680
mode_lib->vba.XFCPrechargeDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2681
mode_lib->vba.XFCTransferDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2682
mode_lib->vba.XFCPrefetchMargin[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2689
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2690
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2691
unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2692
* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2702
if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2704
mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2728
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2730
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2733
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2736
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2739
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2742
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2745
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2753
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2754
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2755
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2756
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2757
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2759
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2761
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2762
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2772
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2775
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2788
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2796
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2797
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2798
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2799
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2800
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2801
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2802
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2804
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2806
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2808
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2810
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2812
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2814
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2816
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2818
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2819
&& mode_lib->vba.SourceScan[k] != dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2826
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2829
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2830
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2833
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2834
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2843
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2844
SwathWidth = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2846
SwathWidth = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2849
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2853
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2854
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2862
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2864
if (mode_lib->vba.DPPPerPlane[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2867
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2875
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2886
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2896
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2897
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2899
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2900
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2903
if (mode_lib->vba.SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2904
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2905
mode_lib->vba.DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2906
} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2907
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2909
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2912
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
2914
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3288
unsigned int j, k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3295
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3296
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3297
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3298
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3299
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3300
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3301
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3302
|| mode_lib->vba.HRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3303
|| mode_lib->vba.htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3304
|| mode_lib->vba.VRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3305
|| mode_lib->vba.vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3307
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3308
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3309
|| (mode_lib->vba.htaps[k] > 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3310
&& (mode_lib->vba.htaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3311
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3312
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3313
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3314
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3315
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3316
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3317
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3318
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3319
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3320
&& (mode_lib->vba.HRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3321
> mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3322
|| mode_lib->vba.VRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3323
> mode_lib->vba.VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3330
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3331
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3332
&& mode_lib->vba.SourceScan[k] != dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3333
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3334
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3335
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3336
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3337
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3338
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3339
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3340
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3341
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3342
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3343
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3345
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3347
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3348
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3350
&& !((mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3352
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3354
&& mode_lib->vba.SourceScan[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3358
&& mode_lib->vba.DCCEnable[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3360
|| (mode_lib->vba.DCCEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3361
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3363
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3365
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3372
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3373
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3374
locals->BytePerPixelInDETY[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3375
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3376
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3377
locals->BytePerPixelInDETY[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3378
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3379
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3380
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3381
locals->BytePerPixelInDETY[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3382
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3383
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3384
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3385
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3386
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3387
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3388
locals->BytePerPixelInDETC[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3390
locals->BytePerPixelInDETY[k] = 4.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3391
locals->BytePerPixelInDETC[k] = 8.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3393
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3394
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3396
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3399
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3400
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3401
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3402
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3403
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3404
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3406
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3407
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3408
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3409
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3410
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3411
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3412
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3413
/ mode_lib->vba.PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3414
} else if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3415
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3416
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3417
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3418
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3419
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3420
/ mode_lib->vba.PixelClock[k]) * 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3421
} else if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3422
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3423
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3424
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3425
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3426
/ mode_lib->vba.PixelClock[k]) * 1.5;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3428
locals->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3432
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3433
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3496
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3497
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3498
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3499
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3506
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3534
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3535
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3536
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3537
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3540
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3547
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3548
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3550
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3557
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3558
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3560
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3561
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3564
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3565
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3567
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3569
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3571
|| mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3573
|| mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3575
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3576
> mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3577
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3578
> mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3579
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3580
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3582
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3583
&& (mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3585
|| mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3588
* mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3589
> mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3591
* mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3592
> mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3593
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3594
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3597
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3599
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3603
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3604
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3608
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3610
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3611
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3613
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3615
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3616
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3619
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3623
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3628
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3629
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3631
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3633
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3634
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3637
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3646
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3647
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3652
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3653
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3654
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3655
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3656
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3657
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3658
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3659
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3660
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3661
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3665
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3666
if (mode_lib->vba.HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3667
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3670
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3672
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3676
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3680
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3681
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3682
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3683
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3685
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3688
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3689
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3690
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3691
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3693
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3694
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3695
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3696
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3697
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3700
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3701
locals->PSCL_FACTOR_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3705
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3708
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3712
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3716
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3717
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3719
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3722
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3723
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3724
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3725
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3726
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3730
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3732
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3733
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3735
/ locals->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3737
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3738
|| mode_lib->vba.HTAPsChroma[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3739
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3740
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3741
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3742
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3743
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3747
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3749
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3750
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3751
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3752
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3753
&locals->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3754
&locals->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3755
&locals->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3756
&locals->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3757
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3758
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3759
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3761
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3762
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3764
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3765
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3766
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3767
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3768
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3769
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3770
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3771
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3773
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3775
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3777
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3779
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3781
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3783
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3785
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3786
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3788
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3791
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3793
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3794
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3795
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3796
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3797
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3798
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3800
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3801
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3802
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3803
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3805
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3807
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3808
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3811
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3820
/ (locals->BytePerPixelInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3821
* locals->MinSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3822
+ locals->BytePerPixelInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3824
* locals->MinSwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3825
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3828
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3829
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3830
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3833
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3842
mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3844
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3845
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3848
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3854
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3857
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3858
/ (mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3861
mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3867
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3881
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3883
mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3887
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3890
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3894
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3897
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3901
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3903
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3904
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3909
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3910
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3911
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3912
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3913
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3914
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3916
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3917
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3918
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3923
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3930
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3931
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3940
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3941
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3942
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3943
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3956
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3957
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3958
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3959
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3960
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3963
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3964
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3969
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3973
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3979
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3985
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
3986
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4001
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4002
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4003
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4004
> locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4008
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4027
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4028
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4041
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4042
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4043
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4044
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4049
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4050
locals->RequiresDSC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4051
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4052
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4053
if (mode_lib->vba.Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4054
locals->RequiresDSC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4055
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4056
locals->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4057
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4059
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4060
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4061
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4062
} else if (mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4063
|| mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4064
if (mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4073
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4075
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4076
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4077
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4080
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4082
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4083
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4084
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4085
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4086
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4087
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4088
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4090
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4094
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4095
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4097
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4102
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4104
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4105
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4106
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4109
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4111
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4112
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4113
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4114
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4115
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4116
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4117
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4119
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4123
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4124
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4126
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4133
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4135
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4136
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4137
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4140
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4142
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4143
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4144
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4145
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4146
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4147
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4148
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4150
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4154
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4155
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4157
locals->OutputBppPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4162
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4168
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4169
if (!mode_lib->vba.skip_dio_check[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4170
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4171
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4172
&& mode_lib->vba.Interlace[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4179
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4181
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4182
if ((mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4183
|| mode_lib->vba.Output[k] == dm_edp)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4184
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4185
|| mode_lib->vba.OutputFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4191
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4192
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4193
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4199
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4213
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4214
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4215
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4231
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4232
if (mode_lib->vba.BlendingAndTiming[k] != k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4234
} else if (locals->RequiresDSC[i][k] == 0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4235
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4237
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4239
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4241
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4243
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4245
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4250
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4251
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4254
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4256
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4257
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4258
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4260
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4263
mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4267
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4269
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4271
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4273
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4275
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4277
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4278
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4280
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4281
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4283
locals->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4286
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4289
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4290
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4299
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4300
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4301
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4303
locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4304
locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4305
locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4306
+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4307
if (locals->SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4310
if (locals->MaxSwathHeightC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4311
locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4313
locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4314
+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4316
if (locals->SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4323
locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4324
locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4326
locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4327
locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4330
if (locals->BytePerPixelInDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4331
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4333
} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4334
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4335
locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4336
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4338
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4339
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4343
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4344
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4347
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4348
/ (locals->SwathWidthYPerState[i][j][k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4349
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4352
locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4353
locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4355
locals->SwathHeightYPerState[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4359
locals->BytePerPixelInDETC[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4360
locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4362
locals->SwathHeightCPerState[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4367
if (locals->BytePerPixelInDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4368
locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4369
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4370
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4372
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4373
locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4374
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4375
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4376
locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4377
locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4378
dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4387
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4388
if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4399
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4400
if (locals->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4402
locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4412
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4413
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4414
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4415
locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4416
locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4417
locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4420
mode_lib->vba.PixelClock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4421
if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4422
if (mode_lib->vba.VRatio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4428
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4431
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4432
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4433
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4440
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4443
* mode_lib->vba.PSCL_FACTOR[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4444
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4447
if (mode_lib->vba.VRatio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4453
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4456
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4457
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4458
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4465
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4468
* mode_lib->vba.PSCL_FACTOR[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4469
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4471
if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4477
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4480
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4482
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4483
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4490
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4493
* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4494
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4498
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4501
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4502
mode_lib->vba.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4503
mode_lib->vba.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4504
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4505
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4506
dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4507
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4508
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4509
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4510
mode_lib->vba.SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4515
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4516
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4517
&mode_lib->vba.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4520
&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4521
&mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4522
&mode_lib->vba.meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4523
mode_lib->vba.PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4525
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4526
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4527
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4529
mode_lib->vba.SwathHeightYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4530
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4531
&mode_lib->vba.PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4532
&mode_lib->vba.MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4533
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4534
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4535
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4536
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4537
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4540
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4541
mode_lib->vba.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4542
mode_lib->vba.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4543
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4544
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4545
dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4546
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4547
mode_lib->vba.ViewportWidth[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4548
mode_lib->vba.ViewportHeight[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4549
mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4554
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4556
&mode_lib->vba.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4559
&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4560
&mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4561
&mode_lib->vba.meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4562
mode_lib->vba.PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4564
mode_lib->vba.VRatio[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4565
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4566
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4568
mode_lib->vba.SwathHeightCPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4569
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4570
&mode_lib->vba.PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4571
&mode_lib->vba.MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4576
locals->PrefetchLinesC[0][0][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4577
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4580
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4582
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4583
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4587
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4588
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4589
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4590
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4593
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4594
mode_lib->vba.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4597
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4598
mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4599
&mode_lib->vba.meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4600
&mode_lib->vba.dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4601
&mode_lib->vba.qual_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4619
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4620
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4621
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4622
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4624
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4625
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4626
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4627
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4628
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4629
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4630
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4631
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4633
locals->WritebackDelay[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4636
if (mode_lib->vba.BlendingAndTiming[m] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4639
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4653
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4655
if (mode_lib->vba.BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4656
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4660
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4661
for (m = 0; m < locals->NumberOfCursors[k]; m++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4662
locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4663
/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4666
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4667
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4668
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4681
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4683
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4687
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4688
locals->SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4689
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4690
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4706
mode_lib->vba.IsErrorResult[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4709
mode_lib->vba.RequiredDPPCLK[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4711
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4713
mode_lib->vba.DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4714
mode_lib->vba.NoOfDPP[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4715
mode_lib->vba.ScalerEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4716
mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4723
mode_lib->vba.SwathWidthYPerState[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4724
/ mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4725
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4726
mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4727
- mode_lib->vba.VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4728
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4730
mode_lib->vba.MaximumVStartup[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4733
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4734
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4735
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4736
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4740
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4741
mode_lib->vba.MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4742
mode_lib->vba.DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4743
mode_lib->vba.PrefetchLinesY[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4744
mode_lib->vba.SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4745
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4746
mode_lib->vba.PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4747
mode_lib->vba.MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4748
mode_lib->vba.PrefetchLinesC[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4749
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4750
mode_lib->vba.PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4751
mode_lib->vba.MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4752
mode_lib->vba.SwathHeightYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4753
mode_lib->vba.SwathHeightCPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4755
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4757
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4761
&mode_lib->vba.LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4762
&mode_lib->vba.PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4763
&mode_lib->vba.LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4764
&mode_lib->vba.LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4765
&mode_lib->vba.VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4766
&mode_lib->vba.VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4767
&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4769
&mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4770
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4771
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4772
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4778
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4779
if (locals->PDEAndMetaPTEBytesPerFrame[0][0][k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4780
locals->prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4781
else if (locals->LinesForMetaPTE[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4782
locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4783
/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4785
locals->prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4788
if (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4789
locals->prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4790
else if (locals->LinesForMetaAndDPTERow[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4791
locals->prefetch_row_bw[k] = (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4792
/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4794
locals->prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4799
+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4802
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4804
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4805
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4806
dml_max(mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4807
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4808
+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4819
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4820
if (locals->LineTimesForPrefetch[k] < 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4821
|| locals->LinesForMetaPTE[k] >= 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4822
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4823
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4828
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4829
if (locals->VRatioPreY[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4830
|| locals->VRatioPreC[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4831
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4842
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4845
- mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4847
mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4848
mode_lib->vba.PrefetchBW[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4850
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4851
mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4852
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4853
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4854
mode_lib->vba.ImmediateFlipBytes[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4855
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4856
+ mode_lib->vba.MetaRowBytes[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4857
+ mode_lib->vba.DPTEBytesPerRow[0][0][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4861
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4862
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4863
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4866
+ mode_lib->vba.ImmediateFlipBytes[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4870
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4879
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4880
mode_lib->vba.ImmediateFlipBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4881
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4882
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4883
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4884
mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4885
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4886
mode_lib->vba.MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4887
mode_lib->vba.DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4888
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4889
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4890
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4891
mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4892
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4893
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4894
&mode_lib->vba.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4895
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4898
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4901
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4903
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4904
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4905
mode_lib->vba.final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4907
mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4908
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4915
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4916
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4928
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4929
mode_lib->vba.MaxTotalVActiveRDBandwidth = mode_lib->vba.MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4945
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4946
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4947
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4955
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4957
if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4963
/ (mode_lib->vba.CursorWidth[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4964
* mode_lib->vba.CursorBPP[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4967
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4968
/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4969
|| (mode_lib->vba.CursorBPP[k][j] == 64.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4979
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4980
locals->AlignedYPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4981
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4982
locals->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4983
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4986
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4987
locals->AlignedDCCMetaPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4989
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4990
mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4991
64.0 * locals->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4993
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4995
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4998
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
4999
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5000
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5001
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5002
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5003
locals->AlignedCPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5005
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5006
mode_lib->vba.ViewportWidth[k] / 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5007
locals->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5009
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5011
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5090
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5091
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5092
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5103
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5104
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5105
mode_lib->vba.ODMCombineEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5106
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5108
mode_lib->vba.ODMCombineEnabled[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5110
mode_lib->vba.DSCEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5111
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5112
mode_lib->vba.OutputBpp[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
5113
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1145
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1154
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1155
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1160
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1161
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1162
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1163
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1164
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1165
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1166
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1167
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1168
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1169
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1174
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1175
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1176
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1179
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1181
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1185
mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1191
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1193
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1196
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1198
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1199
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1200
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1203
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1205
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1206
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1209
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1210
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1211
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1212
mode_lib->vba.DPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1215
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1216
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1220
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1223
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1227
mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1232
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1234
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1238
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1241
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1242
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1244
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1247
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1249
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1251
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1254
mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1260
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1261
if (mode_lib->vba.BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1263
if (mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1267
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1277
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1281
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1285
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1295
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1332
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1333
if (mode_lib->vba.DPPPerPlane[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1334
mode_lib->vba.DPPCLK_calculated[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1336
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1337
/ mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1342
mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1347
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1348
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1350
mode_lib->vba.DPPCLK_calculated[k] * 255
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1353
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1358
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1359
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1388
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1391
if (mode_lib->vba.SourceScan[k] == dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1392
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1394
mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1396
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1399
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1400
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1404
mode_lib->vba.SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1405
(double) mode_lib->vba.SwathWidthSingleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1407
mode_lib->vba.HActive[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1408
* mode_lib->vba.HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1410
if (mode_lib->vba.DPPPerPlane[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1411
mode_lib->vba.SwathWidthY[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1413
mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1414
/ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1419
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1420
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1421
mode_lib->vba.BytePerPixelDETY[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1422
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1423
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1424
mode_lib->vba.BytePerPixelDETY[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1425
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1426
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1427
mode_lib->vba.BytePerPixelDETY[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1428
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1429
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1430
mode_lib->vba.BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1431
mode_lib->vba.BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1432
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1433
mode_lib->vba.BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1434
mode_lib->vba.BytePerPixelDETC[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1436
mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1437
mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1442
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1443
mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1444
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1445
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1446
* mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1447
mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1448
/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1449
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1450
* mode_lib->vba.VRatio[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1453
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1454
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1455
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1456
mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1457
+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1462
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1464
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1465
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1467
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1477
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1478
if (mode_lib->vba.VRatio[k] <= 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1479
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1480
(double) mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1481
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1482
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1483
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1485
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1486
(double) mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1487
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1488
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1490
if (mode_lib->vba.BytePerPixelDETC[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1491
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1492
else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1493
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1494
mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1495
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1496
/ (mode_lib->vba.HRatio[k] / 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1497
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1499
mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1500
mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1501
/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1502
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1525
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1526
if (mode_lib->vba.WritebackEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1527
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1563
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1564
mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1565
/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1566
mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1567
mode_lib->vba.LinesInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1568
mode_lib->vba.SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1569
mode_lib->vba.FullDETBufferingTimeY[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1570
mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1571
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1572
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1573
/ mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1574
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1575
mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1576
/ mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1577
/ (mode_lib->vba.SwathWidthY[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1578
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1579
mode_lib->vba.LinesInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1580
mode_lib->vba.SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1581
mode_lib->vba.FullDETBufferingTimeC[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1582
mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1583
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1584
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1585
/ (mode_lib->vba.VRatio[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1587
mode_lib->vba.LinesInDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1588
mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1589
mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1594
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1595
if (mode_lib->vba.FullDETBufferingTimeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1598
mode_lib->vba.FullDETBufferingTimeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1600
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1601
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1603
if (mode_lib->vba.FullDETBufferingTimeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1606
mode_lib->vba.FullDETBufferingTimeC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1608
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1609
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1614
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1615
if (mode_lib->vba.DCCEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1618
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1619
/ mode_lib->vba.DCCRate[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1621
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1622
/ mode_lib->vba.DCCRate[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1627
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1629
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1632
if (mode_lib->vba.DCCEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1635
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1637
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1643
+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1645
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1674
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1676
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1677
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1678
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1696
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1697
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1698
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1700
1.1 * mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1702
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1704
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1705
1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1707
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1709
/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1711
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1712
* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1713
/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1714
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1715
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1716
mode_lib->vba.PixelClock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1719
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1723
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1724
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1741
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1744
mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1746
mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1747
* mode_lib->vba.DPPCLK[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1748
* mode_lib->vba.BytePerPixelDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1749
* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1751
/ mode_lib->vba.DPPPerPlane[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1753
mode_lib->vba.SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1756
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1757
/ mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1759
* mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1760
* mode_lib->vba.BytePerPixelDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1762
/ mode_lib->vba.DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1764
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1767
mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1769
mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1770
* mode_lib->vba.DPPCLK[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1771
* mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1772
* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1774
/ mode_lib->vba.DPPPerPlane[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1776
mode_lib->vba.SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1779
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1780
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1781
/ (mode_lib->vba.VRatio[k] / 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1783
* (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1785
* mode_lib->vba.BytePerPixelDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1787
/ mode_lib->vba.DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1788
mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1792
mode_lib->vba.UrgentLatencySupportUs[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1798
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1801
mode_lib->vba.UrgentLatencySupportUs[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1809
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1810
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1811
mode_lib->vba.DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1813
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1814
|| mode_lib->vba.OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1818
if (mode_lib->vba.ODMCombineEnabled[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1819
mode_lib->vba.DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1820
mode_lib->vba.PixelClockBackEnd[k] / 6
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1826
mode_lib->vba.DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1827
mode_lib->vba.PixelClockBackEnd[k] / 3
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1837
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1838
double bpp = mode_lib->vba.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1839
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1841
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1842
if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1843
mode_lib->vba.DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1845
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1848
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1849
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1852
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1854
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1856
mode_lib->vba.DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1859
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1862
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1863
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1866
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1868
mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1870
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1871
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1872
/ mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1874
mode_lib->vba.DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1878
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1880
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1882
mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1885
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1894
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1895
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1896
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1897
dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1898
&mode_lib->vba.BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1899
&mode_lib->vba.BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1900
&mode_lib->vba.BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1901
&mode_lib->vba.BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1904
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1905
mode_lib->vba.BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1906
mode_lib->vba.BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1907
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1908
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1909
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1910
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1911
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1912
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1913
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1918
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1919
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1920
&mode_lib->vba.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1924
&mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1925
&mode_lib->vba.meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1926
mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1928
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1929
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1930
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1932
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1933
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1934
&mode_lib->vba.VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1935
&mode_lib->vba.MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1937
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1938
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1939
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1940
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1944
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1945
mode_lib->vba.BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1946
mode_lib->vba.BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1947
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1948
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1950
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1952
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1953
mode_lib->vba.ViewportWidth[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1954
mode_lib->vba.ViewportHeight[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1955
mode_lib->vba.SwathWidthY[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1960
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1962
&mode_lib->vba.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1966
&mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1967
&mode_lib->vba.meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1968
mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1970
mode_lib->vba.VRatio[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1971
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1972
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1974
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1975
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1976
&mode_lib->vba.VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1977
&mode_lib->vba.MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1982
mode_lib->vba.MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1983
mode_lib->vba.PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1986
mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1987
mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1989
mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1993
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1994
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1995
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1996
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
1999
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2000
mode_lib->vba.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2003
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2004
mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2005
&mode_lib->vba.meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2006
&mode_lib->vba.dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2007
&mode_lib->vba.qual_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2012
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2013
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2014
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2015
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2018
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2019
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2020
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2021
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2022
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2023
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2024
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2025
mode_lib->vba.WritebackDestinationWidth[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2028
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2030
if (mode_lib->vba.BlendingAndTiming[j] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2032
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2034
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2051
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2053
if (mode_lib->vba.BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2054
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2058
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2059
mode_lib->vba.MaxVStartupLines[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2060
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2064
mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2065
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2066
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2070
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2073
mode_lib->vba.MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2075
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2076
mode_lib->vba.cursor_bw[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2077
for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2078
mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2079
* mode_lib->vba.CursorBPP[k][j] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2080
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2081
* mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2096
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2097
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2101
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2102
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2104
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2106
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2107
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2124
CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2125
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2126
mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2128
mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2129
mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2130
mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2132
mode_lib->vba.ErrorResult[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2135
mode_lib->vba.DPPCLK[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2137
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2139
mode_lib->vba.DPPPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2140
mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2141
mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2142
- mode_lib->vba.VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2143
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2147
mode_lib->vba.MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2150
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2151
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2152
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2153
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2157
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2158
mode_lib->vba.MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2159
mode_lib->vba.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2160
mode_lib->vba.PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2161
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2162
mode_lib->vba.BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2163
mode_lib->vba.VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2164
mode_lib->vba.MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2165
mode_lib->vba.PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2166
mode_lib->vba.BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2167
mode_lib->vba.VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2168
mode_lib->vba.MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2169
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2170
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2172
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2174
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2176
mode_lib->vba.DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2177
mode_lib->vba.DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2178
&mode_lib->vba.DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2179
&mode_lib->vba.PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2180
&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2181
&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2182
&mode_lib->vba.VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2183
&mode_lib->vba.VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2184
&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2185
&mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2186
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2187
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2188
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2190
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2191
mode_lib->vba.VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2193
mode_lib->vba.MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2196
mode_lib->vba.VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2200
mode_lib->vba.VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2203
mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2207
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2209
if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2210
mode_lib->vba.prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2211
else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2212
mode_lib->vba.prefetch_vm_bw[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2213
(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2214
/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2215
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2216
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2218
mode_lib->vba.prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2221
if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2223
mode_lib->vba.prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2224
else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2225
mode_lib->vba.prefetch_row_bw[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2226
(double) (mode_lib->vba.MetaRowByte[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2227
+ mode_lib->vba.PixelPTEBytesPerRow[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2228
/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2229
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2230
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2232
mode_lib->vba.prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2237
MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2239
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2241
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2243
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2244
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2245
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2246
+ mode_lib->vba.meta_row_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2247
+ mode_lib->vba.dpte_row_bw[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2249
if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2251
if (mode_lib->vba.VRatioPrefetchY[k] > 4
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2252
|| mode_lib->vba.VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2272
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2275
- mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2277
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2278
+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2279
+ mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2280
mode_lib->vba.PrefetchBandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2283
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2284
ImmediateFlipBytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2285
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2286
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2287
ImmediateFlipBytes[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2288
mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2289
+ mode_lib->vba.MetaRowByte[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2290
+ mode_lib->vba.PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2294
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2295
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2296
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2299
+ ImmediateFlipBytes[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2302
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2311
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2312
ImmediateFlipBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2313
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2314
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2315
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2316
mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2317
mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2318
mode_lib->vba.MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2319
mode_lib->vba.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2320
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2321
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2322
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2323
mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2324
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2325
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2326
&final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2327
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2329
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2332
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2334
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2336
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2337
final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2339
mode_lib->vba.ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2340
+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2341
mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2347
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2348
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2356
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2357
if (mode_lib->vba.ErrorResult[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2371
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2372
if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2373
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2374
mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2375
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2376
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2378
mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2379
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2380
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2381
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2383
if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2384
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2386
if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2387
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2388
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2389
* mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2390
/ mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2391
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2393
mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2394
mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2395
/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2396
/ mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2402
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2404
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2405
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2406
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2412
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2413
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2414
mode_lib->vba.MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2418
mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2419
mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2420
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2422
if (!mode_lib->vba.DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2423
mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2424
+ mode_lib->vba.MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2430
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2431
mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2434
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2448
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2449
/ (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2451
mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2453
1)) - (mode_lib->vba.vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2460
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2461
/ (mode_lib->vba.SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2464
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2468
- (mode_lib->vba.VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2471
/ mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2472
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2475
/ (mode_lib->vba.VRatio[k] / 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2476
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2478
if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2480
/ mode_lib->vba.SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2481
} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2487
if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2489
/ (mode_lib->vba.SwathWidthY[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2490
} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2496
DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2498
MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2499
+ (mode_lib->vba.LinesInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2500
- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2501
/ mode_lib->vba.SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2502
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2503
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2512
* mode_lib->vba.SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2513
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2514
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2517
if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2518
double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2519
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2523
mode_lib->vba.FullDETBufferingTimeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2524
+ (mode_lib->vba.LinesInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2525
- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2526
/ mode_lib->vba.SwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2527
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2528
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2540
* mode_lib->vba.SwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2541
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2542
/ mode_lib->vba.PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2544
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2548
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2552
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2555
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2559
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2560
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2561
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2562
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2563
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2566
} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2574
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2575
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2576
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2577
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2578
/ mode_lib->vba.PixelClock[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2586
/ (mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2587
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2588
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2589
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2590
/ mode_lib->vba.PixelClock[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2593
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2594
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2604
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2605
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2608
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2609
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2610
PlaneWithMinActiveDRAMClockChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2613
if (mode_lib->vba.BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2624
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2625
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (mode_lib->vba.BlendingAndTiming[k] == k))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2626
&& !(mode_lib->vba.BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2627
&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2630
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2638
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2642
mode_lib->vba.MinTTUVBlank[k] += 25;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2657
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2658
if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2668
for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2670
mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2673
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2674
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2677
mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2678
mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2679
mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2687
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2688
mode_lib->vba.SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2689
dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2690
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2703
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2706
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2707
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2709
mode_lib->vba.XFCTransferDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2712
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2713
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2715
mode_lib->vba.XFCPrechargeDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2720
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2721
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2726
(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2727
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2728
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2729
/ mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2741
mode_lib->vba.XFCPrefetchMargin[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2744
+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2745
+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2746
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2747
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2749
mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2750
mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2751
mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2752
mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2753
mode_lib->vba.XFCPrechargeDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2754
mode_lib->vba.XFCTransferDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2755
mode_lib->vba.XFCPrefetchMargin[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2762
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2763
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2764
unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2765
* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2775
if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2777
mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2801
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2803
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2806
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2809
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2812
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2815
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2818
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2826
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2827
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2828
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2829
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2830
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2832
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2834
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2835
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2845
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2848
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2861
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2869
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2870
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2871
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2872
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2873
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2874
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2875
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2877
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2879
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2881
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2883
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2885
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2887
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2889
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2891
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2892
&& mode_lib->vba.SourceScan[k] != dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2899
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2902
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2903
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2906
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2907
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2916
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2917
SwathWidth = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2919
SwathWidth = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2922
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2926
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2927
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2935
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2937
if (mode_lib->vba.DPPPerPlane[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2940
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2948
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2959
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2969
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2970
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2972
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2973
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2976
if (mode_lib->vba.SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2977
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0] * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2978
mode_lib->vba.DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2979
} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2980
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2982
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2985
mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
2987
mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte[0]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3395
unsigned int j, k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3402
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3403
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3404
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3405
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3406
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3407
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3408
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3409
|| mode_lib->vba.HRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3410
|| mode_lib->vba.htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3411
|| mode_lib->vba.VRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3412
|| mode_lib->vba.vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3414
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3415
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3416
|| (mode_lib->vba.htaps[k] > 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3417
&& (mode_lib->vba.htaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3418
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3419
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3420
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3421
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3422
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3423
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3424
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3425
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3426
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3427
&& (mode_lib->vba.HRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3428
> mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3429
|| mode_lib->vba.VRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3430
> mode_lib->vba.VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3437
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3438
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3439
&& mode_lib->vba.SourceScan[k] != dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3440
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3441
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3442
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3443
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3444
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3445
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3446
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3447
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3448
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3449
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3450
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3452
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3454
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3455
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3457
&& !((mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3459
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3461
&& mode_lib->vba.SourceScan[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3465
&& mode_lib->vba.DCCEnable[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3467
|| (mode_lib->vba.DCCEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3468
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3470
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3472
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3479
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3480
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3481
locals->BytePerPixelInDETY[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3482
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3483
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3484
locals->BytePerPixelInDETY[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3485
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3486
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3487
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3488
locals->BytePerPixelInDETY[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3489
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3490
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3491
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3492
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3493
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3494
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3495
locals->BytePerPixelInDETC[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3497
locals->BytePerPixelInDETY[k] = 4.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3498
locals->BytePerPixelInDETC[k] = 8.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3500
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3501
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3503
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3506
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3507
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3508
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3509
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3510
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3511
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3513
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3514
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3515
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3516
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3517
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3518
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3519
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3520
/ mode_lib->vba.PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3521
} else if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3522
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3523
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3524
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3525
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3526
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3527
/ mode_lib->vba.PixelClock[k]) * 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3528
} else if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3529
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3530
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3531
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3532
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3533
/ mode_lib->vba.PixelClock[k]) * 1.5;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3535
locals->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3539
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3540
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3603
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3604
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3605
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3606
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3613
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3641
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3642
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3643
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3644
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3647
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3654
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3655
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3657
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3664
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3665
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3667
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3668
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3671
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3672
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3674
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3676
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3678
|| mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3680
|| mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3682
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3683
> mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3684
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3685
> mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3686
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3687
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3689
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3690
&& (mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3692
|| mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3695
* mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3696
> mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3698
* mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3699
> mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3700
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3701
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3704
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3706
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3710
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3711
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3715
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3717
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3718
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3720
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3722
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3723
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3726
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3730
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3735
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3736
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3738
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3740
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3741
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3744
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3753
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3754
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3759
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3760
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3761
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3762
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3763
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3764
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3765
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3766
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3767
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3768
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3772
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3773
if (mode_lib->vba.HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3774
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3777
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3779
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3783
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3787
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3788
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3789
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3790
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3792
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3795
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3796
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3797
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3798
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3800
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3801
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3802
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3803
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3804
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3807
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3808
locals->PSCL_FACTOR_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3812
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3815
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3819
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3823
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3824
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3826
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3829
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3830
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3831
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3832
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3833
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3837
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3839
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3840
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3842
/ locals->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3844
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3845
|| mode_lib->vba.HTAPsChroma[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3846
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3847
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3848
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3849
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3850
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3854
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3856
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3857
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3858
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3859
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3860
&locals->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3861
&locals->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3862
&locals->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3863
&locals->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3864
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3865
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3866
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3868
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3869
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3871
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3872
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3873
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3874
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3875
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3876
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3877
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3878
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3880
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3882
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3884
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3886
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3888
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3890
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3892
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3893
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3895
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3898
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3900
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3901
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3902
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3903
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3904
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3905
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3907
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3908
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3909
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3910
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3912
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3914
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3915
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3918
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3927
/ (locals->BytePerPixelInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3928
* locals->MinSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3929
+ locals->BytePerPixelInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3931
* locals->MinSwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3932
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3935
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3936
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3937
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3940
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3949
mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3951
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3952
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3955
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3961
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3964
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3965
/ (mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3968
mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3974
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3992
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3994
mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
3998
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4001
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4005
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4008
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4012
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4014
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4015
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4017
} else if (locals->HActive[k] > DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4018
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4023
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4024
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4025
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4026
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4027
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4028
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4030
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4031
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4032
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4037
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4044
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4045
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4054
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4055
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4056
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4057
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4070
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4071
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4072
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4073
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4074
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4077
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4078
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4083
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4087
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4093
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4099
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4100
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4115
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4116
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4117
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4118
> locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4122
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4141
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4142
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4155
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4156
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4157
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4158
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4163
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4164
locals->RequiresDSC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4165
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4166
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4167
if (mode_lib->vba.Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4168
locals->RequiresDSC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4169
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4170
locals->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4171
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4172
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4174
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4175
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4176
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4177
} else if (mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4178
|| mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4179
if (mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4188
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4189
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4191
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4192
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4193
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4196
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4197
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4199
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4200
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4201
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4202
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4203
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4204
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4205
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4207
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4211
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4212
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4214
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4219
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4220
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4222
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4223
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4224
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4227
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4228
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4230
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4231
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4232
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4233
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4234
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4235
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4236
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4238
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4242
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4243
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4245
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4252
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4253
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4255
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4256
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4257
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4260
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4261
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4263
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4264
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4265
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4266
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4267
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4268
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4269
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4271
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4275
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4276
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4278
locals->OutputBppPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4283
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4289
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4290
if (!mode_lib->vba.skip_dio_check[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4291
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4292
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4293
&& mode_lib->vba.Interlace[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4300
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4302
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4303
if ((mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4304
|| mode_lib->vba.Output[k] == dm_edp)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4305
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4306
|| mode_lib->vba.OutputFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4312
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4313
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4314
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4320
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4334
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4335
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4336
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4352
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4353
if (mode_lib->vba.BlendingAndTiming[k] != k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4355
} else if (locals->RequiresDSC[i][k] == 0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4356
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4358
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4360
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4362
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4364
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4366
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4371
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4372
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4375
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4377
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4378
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4379
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4381
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4384
mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4388
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4390
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4392
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4394
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4396
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4398
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4399
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4401
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4402
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4404
locals->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4407
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4410
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4411
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4420
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4421
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4422
locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4424
locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4425
locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4426
locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4427
+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4428
if (locals->SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4431
if (locals->MaxSwathHeightC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4432
locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4434
locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4435
+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4437
if (locals->SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4444
locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4445
locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4447
locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4448
locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4451
if (locals->BytePerPixelInDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4452
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4454
} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4455
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETY[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4456
locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4457
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4459
locals->LinesInDETLuma = locals->DETBufferSizeInKByte[0] * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4460
locals->LinesInDETChroma = locals->DETBufferSizeInKByte[0] * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4464
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4465
/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4468
dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4469
/ (locals->SwathWidthYPerState[i][j][k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4470
/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4473
locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4474
locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4476
locals->SwathHeightYPerState[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4479
if (locals->BytePerPixelInDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4480
locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4481
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4482
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4485
locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4486
locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4488
locals->SwathHeightCPerState[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4489
locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4490
locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4491
/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4492
dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4493
locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4494
locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4495
dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i][0] / locals->NoOfDPP[i][j][k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4504
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4505
if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4516
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4517
if (locals->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4519
locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4528
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4529
locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4534
for (k = 0; k < locals->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4535
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4536
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4537
locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4538
locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4539
locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4542
mode_lib->vba.PixelClock[k] / 16.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4543
if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4544
if (mode_lib->vba.VRatio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4550
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4553
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4554
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4555
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4562
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4565
* mode_lib->vba.PSCL_FACTOR[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4566
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4569
if (mode_lib->vba.VRatio[k] <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4575
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4578
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4579
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4580
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4587
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4590
* mode_lib->vba.PSCL_FACTOR[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4591
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4593
if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4599
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4602
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4604
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4605
/ mode_lib->vba.NoOfDPP[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4612
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4615
* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4616
* mode_lib->vba.RequiredDPPCLK[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4620
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4623
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4624
mode_lib->vba.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4625
mode_lib->vba.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4626
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4627
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4628
dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4629
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4630
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4631
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4632
mode_lib->vba.SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4637
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4638
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4639
&mode_lib->vba.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4642
&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4643
&mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4644
&mode_lib->vba.meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4645
mode_lib->vba.PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4647
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4648
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4649
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4651
mode_lib->vba.SwathHeightYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4652
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4653
&mode_lib->vba.PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4654
&mode_lib->vba.MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4655
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4656
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4657
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4658
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4659
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4662
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4663
mode_lib->vba.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4664
mode_lib->vba.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4665
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4666
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4667
dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4668
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4669
mode_lib->vba.ViewportWidth[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4670
mode_lib->vba.ViewportHeight[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4671
mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4676
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4678
&mode_lib->vba.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4681
&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4682
&mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4683
&mode_lib->vba.meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4684
mode_lib->vba.PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4686
mode_lib->vba.VRatio[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4687
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4688
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4690
mode_lib->vba.SwathHeightCPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4691
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4692
&mode_lib->vba.PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4693
&mode_lib->vba.MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4698
locals->PrefetchLinesC[0][0][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4699
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4702
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4704
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4705
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4709
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4710
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4711
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4712
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4715
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4716
mode_lib->vba.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4719
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4720
mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4721
&mode_lib->vba.meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4722
&mode_lib->vba.dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4723
&mode_lib->vba.qual_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4741
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4742
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4743
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4744
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4746
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4747
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4748
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4749
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4750
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4751
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4752
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4753
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4755
locals->WritebackDelay[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4758
if (mode_lib->vba.BlendingAndTiming[m] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4761
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4775
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4777
if (mode_lib->vba.BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4778
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4782
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4783
for (m = 0; m < locals->NumberOfCursors[k]; m++)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4784
locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4785
/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4788
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4789
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4790
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4803
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4805
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4809
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4810
locals->SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4811
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4812
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4829
CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i][0], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4830
mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4831
mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4833
mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4834
mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4835
&mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4837
mode_lib->vba.IsErrorResult[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4840
mode_lib->vba.RequiredDPPCLK[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4842
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4844
mode_lib->vba.NoOfDPP[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4845
mode_lib->vba.NumberOfCursors[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4846
mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4847
- mode_lib->vba.VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4848
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4850
mode_lib->vba.MaximumVStartup[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4853
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4854
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4855
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4856
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4860
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4861
mode_lib->vba.MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4862
mode_lib->vba.DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4863
mode_lib->vba.PrefetchLinesY[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4864
mode_lib->vba.SwathWidthYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4865
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4866
mode_lib->vba.PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4867
mode_lib->vba.MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4868
mode_lib->vba.PrefetchLinesC[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4869
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4870
mode_lib->vba.PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4871
mode_lib->vba.MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4872
mode_lib->vba.SwathHeightYPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4873
mode_lib->vba.SwathHeightCPerState[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4875
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4877
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4879
mode_lib->vba.DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4880
mode_lib->vba.DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4881
&mode_lib->vba.LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4882
&mode_lib->vba.PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4883
&mode_lib->vba.LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4884
&mode_lib->vba.LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4885
&mode_lib->vba.VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4886
&mode_lib->vba.VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4887
&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4888
&mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4889
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4890
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4891
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4897
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4898
if (locals->PDEAndMetaPTEBytesPerFrame[0][0][k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4899
locals->prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4900
else if (locals->LinesForMetaPTE[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4901
locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4902
/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4904
locals->prefetch_vm_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4907
if (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4908
locals->prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4909
else if (locals->LinesForMetaAndDPTERow[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4910
locals->prefetch_row_bw[k] = (locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4911
/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4913
locals->prefetch_row_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4918
+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4921
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4923
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4924
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4925
dml_max(mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4926
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4927
+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4938
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4939
if (locals->LineTimesForPrefetch[k] < 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4940
|| locals->LinesForMetaPTE[k] >= 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4941
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4942
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4947
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4948
if (locals->VRatioPreY[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4949
|| locals->VRatioPreC[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4950
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4961
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4964
- mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4966
mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4967
mode_lib->vba.PrefetchBW[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4969
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4970
mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4971
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4972
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4973
mode_lib->vba.ImmediateFlipBytes[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4974
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4975
+ mode_lib->vba.MetaRowBytes[0][0][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4976
+ mode_lib->vba.DPTEBytesPerRow[0][0][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4980
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4981
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4982
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4985
+ mode_lib->vba.ImmediateFlipBytes[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4989
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4998
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
4999
mode_lib->vba.ImmediateFlipBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5000
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5001
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5002
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5003
mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5004
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5005
mode_lib->vba.MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5006
mode_lib->vba.DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5007
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5008
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5009
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5010
mode_lib->vba.qual_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5011
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5012
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5013
&mode_lib->vba.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5014
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5017
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5020
+ mode_lib->vba.cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5022
mode_lib->vba.prefetch_vm_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5023
mode_lib->vba.prefetch_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5024
mode_lib->vba.final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5026
mode_lib->vba.ReadBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5027
mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5034
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5035
if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5061
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5062
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5063
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5071
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5073
if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5079
/ (mode_lib->vba.CursorWidth[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5080
* mode_lib->vba.CursorBPP[k][j]
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5083
* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5084
/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5085
|| (mode_lib->vba.CursorBPP[k][j] == 64.0
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5095
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5096
locals->AlignedYPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5097
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5098
locals->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5099
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5102
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5103
locals->AlignedDCCMetaPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5105
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5106
mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5107
64.0 * locals->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5109
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5111
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5114
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5115
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5116
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5117
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5118
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5119
locals->AlignedCPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5121
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5122
mode_lib->vba.ViewportWidth[k] / 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5123
locals->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5125
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5127
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5206
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5207
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5208
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5219
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5220
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5221
mode_lib->vba.ODMCombineEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5222
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5224
mode_lib->vba.ODMCombineEnabled[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5226
mode_lib->vba.DSCEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5227
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5228
mode_lib->vba.OutputBpp[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
5229
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1469
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1478
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1479
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1484
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1485
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1486
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1487
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1488
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1489
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1490
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1491
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1492
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1493
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1498
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1499
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1500
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1503
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1505
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1509
locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1515
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1517
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1520
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1522
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1523
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1524
/ locals->PSCL_THROUGHPUT_LUMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1527
if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1529
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1530
mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1533
if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1534
&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1535
locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1536
locals->DPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1539
if (mode_lib->vba.HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1540
locals->PSCL_THROUGHPUT_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1544
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1547
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1551
locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1556
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1558
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1562
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1565
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1566
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1568
/ locals->PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1571
if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1573
< 2 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1575
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1578
locals->DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1584
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1585
if (mode_lib->vba.BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1587
if (mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1591
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1601
mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1605
} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1609
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1619
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1656
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1657
mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1658
/ mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1662
mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1667
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1668
mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1670
mode_lib->vba.DPPCLK_calculated[k] * 255
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1673
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1681
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1684
if (mode_lib->vba.SourceScan[k] == dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1685
locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1687
locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1689
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1692
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1693
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1697
locals->SwathWidthY[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1698
(double) locals->SwathWidthSingleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1700
mode_lib->vba.HActive[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1701
* mode_lib->vba.HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1703
locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1704
/ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1707
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1708
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1709
locals->BytePerPixelDETY[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1710
locals->BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1711
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1712
locals->BytePerPixelDETY[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1713
locals->BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1714
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1715
locals->BytePerPixelDETY[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1716
locals->BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1717
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1718
locals->BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1719
locals->BytePerPixelDETC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1720
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1721
locals->BytePerPixelDETY[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1722
locals->BytePerPixelDETC[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1724
locals->BytePerPixelDETY[k] = 4.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1725
locals->BytePerPixelDETC[k] = 8.0 / 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1730
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1731
locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1732
* dml_ceil(locals->BytePerPixelDETY[k], 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1733
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1734
* mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1735
locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1736
/ 2 * dml_ceil(locals->BytePerPixelDETC[k], 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1737
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1738
* mode_lib->vba.VRatio[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1741
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1742
locals->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1743
+ locals->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1744
mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1745
+ locals->ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1765
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1766
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1767
locals->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1769
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1770
|| mode_lib->vba.OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1774
if (mode_lib->vba.ODMCombineEnabled[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1775
locals->DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1776
mode_lib->vba.PixelClockBackEnd[k] / 6
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1782
locals->DSCCLK_calculated[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1783
mode_lib->vba.PixelClockBackEnd[k] / 3
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1793
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1794
double bpp = mode_lib->vba.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1795
unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1797
if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1798
if (!mode_lib->vba.ODMCombineEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1799
locals->DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1801
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1804
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1805
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1808
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1810
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1812
locals->DSCDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1815
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1818
(double) mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1819
/ mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1822
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1824
mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1826
locals->DSCDelay[k] = locals->DSCDelay[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1827
* mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1828
/ mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1830
locals->DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1834
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1836
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1838
locals->DSCDelay[k] = locals->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1841
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1852
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1853
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1854
dml_ceil(locals->BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1855
dml_ceil(locals->BytePerPixelDETC[k], 2),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1856
&locals->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1857
&locals->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1858
&locals->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1859
&locals->BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1861
locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1863
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1864
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1865
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1867
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1868
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1869
&locals->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1870
&locals->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1872
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1873
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1874
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1875
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1879
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1880
locals->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1881
locals->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1882
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1883
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1885
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1887
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1888
mode_lib->vba.ViewportWidth[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1889
mode_lib->vba.ViewportHeight[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1890
locals->SwathWidthY[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1897
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1898
mode_lib->vba.DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1899
&locals->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1903
&locals->dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1904
&locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1905
&locals->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1906
&locals->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1907
&locals->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1908
&locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1911
&locals->PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1912
&locals->PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1913
&locals->PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1914
&locals->dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1915
&locals->meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1917
locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1919
mode_lib->vba.VRatio[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1920
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1921
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1923
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1924
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1925
&locals->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1926
&locals->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1931
locals->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1932
locals->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1938
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1939
locals->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1940
locals->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1941
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1942
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1943
dml_ceil(locals->BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1944
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1945
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1946
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1947
locals->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1954
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1955
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1956
&locals->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1960
&locals->dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1961
&locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1962
&locals->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1963
&locals->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1964
&locals->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1965
&locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1966
&locals->vm_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1967
&locals->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1968
&locals->PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1969
&locals->PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1970
&locals->PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1971
&locals->dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1972
&locals->meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1974
locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1975
locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1977
locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1981
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1982
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1983
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1984
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1987
locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1988
locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1991
locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1992
locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1993
&locals->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1994
&locals->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
1999
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2001
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2002
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2004
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2038
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2039
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2040
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2041
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2044
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2045
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2046
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2047
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2048
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2049
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2050
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2051
mode_lib->vba.WritebackDestinationWidth[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2054
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2056
if (mode_lib->vba.BlendingAndTiming[j] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2058
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2060
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2077
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2079
if (mode_lib->vba.BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2080
locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2084
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2085
locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2088
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2089
locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2106
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2110
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2114
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2115
locals->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2117
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2119
mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2120
/ mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2137
myPipe.DPPCLK = locals->DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2139
myPipe.PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2141
myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2142
myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2143
myPipe.SourceScan = mode_lib->vba.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2144
myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2145
myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2146
myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2147
myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2148
myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2149
myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2150
myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2151
myPipe.HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2158
mode_lib->vba.ErrorResult[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2164
locals->DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2171
(unsigned int) (locals->SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2172
/ mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2173
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2175
dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2176
locals->MaxVStartupLines[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2180
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2181
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2182
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2183
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2187
locals->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2188
locals->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2189
locals->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2190
locals->PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2191
locals->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2192
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2193
locals->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2194
locals->MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2195
locals->PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2196
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2197
locals->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2198
locals->MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2199
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2200
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2202
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2205
&locals->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2206
&locals->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2207
&locals->DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2208
&locals->PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2209
&locals->DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2210
&locals->DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2211
&locals->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2212
&locals->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2213
&locals->RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2214
&locals->RequiredPrefetchPixDataBWChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2216
&locals->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2217
&locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2218
&locals->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2219
&locals->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2220
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2221
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2222
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2223
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2224
locals->VStartup[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2226
locals->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2229
locals->VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2233
locals->VStartup[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2236
locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2240
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2243
locals->cursor_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2244
locals->cursor_bw_pre[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2245
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2246
locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2247
locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2252
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2253
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2254
locals->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2255
mode_lib->vba.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2256
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2259
mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2260
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2261
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2262
locals->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2263
locals->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2264
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2265
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2266
&locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2267
&locals->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2268
&locals->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2269
&locals->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2270
&locals->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2271
&locals->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2276
locals->UrgentBurstFactorLuma[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2277
locals->UrgentBurstFactorChroma[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2278
locals->UrgentBurstFactorCursor[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2279
locals->UrgentBurstFactorLumaPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2280
locals->UrgentBurstFactorChromaPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2281
locals->UrgentBurstFactorCursorPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2285
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2286
locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2287
+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2288
* locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2289
locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2290
* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2293
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2294
locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2295
+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2296
locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2298
if (locals->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2300
if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2317
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2321
locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2322
+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2323
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2324
locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2325
locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2326
locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2330
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2331
mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2333
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2345
locals->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2346
locals->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2347
locals->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2350
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2351
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2352
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2353
locals->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2354
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2355
locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2356
locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2357
locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2358
locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2359
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2360
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2361
&locals->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2362
&locals->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2366
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2369
locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2370
locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2371
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2372
locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2373
+ locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2374
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2377
dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2378
locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2379
locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2388
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2389
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2397
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2398
if (mode_lib->vba.ErrorResult[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2561
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2563
locals->AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2564
locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2565
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2571
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2572
locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2573
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2577
locals->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2578
locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2579
locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2581
if (!mode_lib->vba.DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2582
locals->MinTTUVBlank[k] = mode_lib->vba.TCalc
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2583
+ locals->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2588
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2589
locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2590
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2592
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2593
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2595
locals->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2596
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2597
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2598
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2599
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2600
&locals->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2601
&locals->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2602
&locals->DCCYIndependent64ByteBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2606
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2607
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2610
locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2611
locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2612
locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2620
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2621
locals->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2622
dml_ceil(locals->BytePerPixelDETY[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2623
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2636
locals->XFCRemoteSurfaceFlipLatency[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2639
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2640
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2642
locals->XFCTransferDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2645
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2646
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2648
locals->XFCPrechargeDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2653
/ (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2654
/ mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2659
(locals->DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2660
+ locals->DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2661
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2662
/ mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2674
locals->XFCPrefetchMargin[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2677
+ (locals->DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2678
+ locals->DestinationLinesToRequestRowInVBlank[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2679
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2680
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2682
locals->XFCSlaveVUpdateOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2683
locals->XFCSlaveVupdateWidth[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2684
locals->XFCSlaveVReadyOffset[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2685
locals->XFCRemoteSurfaceFlipLatency[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2686
locals->XFCPrechargeDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2687
locals->XFCTransferDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2688
locals->XFCPrefetchMargin[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2693
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2696
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2697
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2698
&locals->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2699
&locals->DETBufferSizeC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2701
locals->LinesInDETY[k] = (double)locals->DETBufferSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2702
/ locals->BytePerPixelDETY[k] / locals->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2703
locals->LinesInDETYRoundedDownToSwath[k] = dml_floor(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2704
locals->LinesInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2705
mode_lib->vba.SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2706
locals->FullDETBufferingTimeY[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2707
locals->LinesInDETYRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2708
* (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2709
/ mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2710
/ mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2714
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2715
if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2716
mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2718
(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2719
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2720
locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2721
locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2723
mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2729
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2732
if (mode_lib->vba.DCCEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2733
if (locals->DCCYMaxCompressedBlock[k] == 256)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2740
+ (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2741
dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2745
+ locals->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2746
+ locals->ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2749
locals->meta_row_bw[k] + locals->dpte_row_bw[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2773
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2774
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2788
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2790
mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2791
- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2792
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2826
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2828
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2831
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2834
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2837
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2840
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2843
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2851
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2852
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2853
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2854
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2855
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2857
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2859
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2860
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2870
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2873
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2886
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2894
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2895
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2896
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2897
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2898
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2899
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2900
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2902
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2904
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2906
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2908
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2910
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2912
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2914
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2916
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2917
&& mode_lib->vba.SourceScan[k] != dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2924
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2927
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2928
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2931
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2932
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2941
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2942
SwathWidth = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2944
SwathWidth = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2947
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2951
if (mode_lib->vba.BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2952
&& mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2960
mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2962
SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2970
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2981
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2991
mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2992
mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2994
mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
2995
mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3000
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3001
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3002
&mode_lib->vba.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3003
&mode_lib->vba.DETBufferSizeC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3401
unsigned k)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3407
if (mode_lib->vba.XFCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3411
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3412
locals->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3413
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3414
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3431
myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3433
myPipe.PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3435
myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3436
myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3437
myPipe.SourceScan = mode_lib->vba.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3438
myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3439
myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3440
myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3441
myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3442
myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3443
myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3444
myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3445
myPipe.HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3453
mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3458
locals->DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3465
locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3466
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3468
dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[0][0][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3469
locals->MaximumVStartup[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3473
mode_lib->vba.DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3474
mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3475
mode_lib->vba.DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3476
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3480
locals->PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3481
locals->MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3482
locals->DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3483
locals->PrefetchLinesY[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3484
locals->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3485
locals->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3486
locals->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3487
locals->MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3488
locals->PrefetchLinesC[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3489
locals->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3490
locals->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3491
locals->MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3492
locals->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3493
locals->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3495
mode_lib->vba.XFCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3500
&locals->LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3501
&locals->PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3502
&locals->LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3503
&locals->LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3504
&locals->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3505
&locals->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3506
&locals->RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3507
&locals->RequiredPrefetchPixelDataBWChroma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3509
&locals->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3510
&locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3513
&mode_lib->vba.VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3514
&mode_lib->vba.VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3515
&mode_lib->vba.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3522
unsigned int j, k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3529
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3530
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3531
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3532
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3533
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3534
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3535
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3536
|| mode_lib->vba.HRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3537
|| mode_lib->vba.htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3538
|| mode_lib->vba.VRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3539
|| mode_lib->vba.vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3541
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3542
|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3543
|| (mode_lib->vba.htaps[k] > 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3544
&& (mode_lib->vba.htaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3545
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3546
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3547
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3548
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3549
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3550
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3551
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3552
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3553
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3554
&& (mode_lib->vba.HRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3555
> mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3556
|| mode_lib->vba.VRatio[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3557
> mode_lib->vba.VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3564
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3565
if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3566
&& mode_lib->vba.SourceScan[k] != dm_horz)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3567
|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3568
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3569
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3570
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3571
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3572
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3573
|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3574
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3575
|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3576
&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3577
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3579
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3581
|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3582
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3584
&& !((mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3586
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3588
&& mode_lib->vba.SourceScan[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3592
&& mode_lib->vba.DCCEnable[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3594
|| (mode_lib->vba.DCCEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3595
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3597
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3599
|| mode_lib->vba.SourcePixelFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3606
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3607
if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3608
locals->BytePerPixelInDETY[k] = 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3609
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3610
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3611
locals->BytePerPixelInDETY[k] = 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3612
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3613
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3614
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3615
locals->BytePerPixelInDETY[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3616
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3617
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3618
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3619
locals->BytePerPixelInDETC[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3620
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3621
locals->BytePerPixelInDETY[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3622
locals->BytePerPixelInDETC[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3624
locals->BytePerPixelInDETY[k] = 4.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3625
locals->BytePerPixelInDETC[k] = 8.0 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3627
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3628
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3630
locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3633
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3634
locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3635
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3636
locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3637
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3638
locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3640
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3641
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3642
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3643
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3644
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3645
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3646
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3647
/ mode_lib->vba.PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3648
} else if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3649
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3650
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3651
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3652
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3653
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3654
/ mode_lib->vba.PixelClock[k]) * 3.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3655
} else if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3656
locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3657
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3658
/ (mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3659
* mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3660
/ mode_lib->vba.PixelClock[k]) * 1.5;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3662
locals->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3666
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3667
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3689
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3690
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3691
if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3692
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3699
if (locals->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3730
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3731
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3732
if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3733
mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3736
+ mode_lib->vba.ActiveWritebacksPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3743
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3744
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3746
&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3753
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3754
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3756
&& (mode_lib->vba.WritebackHRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3757
|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3760
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3761
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3763
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3765
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3767
|| mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3769
|| mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3771
|| mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3772
> mode_lib->vba.WritebackLumaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3773
|| mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3774
> mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3775
|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3776
&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3778
|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3779
&& (mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3781
|| mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3784
* mode_lib->vba.WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3785
> mode_lib->vba.WritebackChromaHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3787
* mode_lib->vba.WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3788
> mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3789
|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3790
&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3793
if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3795
dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3799
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3800
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3804
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3806
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3807
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3809
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3811
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3812
&& mode_lib->vba.WritebackLumaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3815
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3819
if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3824
if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3825
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3827
* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3829
|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3830
&& mode_lib->vba.WritebackChromaVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3833
/ mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3842
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3843
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3848
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3849
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3850
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3851
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3852
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3853
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3854
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3855
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3856
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3857
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3861
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3862
if (mode_lib->vba.HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3863
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3866
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3868
mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3872
locals->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3876
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3877
locals->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3878
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3879
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3881
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3884
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3885
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3886
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3887
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3889
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3890
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3891
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3892
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3893
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3896
if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3897
locals->PSCL_FACTOR_CHROMA[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3901
* mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3904
mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3908
locals->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3912
locals->MinDPPCLKUsingSingleDPP[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3913
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3915
mode_lib->vba.vtaps[k] / 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3918
mode_lib->vba.HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3919
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3920
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3921
/ locals->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3922
mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3926
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3928
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3929
* mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3931
/ locals->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3933
if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3934
|| mode_lib->vba.HTAPsChroma[k] > 6.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3935
|| mode_lib->vba.VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3936
&& locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3937
< 2.0 * mode_lib->vba.PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3938
locals->MinDPPCLKUsingSingleDPP[k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3939
* mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3943
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3945
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3946
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3947
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3948
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3949
&locals->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3950
&locals->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3951
&locals->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3952
&locals->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3953
if (mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3954
locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3955
locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3957
locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3958
locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3960
if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3961
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3962
|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3963
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3964
|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3965
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3966
|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3967
&& (mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3969
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3971
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3973
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3975
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3977
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3979
|| mode_lib->vba.SurfaceTiling[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3981
&& mode_lib->vba.SourceScan[k] == dm_horz)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3982
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3984
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3987
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3989
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3990
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3991
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3992
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3993
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3994
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3996
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3997
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3998
&& mode_lib->vba.SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
3999
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4001
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4003
locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4004
locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4007
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4016
/ (locals->BytePerPixelInDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4017
* locals->MinSwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4018
+ locals->BytePerPixelInDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4020
* locals->MinSwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4021
if (locals->BytePerPixelInDETC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4024
* dml_max(mode_lib->vba.HRatio[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4025
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4026
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4029
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4038
mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4040
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4041
/ (mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4044
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4050
mode_lib->vba.HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4053
/ mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4054
/ (mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4057
mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4063
locals->MaximumSwathWidth[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4081
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4083
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4092
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4095
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4099
mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4102
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4106
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4108
} else if (locals->DSCEnabled[k] && (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4109
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4111
} else if (locals->HActive[k] > DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4112
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4117
if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4118
&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4119
&& locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4120
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4121
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4122
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4124
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4125
locals->RequiredDPPCLK[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4126
locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4131
if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4138
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4139
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4148
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4149
if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4150
BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4151
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4164
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4165
locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4166
if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4167
locals->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4168
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4171
locals->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4172
locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4177
mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4181
mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4187
if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4193
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4194
locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4209
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4210
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4211
if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4212
> locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4216
if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4235
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4236
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4249
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4250
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4251
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4252
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4257
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4258
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4259
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4260
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4261
if (mode_lib->vba.Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4262
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4263
locals->RequiresFEC[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4264
locals->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4265
dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4266
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4268
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4269
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4270
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4271
} else if (mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4272
|| mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4273
if (mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4282
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4283
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4285
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4286
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4287
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4290
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4291
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4293
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4294
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4295
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4296
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4297
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4298
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4299
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4301
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4305
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4306
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4308
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4313
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4314
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4316
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4317
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4318
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4321
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4322
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4324
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4325
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4326
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4327
if (mode_lib->vba.DSCEnabled[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4328
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4329
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4330
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4332
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4336
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4337
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4339
locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4346
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4347
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4349
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4350
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4351
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4354
* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4355
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4357
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4358
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4359
mode_lib->vba.DSCInputBitPerComponent[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4360
if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4361
locals->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4362
if (mode_lib->vba.Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4363
locals->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4365
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4369
locals->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4370
locals->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4372
locals->OutputBppPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4377
locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4383
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4384
if (!mode_lib->vba.skip_dio_check[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4385
&& (locals->OutputBppPerState[i][k] == BPP_INVALID
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4386
|| (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4387
&& mode_lib->vba.Interlace[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4394
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4396
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4397
if ((mode_lib->vba.Output[k] == dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4398
|| mode_lib->vba.Output[k] == dm_edp)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4399
if (mode_lib->vba.OutputFormat[k] == dm_420
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4400
|| mode_lib->vba.OutputFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4406
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4407
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4408
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4414
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4428
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4429
if (locals->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4430
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4446
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4447
if (mode_lib->vba.BlendingAndTiming[k] != k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4449
} else if (locals->RequiresDSC[i][k] == 0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4450
|| locals->RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4452
} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4454
mode_lib->vba.PixelClockBackEnd[k] / 400.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4456
} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4458
} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4460
} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4465
if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4466
|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4469
mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4471
if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4472
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4473
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4475
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4478
mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4482
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4484
mode_lib->vba.OutputFormat[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4486
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4488
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4490
dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4492
mode_lib->vba.OutputFormat[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4493
+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4495
locals->DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4496
locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4498
locals->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4501
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4504
if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4505
locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4515
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4516
if (mode_lib->vba.DCCEnable[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4517
locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4533
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4534
locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4535
locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4536
if (locals->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4537
locals->SwathWidthYThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4538
dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4540
locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4543
/ dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4544
/ locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4546
(dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4547
+ mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4548
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4553
if (locals->MaxSwathHeightC[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4554
mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4555
mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4556
+ mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4557
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4565
locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4566
locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4568
locals->SwathHeightYThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4569
locals->MinSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4570
locals->SwathHeightCThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4571
locals->MinSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4590
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4591
if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4592
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4593
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4594
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4595
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4598
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4599
locals->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4600
locals->Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4601
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4602
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4603
dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4604
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4605
mode_lib->vba.ViewportWidth[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4606
mode_lib->vba.ViewportHeight[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4607
locals->SwathWidthYThisState[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4614
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4616
&locals->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4619
&locals->PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4621
&locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4622
&locals->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4623
&locals->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4624
&locals->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4625
&locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4633
locals->PrefetchLinesC[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4635
mode_lib->vba.VRatio[k]/2,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4636
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4637
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4639
locals->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4640
mode_lib->vba.ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4641
&locals->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4642
&locals->MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4648
locals->PrefetchLinesC[0][0][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4649
locals->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4654
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4655
locals->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4656
locals->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4657
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4658
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4659
dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4660
mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4661
mode_lib->vba.ViewportWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4662
mode_lib->vba.ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4663
locals->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4670
mode_lib->vba.PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4671
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4672
&locals->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4675
&locals->PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4677
&locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4678
&locals->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4679
&locals->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4680
&locals->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4681
&locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4682
&locals->vm_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4683
&locals->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4689
locals->PrefetchLinesY[0][0][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4691
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4692
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4693
mode_lib->vba.Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4695
locals->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4696
mode_lib->vba.ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4697
&locals->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4698
&locals->MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4699
locals->PDEAndMetaPTEBytesPerFrame[0][0][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4701
locals->MetaRowBytes[0][0][k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4702
locals->DPTEBytesPerRow[0][0][k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4706
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4707
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4708
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4709
mode_lib->vba.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4710
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4713
locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4714
locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4717
locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4718
locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4719
&locals->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4720
&locals->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4740
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4741
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4742
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4743
locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4745
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4746
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4747
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4748
mode_lib->vba.WritebackLumaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4749
mode_lib->vba.WritebackLumaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4750
mode_lib->vba.WritebackChromaHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4751
mode_lib->vba.WritebackChromaVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4752
mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4754
locals->WritebackDelay[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4757
if (mode_lib->vba.BlendingAndTiming[m] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4760
locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4774
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4776
if (mode_lib->vba.BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4777
locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4782
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4783
locals->MaximumVStartup[0][0][k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4784
- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4785
mode_lib->vba.MaxMaxVStartup[0][0] = dml_max(mode_lib->vba.MaxMaxVStartup[0][0], locals->MaximumVStartup[0][0][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4799
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4800
CalculatePrefetchSchedulePerPlane(mode_lib, i, j, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4804
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4807
locals->cursor_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4808
locals->cursor_bw_pre[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4809
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4810
locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4811
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4812
locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4813
/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4818
locals->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4819
locals->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4820
locals->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4821
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4824
mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4825
dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4826
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4827
locals->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4828
locals->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4829
locals->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4830
locals->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4831
&locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4832
&locals->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4833
&locals->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4834
&locals->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4835
&locals->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4836
&locals->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4841
locals->UrgentBurstFactorCursor[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4842
locals->UrgentBurstFactorCursorPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4843
locals->UrgentBurstFactorLuma[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4844
locals->UrgentBurstFactorLumaPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4845
locals->UrgentBurstFactorChroma[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4846
locals->UrgentBurstFactorChromaPre[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4850
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4851
* locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4852
* locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4854
+ dml_max3(locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4855
locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4856
* locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4857
+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4858
locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4859
+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4860
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4874
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4875
if (locals->LineTimesForPrefetch[k] < 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4876
|| locals->LinesForMetaPTE[k] >= 32.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4877
|| locals->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4878
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4883
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4884
if (locals->VRatioPreY[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4885
|| locals->VRatioPreC[i][j][k] > 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4886
|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4891
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4892
if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4909
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4911
- dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4912
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4913
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4914
locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4915
+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4916
+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4919
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4921
+ locals->PDEAndMetaPTEBytesPerFrame[0][0][k] + locals->MetaRowBytes[0][0][k] + locals->DPTEBytesPerRow[0][0][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4924
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4936
locals->PDEAndMetaPTEBytesPerFrame[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4937
locals->MetaRowBytes[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4938
locals->DPTEBytesPerRow[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4941
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4942
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4943
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4944
locals->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4945
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4946
locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4947
locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4948
locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4949
locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4950
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4951
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4952
&locals->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4953
&locals->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4956
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4958
locals->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4959
locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4960
+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4961
+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4962
locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4963
* locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4964
* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4965
* locals->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4972
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
4973
if (locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5047
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5048
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5073
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5074
if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5075
|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5084
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5085
if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5086
for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5087
if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5096
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5097
locals->AlignedYPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5098
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5099
locals->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5100
if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5103
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5104
locals->AlignedDCCMetaPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5106
mode_lib->vba.DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5107
mode_lib->vba.ViewportWidth[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5108
64.0 * locals->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5110
locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5112
if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5115
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5116
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5117
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5118
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5119
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5120
locals->AlignedCPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5122
mode_lib->vba.PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5123
mode_lib->vba.ViewportWidth[k] / 2.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5124
locals->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5126
locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5128
if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5213
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5214
mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5215
locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5225
for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5226
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5227
mode_lib->vba.ODMCombineEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5228
locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5230
mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5232
mode_lib->vba.DSCEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5233
locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5234
mode_lib->vba.OutputBpp[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5235
locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5316
unsigned int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5320
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5321
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5322
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5323
mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5328
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5330
+ ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5338
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5339
if (WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5358
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5361
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5362
- (vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5365
dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5366
- (VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5368
EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5369
* (HTotal[k] / PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5372
/ (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5374
if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5375
DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5376
} else if (SwathWidthY[k] > DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5382
if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5384
/ (SwathWidthY[k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5385
} else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5393
SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5394
SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5398
LinesInDETY[k] = (double)DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5399
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5400
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5401
* (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5402
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5403
LinesInDETC = (double)DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5404
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5406
* (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5412
ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5414
+ FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5418
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5421
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5422
ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5427
- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5429
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5433
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5436
if (WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5437
if (WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5439
+ WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5440
* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5441
/ PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5445
2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5446
* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5449
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5450
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5457
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5458
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5461
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5462
if (BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5463
PlaneWithMinActiveDRAMClockChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5466
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5477
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5478
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5479
&& !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5480
&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5483
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5488
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5489
if (BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5506
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5507
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5508
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5509
- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5510
* (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5538
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5543
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5544
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5545
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5546
/ HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5548
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5549
/ DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5551
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5554
if (VRatio[k] / 2 <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5555
DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5556
* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5558
DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5559
/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5563
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5564
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5565
1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5567
1.1 * SwathWidthY[k] / 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5568
* dml_ceil(BytePerPixelDETC[k], 2) / 32.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5571
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5572
* dml_ceil(BytePerPixelDETY[k], 1) / 64.0
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5575
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5576
mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5577
PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5582
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5585
mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5758
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5760
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5761
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5762
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5763
/ HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5765
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5766
/ PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5769
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5770
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5772
if (VRatio[k] / 2 <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5773
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5774
* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5776
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5777
/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5781
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5782
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5783
* DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5785
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5786
/ PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5789
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5790
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5792
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5793
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5794
swath_width_chroma_ub[k] * DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5795
/ (HRatio[k] / 2) / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5797
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5798
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5803
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5804
if (SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5805
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5807
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5809
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5811
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5812
DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5813
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5814
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5815
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5817
if (SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5818
req_per_swath_ub = swath_width_chroma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5819
/ BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5821
req_per_swath_ub = swath_width_chroma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5822
/ BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5824
DisplayPipeRequestDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5825
DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5826
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5827
DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5900
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5902
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5904
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5905
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5906
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5908
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5911
DST_Y_PER_PTE_ROW_NOM_L[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5912
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5914
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5915
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5917
DST_Y_PER_META_ROW_NOM_L[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5921
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5922
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5924
/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5926
/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5927
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5928
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5929
if (SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5930
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5933
- meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5940
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5941
/ PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5942
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5943
* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5944
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5945
* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5947
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5948
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5949
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5953
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5955
if (SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5956
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5957
* PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5959
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5960
* PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5963
(float) dpte_row_width_luma_ub[k] / dpte_group_width_luma,
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5965
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5966
/ PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5967
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5968
* HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5969
time_per_pte_group_flip_luma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5970
DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5971
/ PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5973
if (BytePerPixelDETC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5974
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5975
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5976
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5978
if (SourceScan[k] == dm_horz) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5979
dpte_group_width_chroma = dpte_group_bytes[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5980
/ PTERequestSizeC[k] * PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5982
dpte_group_width_chroma = dpte_group_bytes[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5983
/ PTERequestSizeC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5984
* PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5987
(float) dpte_row_width_chroma_ub[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5990
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5991
* HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5993
time_per_pte_group_vblank_chroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5994
DestinationLinesToRequestRowInVBlank[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5995
/ PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5997
time_per_pte_group_flip_chroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5998
DestinationLinesToRequestRowInImmediateFlip[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
5999
* HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6003
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6004
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6005
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6006
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6007
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6008
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6012
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6013
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6014
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6015
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6017
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6018
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6021
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6025
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6027
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6028
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6031
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6034
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6036
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6037
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6038
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6039
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6042
dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6043
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6048
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6049
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6050
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6051
/ 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6053
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6058
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6059
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6060
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6062
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6065
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6066
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6067
+ dpde0_bytes_per_frame_ub_c[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6068
+ meta_pte_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6069
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6071
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6072
+ meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6077
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6078
/ PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6079
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6080
* HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6081
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6082
* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6083
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6084
* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6087
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6088
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6089
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6090
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6094
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6095
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6096
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6097
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6139
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6141
for (k = 0; k < NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
6143
+ NumberOfDPP[k] * dpte_group_bytes[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1009
if (Tpre_rounded - v->Tno_bw[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1013
+ PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1014
/ (Tpre_rounded - v->Tno_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1018
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]) > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1019
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1022
if (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded > 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1027
v->BytePerPixelC[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1028
(Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1036
swath_width_chroma_ub * v->BytePerPixelC[k]) / (Tpre_rounded -
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1046
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1057
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1068
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1079
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1103
Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1177
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * v->BytePerPixelC[k] * swath_width_chroma_ub / LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1193
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1195
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1226
v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1792
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1819
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1820
if (v->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1823
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1824
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1825
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1826
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1827
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1828
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1829
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1830
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1831
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1836
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1837
if (v->HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1838
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1839
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1841
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1846
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1847
* dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1848
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1850
if ((v->htaps[k] > 6 || v->vtaps[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1851
&& v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1852
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1855
if ((v->SourcePixelFormat[k] != dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1856
&& v->SourcePixelFormat[k] != dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1857
&& v->SourcePixelFormat[k] != dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1858
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1859
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1860
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1862
if (v->HRatioChroma[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1863
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1864
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1866
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1870
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1871
* dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1872
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1874
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1876
< 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1878
* v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1881
v->DPPCLKUsingSingleDPP[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1887
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1888
if (v->BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1890
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1892
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1895
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1896
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1898
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1901
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1904
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1907
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1942
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1943
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1944
/ v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1948
v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1953
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1954
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1956
v->DPPCLK_calculated[k] * 255.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1959
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1960
v->DPPCLK[k] = v->DPPCLK_calculated[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1967
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1969
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1970
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1971
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1972
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1973
&v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1974
&v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1975
&v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1976
&v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1977
&v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1978
&v->BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2013
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2014
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2015
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2016
DTRACE("read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2043
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2044
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2045
v->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2047
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2049
else if (v->OutputFormat[k] == dm_444)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2051
else if (v->OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2055
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2056
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2058
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2059
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2062
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2068
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2069
double BPP = v->OutputBppPerState[k][v->VoltageLevel];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2071
if (v->DSCEnabled[k] && BPP != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2072
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2073
v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2075
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2076
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2077
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2078
v->Output[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2079
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2080
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2081
v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2083
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2084
v->NumberOfDSCSlices[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2085
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2086
v->Output[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2087
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2089
v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2091
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2092
v->NumberOfDSCSlices[k] / 4.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2093
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2094
v->Output[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2095
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2097
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2099
v->DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2103
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2105
if (j != k && v->BlendingAndTiming[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2107
v->DSCDelay[k] = v->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2110
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2121
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2122
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2132
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2133
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2134
v->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2135
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2136
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2137
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2138
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2139
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2140
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2147
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2148
v->DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2149
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2153
&v->dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2154
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2155
&v->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2156
&v->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2157
&v->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2158
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2161
&v->PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2162
&v->PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2163
&v->PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2164
&v->dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2165
&v->meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2167
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2169
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2170
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2171
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2173
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2174
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2175
&v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2176
&v->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2183
v->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2184
v->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2189
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2190
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2191
v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2192
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2193
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2194
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2195
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2196
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2197
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2204
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2205
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2206
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2210
&v->dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2211
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2212
&v->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2213
&v->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2214
&v->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2215
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2216
&v->vm_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2217
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2218
&v->PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2219
&v->PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2220
&v->PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2221
&v->dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2222
&v->meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2224
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2226
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2227
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2228
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2230
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2231
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2232
&v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2233
&v->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2234
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2235
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2237
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2241
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2242
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2243
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2244
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2245
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2248
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2249
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2252
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2253
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2254
&v->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2255
&v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2260
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2262
+ v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2263
if (v->DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2265
+ v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2295
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2296
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2297
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2298
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2299
CalculateWriteBackDelay(v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2300
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2301
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2302
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2303
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2304
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2305
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2306
v->HTotal[k]) / v->DISPCLK;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2308
v->WritebackDelay[v->VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2310
if (v->BlendingAndTiming[j] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2312
v->WritebackDelay[v->VoltageLevel][k] = dml_max(v->WritebackDelay[v->VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2321
v->HTotal[k]) / v->DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2327
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2329
if (v->BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2330
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2332
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2333
v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2337
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2338
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2364
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2367
myPipe.DPPCLK = v->DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2369
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2371
myPipe.DPPPerPlane = v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2372
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2373
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2374
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2375
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2376
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2377
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2378
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2379
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2380
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2381
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2382
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2383
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2385
v->ErrorResult[k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2387
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2389
v->DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2390
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2391
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2392
v->MaxVStartupLines[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2396
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2397
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2398
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2399
v->PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2400
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2401
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2402
v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2403
v->MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2404
v->PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2405
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2406
v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2407
v->MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2408
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2409
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2410
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2411
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2413
&v->DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2414
&v->PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2415
&v->DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2416
&v->DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2417
&v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2418
&v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2419
&v->RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2420
&v->RequiredPrefetchPixDataBWChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2421
&v->NotEnoughTimeForDynamicMetadata[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2422
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2423
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2424
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2425
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2426
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2427
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2429
int x = v->BlendingAndTiming[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2430
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2431
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[x];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2432
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2433
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2435
v->MaxVStartupLines[x] = v->MaxVStartupLines[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2436
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2443
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2444
v->cursor_bw[k] = v->NumberOfCursors[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2445
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2447
/ (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2448
* v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2449
v->cursor_bw_pre[k] = v->NumberOfCursors[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2450
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2452
/ (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2453
* v->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2456
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2457
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2459
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2460
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2461
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2464
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2465
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2466
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2467
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2468
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2469
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2470
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2471
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2472
&v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2473
&v->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2474
&v->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2475
&v->NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2478
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2479
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2481
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2482
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2483
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2486
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2487
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2488
v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2489
v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2490
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2491
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2492
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2493
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2494
&v->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2495
&v->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2496
&v->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2497
&v->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2500
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2501
v->ReadBandwidthPlaneLuma[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2502
v->UrgentBurstFactorLuma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2503
v->ReadBandwidthPlaneChroma[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2504
v->UrgentBurstFactorChroma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2505
v->cursor_bw[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2506
v->UrgentBurstFactorCursor[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2507
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2508
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2509
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2510
v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2513
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2514
v->ReadBandwidthPlaneLuma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2515
v->ReadBandwidthPlaneChroma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2516
v->cursor_bw[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2517
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2518
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2520
if (v->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2522
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2524
if (v->NoUrgentLatencyHiding[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2527
if (v->NoUrgentLatencyHidingPre[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2547
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2551
v->ReadBandwidthPlaneLuma[k] * v->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2552
+ v->ReadBandwidthPlaneChroma[k] * v->UrgentBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2553
+ v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2554
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2555
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2556
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2560
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2561
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2563
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2575
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2576
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2577
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2580
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2581
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2582
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2583
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2584
v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2585
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2586
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2587
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2588
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2589
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2590
&v->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2591
&v->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2592
&v->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2593
&v->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2597
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2599
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2600
v->DPPPerPlane[k] * v->final_flip_bw[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2601
v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2602
v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2603
v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2604
v->DPPPerPlane[k] * (v->final_flip_bw[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2605
v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2606
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2607
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2610
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2611
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2612
v->DPPPerPlane[k] * (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2622
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2623
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2631
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2632
if (v->ErrorResult[k] || v->NotEnoughTimeForDynamicMetadata[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2708
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2709
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2710
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2711
v->ThisVStartup = v->VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2714
if (v->BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2719
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2720
v->ThisVStartup * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2722
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2840
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2842
v->AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2843
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2844
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2850
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2851
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2852
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2856
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2857
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2858
v->MinTTUVBlank[k] = v->UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2860
if (!v->DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2861
v->MinTTUVBlank[k] = v->TCalc
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2862
+ v->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2867
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2868
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2869
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2870
v->SurfaceWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2871
v->SurfaceWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2872
v->SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2873
v->SurfaceHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2875
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2876
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2877
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2878
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2879
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2880
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2881
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2882
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2883
&v->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2884
&v->DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2885
&v->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2886
&v->DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2887
&v->DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2888
&v->DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2894
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2896
+ v->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2897
+ v->ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2904
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2905
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2906
double margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2907
/ v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2977
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2979
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2982
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2983
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2984
&BytePerPixY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2985
&BytePerPixC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2986
&BytePerPixDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2987
&BytePerPixDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2988
&Read256BytesBlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2989
&Read256BytesBlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2990
&Read256BytesBlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2991
&Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3452
unsigned int j, k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3474
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3475
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3476
&& ((v->SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3477
&& v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3478
&& v->SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3479
&& v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3480
&& v->SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3481
&& v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3482
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3483
|| v->HRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3484
|| v->htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3485
|| v->VRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3486
|| v->vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3488
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3489
|| v->htaps[k] < 1.0 || v->htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3490
|| (v->htaps[k] > 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3491
&& (v->htaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3492
|| v->HRatio[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3493
|| v->VRatio[k] > v->MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3494
|| v->HRatio[k] > v->htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3495
|| v->VRatio[k] > v->vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3496
|| (v->SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3497
&& v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3498
&& v->SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3499
&& v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3500
&& v->SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3501
&& v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3502
&& (v->VTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3503
|| v->VTAPsChroma[k] > 8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3504
|| v->HTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3505
|| v->HTAPsChroma[k] > 8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3506
|| (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3507
|| v->HRatioChroma[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3508
|| v->VRatioChroma[k] > v->MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3509
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3510
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3517
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3518
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3519
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t || v->SurfaceTiling[k] == dm_sw_64kb_d_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3520
&& !(v->SourcePixelFormat[k] == dm_444_64))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3526
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3528
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3529
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3530
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3531
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3532
&v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3533
&v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3534
&v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3535
&v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3536
&v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3537
&v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3539
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3540
if (v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3541
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3542
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3544
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3545
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3548
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3549
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3550
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3552
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3553
if (v->WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3554
&& v->WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3555
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3556
* v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3557
/ (v->WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3558
* v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3559
/ v->PixelClock[k]) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3560
} else if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3561
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3562
* v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3563
/ (v->WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3564
* v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3565
/ v->PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3567
v->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3574
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3575
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3578
if (v->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3584
if (v->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3596
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3597
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3619
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3620
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3621
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3622
|| v->WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3624
|| v->WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3626
|| v->WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3628
|| v->WritebackHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3630
|| v->WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3632
|| v->WritebackHRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3633
> v->WritebackHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3634
|| v->WritebackVRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3635
> v->WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3636
|| (v->WritebackHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3637
&& ((v->WritebackHTaps[k] % 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3641
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3649
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3650
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3653
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3654
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3655
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3656
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3657
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3658
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3659
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3660
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3661
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3665
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3666
if (v->HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3667
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3669
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3671
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3672
v->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3673
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3674
* dml_max3(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3675
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3676
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3679
if (v->HRatioChroma[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3680
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3681
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3683
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3685
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] * dml_max5(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3686
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3687
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3688
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3690
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3691
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3692
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3696
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3700
if (v->SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3702
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3708
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3713
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3714
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3715
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3718
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3719
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3721
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3722
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3771
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3772
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3776
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3778
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3782
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3784
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3788
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3792
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3795
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3799
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3802
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3805
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3808
if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3809
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3810
if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3811
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3814
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3818
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3819
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3820
if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3821
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3824
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3828
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3829
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3830
v->NoOfDPP[i][j][k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3831
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3832
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3833
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3834
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3835
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3837
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= v->MaxDppclkRoundedDownToDFSGranularity
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3838
&& v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3839
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3840
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3841
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3843
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3844
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3845
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3848
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3855
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3856
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3857
if (v->NoOfDPP[i][j][k] == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3866
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3867
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3868
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3869
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3870
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3884
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3885
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3886
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3887
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3888
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3889
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3891
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3892
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3893
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3896
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3899
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3902
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3908
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3909
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3933
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3934
if (!(v->DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3935
|| v->DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3936
|| v->DSCInputBitPerComponent[k] == 8.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3942
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3943
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3944
if (v->PixelClockBackEnd[k] > 3200) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3945
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3946
} else if (v->PixelClockBackEnd[k] > 1360) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3947
v->NumberOfDSCSlices[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3948
} else if (v->PixelClockBackEnd[k] > 680) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3949
v->NumberOfDSCSlices[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3950
} else if (v->PixelClockBackEnd[k] > 340) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3951
v->NumberOfDSCSlices[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3953
v->NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3956
v->NumberOfDSCSlices[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3961
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3962
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3963
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3964
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3965
if (v->Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3966
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3967
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3968
v->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3971
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3972
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3973
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3974
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3976
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3977
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3978
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3979
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3980
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3981
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3982
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3983
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3984
if (v->DSCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3985
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3987
if (v->Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3988
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3990
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3993
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3995
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4002
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4003
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4004
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4005
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4006
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4008
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4009
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4010
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4011
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4012
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4013
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4014
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4015
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4022
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4023
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4024
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4025
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4026
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4028
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4029
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4030
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4031
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4032
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4033
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4034
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4035
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4042
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4043
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4044
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4045
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4046
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4048
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4049
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4050
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4051
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4052
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4053
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4054
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4055
if (v->Outbpp == BPP_INVALID && v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4057
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4059
if (v->Output[k] == dm_dp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4060
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4064
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4065
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4066
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4067
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4068
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4070
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4071
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4072
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4073
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4074
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4075
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4076
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4078
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4084
v->OutputBppPerState[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4090
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4091
if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4092
&& (v->OutputBppPerState[i][k] == 0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4093
|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4101
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4102
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4103
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4114
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4115
if (v->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4116
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4118
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4132
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4133
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4136
v->BPP = v->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4138
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4139
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4140
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4141
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4143
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4144
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4145
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4146
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4147
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4148
v->DSCDelayPerState[i][k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4150
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4152
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4153
v->NumberOfDSCSlices[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4154
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4155
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4157
v->DSCDelayPerState[i][k] = 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4159
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4161
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4162
v->NumberOfDSCSlices[k] / 4,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4163
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4164
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4166
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4168
v->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4171
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4173
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4174
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4184
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4185
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4186
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4187
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4230
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4231
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4232
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4233
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4234
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4235
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4236
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4237
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4238
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4243
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4244
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4249
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4250
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4251
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4252
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4253
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4254
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4255
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4256
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4257
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4261
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4262
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4263
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4267
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4268
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4269
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4271
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4281
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4282
v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4283
v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4284
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4285
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4286
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4287
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4288
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4289
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4296
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4298
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4301
&v->PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4303
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4307
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4316
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4318
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4319
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4320
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4322
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4323
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4324
&v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4325
&v->MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4332
v->PrefetchLinesC[i][j][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4333
v->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4337
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4338
v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4339
v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4340
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4341
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4342
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4343
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4344
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4345
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4352
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4353
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4354
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4357
&v->PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4359
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4363
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4365
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4371
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4373
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4374
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4375
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4377
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4378
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4379
&v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4380
&v->MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4381
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4382
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4383
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4387
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4388
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4389
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4390
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4391
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4394
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4395
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4398
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4399
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4400
&v->meta_row_bandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4401
&v->dpte_row_bandwidth[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4412
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4414
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4415
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4417
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4418
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4419
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4422
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4423
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4424
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4425
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4426
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4427
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4428
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4429
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4430
&v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4431
&v->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4432
&v->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4433
&NotUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4437
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4438
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4443
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4444
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4445
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4446
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4453
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4454
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4455
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4456
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4457
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4487
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4488
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4489
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4490
v->WritebackDelayTime[k] = v->WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4492
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4493
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4494
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4495
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4496
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4497
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4498
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4499
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4501
v->WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4504
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4505
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4506
v->WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4521
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4523
if (v->BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4524
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4529
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4530
v->MaximumVStartup[i][j][k] = v->VTotal[k] - v->VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4531
- dml_max(1.0, dml_ceil(1.0 * v->WritebackDelayTime[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4532
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4597
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4598
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4629
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4630
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4631
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4632
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4633
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4634
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4635
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4636
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4637
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4638
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4639
v->ODMCombineEnabled[k] = v->ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4668
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4671
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4673
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4675
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4676
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4677
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4678
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4679
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4680
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4681
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4682
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4683
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4684
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4685
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4686
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4687
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4689
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4691
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4693
v->DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4694
v->SwathWidthYThisState[k] / v->HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4695
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4696
v->MaximumVStartup[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4700
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4701
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4702
v->DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4703
v->PrefetchLinesY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4704
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4705
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4706
v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4707
v->MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4708
v->PrefetchLinesC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4709
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4710
v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4711
v->MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4712
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4713
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4714
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4715
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4717
&v->LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4718
&v->PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4719
&v->LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4720
&v->LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4721
&v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4722
&v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4723
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4724
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4725
&v->NoTimeForDynamicMetadata[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4728
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4730
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4731
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4733
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4734
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4735
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4738
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4739
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4740
v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4741
v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4742
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4743
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4744
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4745
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4746
&v->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4747
&v->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4748
&v->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4749
&v->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4753
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4754
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4755
* v->VRatioPreY[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4759
v->VActivePixelBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4760
v->VActiveCursorBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4761
+ v->NoOfDPP[i][j][k] * (v->meta_row_bandwidth[i][j][k] + v->dpte_row_bandwidth[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4762
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4763
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4764
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4765
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4766
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4767
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4771
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4772
if (v->NoUrgentLatencyHidingPre[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4782
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4783
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4784
|| v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4790
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4791
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4797
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4798
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4803
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4804
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4811
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4814
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4815
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4816
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4817
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4818
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4819
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4822
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4823
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4824
+ v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4827
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4839
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4840
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4841
v->DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4844
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4845
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4846
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4847
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4848
v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4849
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4850
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4851
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4852
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4853
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4854
&v->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4855
&v->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4856
&v->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4857
&v->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4860
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4863
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4864
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4865
+ v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4866
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4867
* (v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4868
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4869
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4870
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4871
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4872
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4878
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4879
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4964
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4965
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4974
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4975
if (v->CursorWidth[k][0] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4976
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4984
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4985
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4986
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4987
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4989
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4991
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4992
&& v->SourcePixelFormat[k] != dm_rgbe && v->SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4993
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4994
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4995
v->AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]), 64.0 * v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4997
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5000
v->AlignedCPitch[k] = v->PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5001
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5003
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] || v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5004
|| v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5009
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5010
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5013
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5014
&& v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5015
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] || v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5056
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5057
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5058
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5145
unsigned int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5149
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5150
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5151
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5152
mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5161
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5162
if (WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5179
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5181
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5183
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5185
EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5187
EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5189
LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5190
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5191
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5192
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5193
LinesInDETC = mode_lib->vba.DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5194
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5195
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5201
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5204
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5207
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5208
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5211
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5213
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5215
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5218
if (WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5220
WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5221
if (WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5228
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5234
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5235
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < mode_lib->vba.MinActiveDRAMClockChangeMargin) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5236
mode_lib->vba.MinActiveDRAMClockChangeMargin = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5237
if (BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5238
PlaneWithMinActiveDRAMClockChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5241
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5252
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5253
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5254
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5259
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5260
if (BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5274
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5275
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5276
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5277
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5309
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5313
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5315
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5316
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5318
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5320
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5323
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5324
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5326
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5330
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5331
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(1.1 * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma, 1.1 * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5333
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5335
mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(mode_lib->vba.DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5339
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5340
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5345
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5346
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5461
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5463
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5464
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5465
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5467
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5470
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5471
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5473
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5474
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5476
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5480
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5481
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5483
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5486
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5487
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5489
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5490
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5492
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5497
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5498
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5499
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5501
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5503
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5504
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5505
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5506
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5507
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5509
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5510
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5512
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5514
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5515
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5519
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5521
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5522
if (NumberOfCursors[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5523
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5524
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5526
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5528
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5529
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5531
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5534
CursorRequestDeliveryTime[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5535
CursorRequestDeliveryTimePrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5607
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5609
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5610
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5611
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5612
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5614
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5616
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5617
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5618
DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5620
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5624
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5625
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5626
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5627
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5628
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5629
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5630
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5631
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5633
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5640
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5641
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5642
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5643
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5644
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5645
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5646
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5648
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5649
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5650
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5651
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5652
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5653
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5655
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5662
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5663
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5664
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5667
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5668
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5669
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5670
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5671
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5672
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5676
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5678
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5679
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5681
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5683
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5684
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5685
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5686
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5687
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5688
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5689
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5690
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5692
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5693
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5695
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5697
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5698
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5699
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5700
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5703
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5704
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5705
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5706
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5707
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5708
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5737
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5739
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5740
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5741
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5742
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5743
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5744
/ (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5745
/ (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5747
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5748
/ (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5752
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5753
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5754
/ (double) (vm_group_bytes[k]), 1) + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5755
/ (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5757
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5758
/ (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5761
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5762
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5763
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5764
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5765
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5767
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5768
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5773
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5774
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5775
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5777
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5781
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5782
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5783
+ meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5785
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5788
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5789
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5790
+ dpde0_bytes_per_frame_ub_c[k] / 64 + meta_pte_bytes_per_frame_ub_l[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5791
/ 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5793
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5794
+ meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5799
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5801
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5803
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5805
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5809
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5810
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5811
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5812
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5816
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5817
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5818
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5819
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5881
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5883
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5884
LinesInDETY[k] = DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5885
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5886
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5896
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5897
if (FullDETBufferingTimeY[k] < StutterPeriod) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5898
StutterPeriod = FullDETBufferingTimeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5899
FrameTimeForMinFullDETBufferingTime = VTotal[k] * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5900
BytePerPixelYCriticalPlane = BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5901
SwathWidthYCriticalPlane = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5902
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5903
- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5909
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5910
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5911
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5912
|| (SourceScan[k] != dm_vert
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5913
&& BlockHeight256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5914
|| DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5919
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(DCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5921
if (ReadBandwidthPlaneChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5922
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5923
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5924
|| DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5929
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneChroma[k] / dml_min(DCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5932
AverageReadBandwidth = AverageReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5934
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5944
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5945
if (WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5962
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5964
VBlankTime = (VTotal[k] - VActive[k]) * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6029
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6063
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6064
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6065
|| SourcePixelFormat[k] == dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6066
|| SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6067
|| SourcePixelFormat[k] == dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6068
|| SourcePixelFormat[k] == dm_rgbe)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6069
if (SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6070
|| (SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6071
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6072
&& SourceScan[k] != dm_vert)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6073
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6074
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6075
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6077
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6079
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6081
if (SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6082
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6083
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6084
} else if (SourcePixelFormat[k] == dm_rgbe_alpha
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6085
&& SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6086
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6087
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6088
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6089
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6090
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6091
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6092
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6093
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6095
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6096
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6100
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6101
* MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6102
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6104
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6108
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6109
* MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6110
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6112
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6119
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6120
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6126
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6127
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6133
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6134
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6138
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6139
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6144
if (SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6145
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6146
DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6148
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6149
DETBufferSizeC[k] = DETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6151
DETBufferSizeY[k] = DETBufferSizeInKByte * 1024 * 2 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6152
DETBufferSizeC[k] = DETBufferSizeInKByte * 1024 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6157
|| SwathWidth[k] > MaximumSwathWidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6158
|| (SwathHeightC[k] > 0
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6159
&& SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6161
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6163
ViewportSizeSupportPerPlane[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6199
unsigned int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6205
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6208
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6209
SwathWidthSingleDPPY[k] = ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6211
SwathWidthSingleDPPY[k] = ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6214
MainPlaneODMCombine = ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6216
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6222
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6224
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6225
} else if (DPPPerPlane[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6226
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6228
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6231
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6232
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6233
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6235
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6236
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6240
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6241
SwathWidthC[k] = SwathWidthSingleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6244
surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6245
surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6247
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6248
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6249
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6250
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6251
Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6252
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6253
surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6254
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6255
Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6257
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6260
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6261
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6262
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (long) dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6263
Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6264
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6265
surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6266
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c, (long) dml_ceil(SwathWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6267
Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6269
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6333
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6352
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6353
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6387
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6410
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6412
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6415
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6416
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6432
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6437
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6438
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6439
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6440
/ NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * v->DPTEBytesPerRow[i][j][k] / PTEEfficiency
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6441
/ NormalEfficiency / v->ReturnBusWidth + 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6442
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6443
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6444
DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6446
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6447
: v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6451
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6452
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6455
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6456
+ NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6459
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6461
if (v->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6470
v->RequiredDPPCLK[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6473
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6474
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6475
v->VTotal[k] - v->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6476
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6477
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6478
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6484
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TsetupPipe
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6485
- TdmbfPipe - TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6487
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(DCFCLKRequiredForPeakBandwidthPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6490
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6495
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6496
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6500
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6502
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6503
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6507
/ (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6508
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
786
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
84
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
871
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
872
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
885
v->Tdmdl[k] = TWait + Tvm_trips + trip_to_mem;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
887
v->Tdmdl[k] = TWait + UrgentExtraLatency;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
890
if (v->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
891
if (VStartup * LineTime < Tsetup + v->Tdmdl[k] + Tdmbf + Tdmec + Tdmsks) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
899
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
905
v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
919
v->DSTXAfterScaler[k] = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
922
v->DSTXAfterScaler[k] = v->DSTXAfterScaler[k] + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
924
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
925
v->DSTYAfterScaler[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
927
v->DSTYAfterScaler[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
929
DSTTotalPixelsAfterScaler = v->DSTYAfterScaler[k] * myPipe->HTotal + v->DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
930
v->DSTYAfterScaler[k] = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
931
v->DSTXAfterScaler[k] = DSTTotalPixelsAfterScaler - ((double) (v->DSTYAfterScaler[k] * myPipe->HTotal));
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
942
v->Tno_bw[k] = UrgentExtraLatency + trip_to_mem * ((v->GPUVMMaxPageTableLevels - 2) - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
944
v->Tno_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
946
v->Tno_bw[k] = LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
948
v->Tno_bw[k] = LineTime / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
950
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
951
- (v->DSTYAfterScaler[k] + v->DSTXAfterScaler[k] / myPipe->HTotal);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
957
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k]) / Tsw_oto;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
960
Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
992
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", v->Tdmdl_vm[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
993
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
994
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", v->DSTXAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
995
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)v->DSTYAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1184
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1186
for (k = 0; k < num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1187
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
1188
pipe_index_in_combine[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1990
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2022
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2023
if (v->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2027
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2028
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2029
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2030
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2031
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2032
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2033
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2034
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2035
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2041
if (v->HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2042
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2044
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2046
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2049
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2052
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2054
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2055
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2058
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2059
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2060
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2061
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2063
if (v->HRatioChroma[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2064
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2066
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2068
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2070
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2072
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2073
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2076
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2077
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2080
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2084
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2085
if (v->BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2087
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2090
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2094
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2095
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2098
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2102
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2106
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2109
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2132
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2133
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2134
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2137
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2138
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2139
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2142
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2143
v->DPPCLK[k] = v->DPPCLK_calculated[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2152
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2153
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2154
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2155
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2156
&v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2157
&v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2158
&v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2159
&v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2160
&v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2161
&v->BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2195
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2196
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2197
* v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2198
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2199
* v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2200
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2226
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2227
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2228
v->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2230
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2232
else if (v->OutputFormat[k] == dm_444)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2234
else if (v->OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2238
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2239
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2241
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2242
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2245
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2251
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2252
double BPP = v->OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2254
if (v->DSCEnabled[k] && BPP != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2255
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2256
v->DSCDelay[k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2257
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2259
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2260
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2261
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2262
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2263
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2264
v->DSCDelay[k] = 2
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2266
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2268
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2269
v->NumberOfDSCSlices[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2270
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2271
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2273
v->DSCDelay[k] = 4
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2275
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2278
v->NumberOfDSCSlices[k] / 4.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2279
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2282
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2284
v->DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2288
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2290
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2291
v->DSCDelay[k] = v->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2294
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2304
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2305
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2306
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2316
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2317
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2318
v->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2319
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2320
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2321
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2322
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2323
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2324
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2331
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2332
v->DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2333
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2337
&v->dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2338
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2339
&v->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2340
&v->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2341
&v->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2342
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2345
&v->PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2346
&v->PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2347
&v->PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2348
&v->dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2349
&v->meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2351
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2353
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2354
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2355
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2357
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2358
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2359
&v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2360
&v->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2367
v->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2368
v->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2373
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2374
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2375
v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2376
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2377
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2378
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2379
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2380
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2381
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2388
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2389
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2390
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2394
&v->dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2395
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2396
&v->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2397
&v->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2398
&v->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2399
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2400
&v->vm_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2401
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2402
&v->PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2403
&v->PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2404
&v->PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2405
&v->dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2406
&v->meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2408
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2410
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2411
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2412
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2414
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2415
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2416
&v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2417
&v->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2418
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2419
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2420
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2424
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2425
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2426
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2427
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2428
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2431
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2432
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2435
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2436
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2437
&v->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2438
&v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2443
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2444
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2445
if (v->DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2446
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2447
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2448
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2501
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2502
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2503
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2504
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2506
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2507
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2508
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2509
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2510
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2511
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2512
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2513
v->HTotal[k]) / v->DISPCLK;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2515
v->WritebackDelay[v->VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2517
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2518
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2519
v->WritebackDelay[v->VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2529
v->HTotal[k]) / v->DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2535
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2537
if (v->BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2538
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2540
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2541
v->MaxVStartupLines[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2542
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2543
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2544
v->VTotal[k] - v->VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2548
(double) v->WritebackDelay[v->VoltageLevel][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2549
/ (v->HTotal[k] / v->PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
255
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2551
if (v->MaxVStartupLines[k] > 1023)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2552
v->MaxVStartupLines[k] = 1023;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2555
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2556
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2557
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2562
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2563
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2592
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2595
myPipe.DPPCLK = v->DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2597
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2599
myPipe.DPPPerPlane = v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2600
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2601
myPipe.VRatio = v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2602
myPipe.VRatioChroma = v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2603
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2604
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2605
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2606
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2607
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2608
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2609
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2610
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2611
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2612
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2613
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2614
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2615
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2616
myPipe.BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2617
myPipe.BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2619
v->ErrorResult[k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2623
v->DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2629
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2630
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2632
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2633
v->MaxVStartupLines[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2639
v->DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2641
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2642
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2646
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2647
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2648
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2649
v->PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2650
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2651
v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2652
v->MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2653
v->PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2654
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2655
v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2656
v->MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2657
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2658
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2659
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2660
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2662
&v->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2663
&v->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2664
&v->DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2665
&v->PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2666
&v->DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2667
&v->DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2668
&v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2669
&v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2670
&v->RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2671
&v->RequiredPrefetchPixDataBWChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2672
&v->NotEnoughTimeForDynamicMetadata[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2673
&v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2674
&v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2675
&v->Tdmdl_vm[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2676
&v->Tdmdl[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2677
&v->TSetup[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2678
&v->VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2679
&v->VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2680
&v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2683
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2685
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2691
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2692
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2693
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2694
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2695
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2698
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2699
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2700
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2701
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2702
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2705
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2706
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2707
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2708
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2709
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2710
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2711
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2712
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2713
&v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2714
&v->UrgBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2715
&v->UrgBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2716
&v->NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2719
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2720
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2721
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2722
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2723
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2726
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2727
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2728
v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2729
v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2730
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2731
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2732
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2733
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2734
&v->UrgBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2735
&v->UrgBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2736
&v->UrgBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2737
&v->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2741
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2742
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2743
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2744
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2745
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2746
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2747
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2748
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2749
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2753
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2754
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2755
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2756
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2757
+ v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2760
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2761
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2762
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2763
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2764
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2766
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2767
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2769
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2770
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2771
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2772
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2773
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2774
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2775
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2776
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2777
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2778
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2781
if (v->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2784
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2787
if (v->NoUrgentLatencyHiding[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2790
if (v->NoUrgentLatencyHidingPre[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2816
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2817
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2825
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2828
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2829
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2830
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2831
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2832
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2833
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2834
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2838
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2840
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2842
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2845
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2849
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2850
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2851
v->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2856
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2859
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2860
v->DPPPerPlane[k] * v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2861
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2862
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2863
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2864
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2865
* (v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2866
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2867
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2868
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2871
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2872
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2873
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2874
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2875
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2876
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2888
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2889
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2892
__func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2961
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2962
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2963
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2965
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2967
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3082
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3084
v->AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3085
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3086
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3090
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3091
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3092
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3094
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3095
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3096
v->MinTTUVBlank[k] = v->UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3098
if (!v->DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3099
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3104
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3105
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3106
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3107
v->SurfaceWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3108
v->SurfaceWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3109
v->SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3110
v->SurfaceHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3111
v->DETBufferSizeInKByte[k] * 1024,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3112
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3113
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3114
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3115
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3116
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3117
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3118
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3119
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3120
&v->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3121
&v->DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3122
&v->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3123
&v->DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3124
&v->DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3125
&v->DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3129
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3131
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3133
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3136
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3139
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3140
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3141
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3142
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3145
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3146
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3147
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3150
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3152
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3153
- v->VFrontPorch[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3154
+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3155
+ dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3157
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3159
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3161
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3162
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3163
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3165
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3168
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3169
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3170
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3171
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3172
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3173
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3174
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3175
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3176
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3177
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3178
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3187
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3188
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3189
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3190
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3191
} else if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3192
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3193
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3200
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3201
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3286
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3288
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3291
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3292
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3293
&BytePerPixY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3294
&BytePerPixC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3295
&BytePerPixDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3296
&BytePerPixDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3297
&Read256BytesBlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3298
&Read256BytesBlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3299
&Read256BytesBlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3300
&Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3484
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3498
double LineTime = v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3506
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3512
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3519
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3520
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3529
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3532
v->final_flip_bw[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3533
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3534
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3535
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3536
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3538
v->final_flip_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3541
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3542
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3543
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3544
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3545
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3548
v->dpte_row_height[k] * LineTime / v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3549
v->meta_row_height[k] * LineTime / v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3550
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3551
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3554
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3555
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3556
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3557
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3559
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3563
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3565
v->ImmediateFlipSupportedForPipe[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3567
v->ImmediateFlipSupportedForPipe[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3571
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3572
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3576
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3678
unsigned k)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3683
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3685
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3687
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3688
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3689
myPipe.VRatio = mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3690
myPipe.VRatioChroma = mode_lib->vba.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3692
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3693
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3694
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3695
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3696
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3697
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3698
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3699
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3700
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3701
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3702
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3703
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3704
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3705
myPipe.BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3706
myPipe.BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3708
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3712
v->DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3718
v->SwathWidthYThisState[k] / v->HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3719
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3721
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3722
v->MaximumVStartup[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3728
v->DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3730
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3731
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3735
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3736
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3737
v->DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3738
v->PrefetchLinesY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3739
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3740
v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3741
v->MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3742
v->PrefetchLinesC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3743
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3744
v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3745
v->MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3746
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3747
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3748
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3749
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3751
&v->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3752
&v->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3753
&v->LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3754
&v->PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3755
&v->LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3756
&v->LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3757
&v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3758
&v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3759
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3760
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3761
&v->NoTimeForDynamicMetadata[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3762
&v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3763
&v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3764
&v->dummy7[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3765
&v->dummy8[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3766
&v->dummy13[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3767
&v->VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3768
&v->VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3769
&v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3790
unsigned int k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3811
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3812
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3813
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3814
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3815
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3816
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3817
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3819
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3820
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3821
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3822
|| v->VRatio[k] > v->vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3823
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3824
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3825
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3826
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3827
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3828
|| v->HRatioChroma[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3829
|| v->VRatioChroma[k] > v->MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3830
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3831
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3838
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3839
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3840
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3841
|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3847
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3849
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3850
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3851
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3852
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3853
&v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3854
&v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3855
&v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3856
&v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3857
&v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3858
&v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3860
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3861
if (v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3862
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3863
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3865
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3866
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3869
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3870
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3871
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3872
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3873
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3875
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3876
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3877
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3878
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3879
} else if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3880
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3881
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3883
v->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3890
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3891
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3899
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3900
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3912
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3913
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3914
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3915
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3916
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3917
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3918
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3919
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3920
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3923
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3932
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3936
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3937
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3938
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3939
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3940
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3941
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3942
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3943
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3944
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3948
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3949
if (v->HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3950
v->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3952
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3954
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3956
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3957
v->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3958
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3960
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3961
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3963
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3964
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3967
if (v->HRatioChroma[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3968
v->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3970
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3972
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3974
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3976
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3977
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3978
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3979
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3981
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3982
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3983
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3987
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3991
if (v->SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3993
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3995
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4001
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4006
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4007
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4008
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4011
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4012
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4014
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4015
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4065
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4066
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4071
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4074
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4079
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4082
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4087
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4092
|| !(v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4093
v->Output[k] == dm_dp2p0 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4094
v->Output[k] == dm_edp)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4095
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4098
if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4101
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4105
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4108
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4111
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4114
if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4115
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4116
if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4117
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4120
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4124
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4125
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4126
if (v->Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4128
} else if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4129
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4132
if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4135
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4139
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4140
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4141
v->NoOfDPP[i][j][k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4142
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4143
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4144
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4145
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4146
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4148
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4149
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4150
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4151
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4152
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4154
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4155
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4156
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4159
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4164
if (mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[k] > DCN3_15_MAX_DET_SIZE && v->NoOfDPP[i][j][k] < 2) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4165
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4166
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4171
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4172
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4173
if (v->NoOfDPP[i][j][k] == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4175
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4176
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4188
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4189
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4190
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4191
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4192
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4207
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4208
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4209
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4210
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4211
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4212
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4215
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4216
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4217
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4222
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4225
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4228
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4235
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4236
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4260
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4261
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4262
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4268
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4269
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4270
if (v->PixelClockBackEnd[k] > 3200) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4271
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4272
} else if (v->PixelClockBackEnd[k] > 1360) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4273
v->NumberOfDSCSlices[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4274
} else if (v->PixelClockBackEnd[k] > 680) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4275
v->NumberOfDSCSlices[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4276
} else if (v->PixelClockBackEnd[k] > 340) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4277
v->NumberOfDSCSlices[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4279
v->NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4282
v->NumberOfDSCSlices[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4287
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4288
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4289
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4290
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4291
if (v->Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4292
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4293
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4294
v->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4297
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4298
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4299
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4300
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4302
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4303
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4304
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4305
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4306
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4307
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4308
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4309
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4310
if (v->DSCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4311
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4313
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4314
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4316
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4319
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4321
if (v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4322
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4324
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4327
if (v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4329
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4330
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4333
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4334
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4335
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4336
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4337
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4339
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4340
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4341
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4342
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4343
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4344
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4345
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4346
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4347
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4348
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4352
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4353
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4354
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4355
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4356
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4358
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4359
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4360
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4361
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4362
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4363
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4364
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4366
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4371
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4372
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4375
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4376
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4377
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4378
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4379
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4381
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4382
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4383
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4384
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4385
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4386
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4387
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4388
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4389
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4390
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4394
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4395
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4396
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4397
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4398
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4400
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4401
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4402
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4403
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4404
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4405
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4406
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4408
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4413
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4414
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4417
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4418
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4419
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4420
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4421
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4423
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4424
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4425
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4426
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4427
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4428
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4429
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4430
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4431
v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4432
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4436
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4437
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4438
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4439
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4440
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4442
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4443
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4444
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4445
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4446
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4447
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4448
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4450
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4459
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4460
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4461
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4462
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4463
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4465
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4466
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4467
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4468
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4469
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4470
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4471
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4472
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4479
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4480
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4481
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4482
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4483
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4485
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4486
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4487
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4488
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4489
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4490
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4491
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4492
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4499
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4500
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4501
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4502
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4503
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4505
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4506
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4507
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4508
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4509
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4510
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4511
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4512
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4519
v->OutputBppPerState[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4526
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4527
if (v->BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4528
&& (v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4529
v->Output[k] == dm_edp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4530
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4537
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4538
if (v->BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4539
&& (v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4540
v->Output[k] == dm_edp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4541
v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4542
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4545
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4554
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4555
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4556
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4557
|| v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4568
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4569
if (v->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4570
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4572
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4586
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4587
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4590
v->BPP = v->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4592
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4593
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4594
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4595
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4597
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4598
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4599
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4600
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4601
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4602
v->DSCDelayPerState[i][k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4604
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4606
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4607
v->NumberOfDSCSlices[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4608
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4609
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4611
v->DSCDelayPerState[i][k] = 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4613
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4615
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4616
v->NumberOfDSCSlices[k] / 4,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4617
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4618
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4620
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4622
v->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4625
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4627
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4628
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4638
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4639
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4640
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4641
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4708
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4709
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4710
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4711
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4712
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4713
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4714
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4715
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4716
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4722
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4723
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4730
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4731
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4732
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4733
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4734
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4735
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4736
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4737
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4738
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4742
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4743
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4744
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4748
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4749
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4750
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4752
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4753
&& v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4764
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4765
v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4766
v->Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4767
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4768
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4769
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4770
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4771
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4772
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4779
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4781
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4784
&v->PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4786
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4790
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4799
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4801
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4802
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4803
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4805
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4806
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4807
&v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4808
&v->MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4815
v->PrefetchLinesC[i][j][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4816
v->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4820
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4821
v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4822
v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4823
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4824
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4825
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4826
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4827
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4828
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4835
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4836
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4837
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4840
&v->PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4842
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4846
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4848
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4854
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4856
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4857
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4858
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4860
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4861
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4862
&v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4863
&v->MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4864
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4865
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4866
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4870
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4871
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4872
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4873
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4874
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4877
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4878
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4881
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4882
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4883
&v->meta_row_bandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4884
&v->dpte_row_bandwidth[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4893
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4894
if (v->MetaRowBytes[i][j][k] > 24064)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4906
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4908
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4909
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4910
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4911
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4912
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4915
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4916
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4917
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4918
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4919
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4920
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4921
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4922
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4923
&v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4924
&v->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4925
&v->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4926
&NotUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4930
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4931
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4936
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4937
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4938
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4939
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4946
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4947
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4948
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4949
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4950
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4958
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4959
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4960
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4961
v->WritebackDelayTime[k] = v->WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4963
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4964
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4965
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4966
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4967
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4968
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4969
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4970
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4972
v->WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4975
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4976
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4977
v->WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4992
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4994
if (v->BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4995
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5000
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5001
v->MaximumVStartup[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5002
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5003
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5004
v->VTotal[k] - v->VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5008
1.0 * v->WritebackDelayTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5009
/ (v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5010
/ v->PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5012
if (v->MaximumVStartup[i][j][k] > 1023)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5013
v->MaximumVStartup[i][j][k] = 1023;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5014
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5070
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5071
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5118
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5119
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5120
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5121
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5122
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5123
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5124
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5125
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5126
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5127
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5169
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5172
i, j, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5175
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5177
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5178
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5179
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5180
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5181
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5184
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5185
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5186
v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5187
v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5188
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5189
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5190
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5191
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5192
&v->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5193
&v->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5194
&v->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5195
&v->NotUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5199
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5200
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5201
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5206
v->VActivePixelBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5207
+ v->VActiveCursorBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5208
+ v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5209
* (v->meta_row_bandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5210
+ v->dpte_row_bandwidth[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5211
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5212
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5213
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5214
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5215
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5216
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5217
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5221
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5222
if (v->NotUrgentLatencyHidingPre[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5232
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5233
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5234
|| v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5240
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5241
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5247
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5248
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5253
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5254
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5263
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5266
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5267
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5268
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5269
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5270
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5271
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5272
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5275
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5277
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5278
+ v->DPTEBytesPerRow[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5281
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5284
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5288
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5289
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5290
v->DPTEBytesPerRow[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5293
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5296
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5297
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5298
+ v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5299
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5300
* (v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5301
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5302
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5303
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5304
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5305
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5311
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5312
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5377
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5378
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5387
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5388
if (v->CursorWidth[k][0] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5389
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5398
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5399
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5400
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5402
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5404
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5405
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5406
&& v->SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5407
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5408
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5409
v->AlignedDCCMetaPitchC[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5410
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5411
64.0 * v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5413
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5416
v->AlignedCPitch[k] = v->PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5417
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5419
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5420
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5425
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5426
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5428
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5429
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5430
&& v->SourcePixelFormat[k] != dm_rgbe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5431
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5432
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5530
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5531
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5532
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5585
int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5603
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5604
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5621
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5623
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5624
/ (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5627
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5628
double EffectiveDETBufferSizeY = DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5632
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5636
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5638
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5640
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5644
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5647
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5648
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5649
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5650
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5651
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5652
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5653
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5660
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5664
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5667
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5669
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5673
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5675
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5677
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5680
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5682
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5683
if (v->WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5687
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5693
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5694
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5695
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5696
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5697
PlaneWithMinActiveDRAMClockChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5700
if (v->BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5711
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5712
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5713
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5714
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5720
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5721
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5773
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5775
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5777
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5778
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5780
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5782
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5785
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5786
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5788
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5792
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5793
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5794
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5796
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5798
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5802
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5803
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5808
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5809
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5923
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5925
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5926
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5927
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5929
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5932
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5933
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5935
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5936
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5938
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5942
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5943
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5945
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5948
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5949
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5951
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5952
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5954
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5959
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5960
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5961
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5963
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5965
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5966
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5967
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5968
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5969
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5971
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5972
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5974
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5976
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5977
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5980
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5981
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5982
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5983
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5984
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5985
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5986
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5987
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5988
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5989
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5990
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5991
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5995
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5997
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5998
if (NumberOfCursors[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5999
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6000
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6002
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6004
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6005
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6007
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6010
CursorRequestDeliveryTime[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6011
CursorRequestDeliveryTimePrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6014
dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6015
dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6016
dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6088
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6090
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6091
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6092
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6093
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6095
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6097
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6098
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6099
DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6101
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6105
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6106
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6107
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6108
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6109
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6110
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6111
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6112
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6114
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6121
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6122
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6123
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6124
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6125
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6126
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6127
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6129
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6130
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6131
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6132
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6133
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6134
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6136
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6143
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6144
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6145
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6148
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6149
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6150
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6151
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6152
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6153
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6157
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6159
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6160
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6162
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6164
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6165
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6166
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6167
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6168
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6169
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6170
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6171
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6173
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6174
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6176
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6178
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6179
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6180
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6181
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6184
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6185
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6186
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6187
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6188
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6189
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6218
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6220
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6221
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6222
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6223
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6224
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6225
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6227
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6231
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6232
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6233
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6235
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6238
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6239
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6240
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6241
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6242
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6244
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6245
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6250
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6251
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6252
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6254
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6258
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6259
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6261
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6264
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6265
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6266
+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6268
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6273
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6274
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6275
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6276
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6279
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6280
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6281
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6282
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6286
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6287
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6288
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6289
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6380
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6387
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6388
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6389
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6390
|| DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6395
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6396
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6398
+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6399
if (ReadBandwidthPlaneChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6400
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6401
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6407
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6408
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6410
+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6413
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6415
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6464
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6465
LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6466
/ BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6467
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6468
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6470
dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6471
dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6472
dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6473
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6474
dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6475
dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6476
dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6477
dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6478
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6479
dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6480
dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6481
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6484
if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6485
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6488
FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6489
VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6490
BytePerPixelYCriticalPlane = BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6491
SwathWidthYCriticalPlane = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6492
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6493
MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6539
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6540
if (WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6570
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6571
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6664
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6698
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6699
unsigned int DETBufferSizeInKByte = DETBufferSizeInKByteA[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6701
if (DETSharedByAllDPP && DPPPerPlane[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6702
DETBufferSizeInKByte /= DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6703
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6704
|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6705
if (SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6706
|| (SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6707
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6708
&& SourceScan[k] != dm_vert)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6709
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6710
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6711
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6713
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6715
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6717
if (SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6718
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6719
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6720
} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6721
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6722
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6723
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6724
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6725
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6726
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6727
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6728
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6730
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6731
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6735
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6736
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6737
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6741
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6742
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6743
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6749
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6750
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6755
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6756
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6761
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6762
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6766
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6767
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6773
if (SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6774
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6775
DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6777
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6778
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6780
DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6781
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6784
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6785
|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6787
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6789
ViewportSizeSupportPerPlane[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6827
int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6833
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6834
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6835
SwathWidthSingleDPPY[k] = ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6837
SwathWidthSingleDPPY[k] = ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6841
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6842
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6845
MainPlaneODMCombine = ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6847
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6853
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6855
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6856
} else if (DPPPerPlane[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6857
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6859
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6863
dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6864
dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6867
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6868
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6869
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6871
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6872
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6876
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6877
SwathWidthC[k] = SwathWidthSingleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6880
int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6881
int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6884
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6887
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6888
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6889
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6890
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6891
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6892
int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6894
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6896
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6898
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6901
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6902
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6903
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6904
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6905
int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6907
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6909
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6911
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6983
int HostVMDynamicLevels = 0, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7000
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7001
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7031
int dummy1, i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7053
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7055
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7058
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7059
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7087
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7092
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7093
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7094
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7095
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7096
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7097
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7098
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7099
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7100
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7101
DynamicMetadataVMExtraLatency[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7102
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7104
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7108
- DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7112
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7113
/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7114
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7117
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7118
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7121
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7123
if (v->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7132
v->RequiredDPPCLK[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7135
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7136
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7137
v->VTotal[k] - v->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7138
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7139
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7140
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7149
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7150
- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7152
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7153
DCFCLKRequiredForPeakBandwidthPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7156
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7161
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7162
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7169
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7171
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7172
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7177
2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7178
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1057
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1059
for (k = 0; k < num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1060
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
1061
pipe_index_in_combine[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2007
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2041
if (v->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2045
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2046
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2047
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2048
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2049
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2050
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2051
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2052
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2053
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2058
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2059
if (v->HRatio[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2060
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2062
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2064
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2067
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2069
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2070
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2072
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2073
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2076
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2077
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2078
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2079
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2081
if (v->HRatioChroma[k] > 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2082
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2084
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2086
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2088
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2090
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2091
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2094
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2095
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2098
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2102
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2103
if (v->BlendingAndTiming[k] != k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2105
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2108
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2112
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2113
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2116
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2120
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2124
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2127
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2151
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2152
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2155
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2156
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2157
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2160
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2161
v->DPPCLK[k] = v->DPPCLK_calculated[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2168
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2170
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2171
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2172
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2173
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2174
&v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2175
&v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2176
&v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2177
&v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2178
&v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2179
&v->BlockWidth256BytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2213
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2214
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2215
* v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2216
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2217
* v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2218
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2244
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2245
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2246
v->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2248
if (v->OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2250
else if (v->OutputFormat[k] == dm_444)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2252
else if (v->OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2256
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2257
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2259
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2260
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2263
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2269
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2270
double BPP = v->OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2272
if (v->DSCEnabled[k] && BPP != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2273
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2274
v->DSCDelay[k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2275
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2278
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2279
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2281
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2282
v->DSCDelay[k] = 2
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2284
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2286
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2287
v->NumberOfDSCSlices[k] / 2.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2288
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2289
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2291
v->DSCDelay[k] = 4
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2293
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2295
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2296
v->NumberOfDSCSlices[k] / 4.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2297
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2298
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2300
v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2301
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2303
v->DSCDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2307
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2309
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2310
v->DSCDelay[k] = v->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2313
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2323
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2324
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2325
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2335
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2336
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2337
v->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2338
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2339
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2340
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2341
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2342
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2343
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2350
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2351
v->DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2352
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2356
&v->dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2357
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2358
&v->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2359
&v->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2360
&v->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2361
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2364
&v->PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2365
&v->PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2366
&v->PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2367
&v->dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2368
&v->meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2370
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2372
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2373
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2374
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2376
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2377
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2378
&v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2379
&v->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2386
v->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2387
v->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2392
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2393
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2394
v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2395
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2396
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2397
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2398
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2399
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2400
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2407
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2408
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2409
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2413
&v->dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2414
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2415
&v->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2416
&v->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2417
&v->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2418
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2419
&v->vm_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2420
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2421
&v->PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2422
&v->PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2423
&v->PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2424
&v->dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2425
&v->meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2427
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2429
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2430
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2431
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2433
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2434
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2435
&v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2436
&v->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2437
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2438
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2439
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2443
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2444
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2445
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2446
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2447
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2450
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2451
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2454
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2455
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2456
&v->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2457
&v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2462
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2463
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2464
if (v->DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2465
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2466
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2467
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2520
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2521
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2522
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2523
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2525
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2526
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2527
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2528
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2529
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2530
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2531
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2532
v->HTotal[k]) / v->DISPCLK;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2534
v->WritebackDelay[v->VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2536
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2537
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2538
v->WritebackDelay[v->VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2548
v->HTotal[k]) / v->DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2554
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2556
if (v->BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2557
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2559
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2560
v->MaxVStartupLines[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2562
v->VTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2563
v->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2564
v->VBlankNom[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2565
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2566
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2568
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2570
v->WritebackDelay[v->VoltageLevel][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2573
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2574
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2575
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2580
for (k = 0; k < v->NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2581
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2611
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2614
myPipe.DPPCLK = v->DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2616
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2618
myPipe.DPPPerPlane = v->DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2619
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2620
myPipe.VRatio = v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2621
myPipe.VRatioChroma = v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2622
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2623
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2624
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2625
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2626
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2627
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2628
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2629
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2630
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2631
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2632
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2633
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2634
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2635
myPipe.BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2636
myPipe.BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2638
v->ErrorResult[k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
264
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2642
v->DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2648
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2649
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2651
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2652
v->MaxVStartupLines[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2658
v->DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2660
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2661
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2665
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2666
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2667
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2668
v->PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2669
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2670
v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2671
v->MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2672
v->PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2673
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2674
v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2675
v->MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2676
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2677
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2678
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2679
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2681
&v->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2682
&v->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2683
&v->DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2684
&v->PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2685
&v->DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2686
&v->DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2687
&v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2688
&v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2689
&v->RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2690
&v->RequiredPrefetchPixDataBWChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2691
&v->NotEnoughTimeForDynamicMetadata[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2692
&v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2693
&v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2694
&v->Tdmdl_vm[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2695
&v->Tdmdl[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2696
&v->TSetup[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2697
&v->VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2698
&v->VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2699
&v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2702
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2704
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2710
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2711
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2712
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2713
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2714
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2717
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2718
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2719
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2720
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2721
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2724
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2725
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2726
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2727
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2728
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2729
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2730
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2731
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2732
&v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2733
&v->UrgBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2734
&v->UrgBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2735
&v->NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2738
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2739
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2740
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2741
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2742
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2745
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2746
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2747
v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2748
v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2749
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2750
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2751
v->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2752
v->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2753
&v->UrgBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2754
&v->UrgBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2755
&v->UrgBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2756
&v->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2760
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2761
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2762
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2763
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2764
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2765
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2766
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2767
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2768
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2772
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2773
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2774
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2775
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2776
+ v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2779
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2780
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2781
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2782
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2783
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2785
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2786
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2788
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2789
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2790
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2791
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2792
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2793
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2794
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2795
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2796
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2797
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2800
if (v->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2803
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2806
if (v->NoUrgentLatencyHiding[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2809
if (v->NoUrgentLatencyHidingPre[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2835
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2836
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2844
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2847
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2848
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2849
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2850
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2851
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2852
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2853
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2857
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2859
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2861
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2864
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2868
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2869
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2870
v->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2875
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2878
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2879
v->DPPPerPlane[k] * v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2880
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2881
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2882
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2883
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2884
* (v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2885
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2886
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2887
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2890
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2891
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2892
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2893
v->DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2894
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2895
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2907
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2908
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2910
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2980
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2981
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2982
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2984
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2986
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3101
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3103
v->AllowDRAMClockChangeDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3104
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3105
v->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3109
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3110
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3111
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3113
v->AllowDRAMClockChangeDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3114
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3115
v->MinTTUVBlank[k] = v->UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3117
if (!v->DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3118
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3123
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3124
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3125
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3126
v->SurfaceWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3127
v->SurfaceWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3128
v->SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3129
v->SurfaceHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3131
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3132
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3133
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3134
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3135
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3136
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3137
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3138
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3139
&v->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3140
&v->DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3141
&v->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3142
&v->DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3143
&v->DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3144
&v->DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3148
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3150
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3152
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3155
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3158
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3159
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3160
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3161
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3164
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3165
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3166
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3169
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3170
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3171
if (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3172
v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3174
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3176
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3177
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3179
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3180
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3181
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3183
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3186
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3187
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3188
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3189
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3190
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3191
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3192
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3193
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3194
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3195
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3196
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3206
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3207
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3208
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3209
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3210
} else if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3211
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3212
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3219
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3220
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3305
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3307
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3310
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3311
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3312
&BytePerPixY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3313
&BytePerPixC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3314
&BytePerPixDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3315
&BytePerPixDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3316
&Read256BytesBlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3317
&Read256BytesBlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3318
&Read256BytesBlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3319
&Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3590
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3604
double LineTime = v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3612
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3618
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3625
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3626
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3635
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3638
v->final_flip_bw[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3639
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3640
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3641
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3642
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3644
v->final_flip_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3647
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3648
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3649
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3650
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3651
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3654
v->dpte_row_height[k] * LineTime / v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3655
v->meta_row_height[k] * LineTime / v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3656
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3657
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3660
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3661
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3662
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3663
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3665
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3669
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3671
v->ImmediateFlipSupportedForPipe[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3673
v->ImmediateFlipSupportedForPipe[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3677
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3678
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3682
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3784
unsigned int k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3789
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3791
myPipe.PixelClock = v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3793
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3794
myPipe.ScalerEnabled = v->ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3795
myPipe.VRatio = mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3796
myPipe.VRatioChroma = mode_lib->vba.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3798
myPipe.SourceScan = v->SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3799
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3800
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3801
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3802
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3803
myPipe.InterlaceEnable = v->Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3804
myPipe.NumberOfCursors = v->NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3805
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3806
myPipe.HTotal = v->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3807
myPipe.DCCEnable = v->DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3808
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3809
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3810
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3811
myPipe.BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3812
myPipe.BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3814
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3818
v->DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3824
v->SwathWidthYThisState[k] / v->HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3825
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3827
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3828
v->MaximumVStartup[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3834
v->DynamicMetadataEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3836
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3837
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3841
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3842
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3843
v->DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3844
v->PrefetchLinesY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3845
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3846
v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3847
v->MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3848
v->PrefetchLinesC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3849
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3850
v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3851
v->MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3852
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3853
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3854
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3855
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3857
&v->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3858
&v->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3859
&v->LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3860
&v->PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3861
&v->LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3862
&v->LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3863
&v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3864
&v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3865
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3866
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3867
&v->NoTimeForDynamicMetadata[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3868
&v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3869
&v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3870
&v->dummy7[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3871
&v->dummy8[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3872
&v->dummy13[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3873
&v->VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3874
&v->VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3875
&v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3883
unsigned int k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3904
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3905
if (v->ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3906
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3907
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3908
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3909
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3910
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3912
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3913
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3914
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3915
|| v->VRatio[k] > v->vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3916
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3917
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3918
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3919
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3920
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3921
|| v->HRatioChroma[k] > v->MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3922
|| v->VRatioChroma[k] > v->MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3923
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3924
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3932
if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3938
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3940
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3941
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3942
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3943
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3944
&v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3945
&v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3946
&v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3947
&v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3948
&v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3949
&v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3951
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3952
if (v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3953
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3954
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3956
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3957
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3960
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3961
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3962
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3963
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3964
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3966
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3967
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3968
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3969
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3970
} else if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3971
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3972
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3974
v->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3981
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3982
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3990
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3991
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4003
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4004
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4005
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4006
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4007
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4008
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4009
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4010
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4011
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4014
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4022
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4023
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4027
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4028
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4029
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4030
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4031
v->WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4032
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4033
v->WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4034
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4035
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4039
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4040
if (v->HRatio[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4041
v->PSCL_FACTOR[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4043
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4045
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4047
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4048
v->PSCL_FACTOR_CHROMA[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4049
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4052
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4054
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4055
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4058
if (v->HRatioChroma[k] > 1.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4059
v->PSCL_FACTOR_CHROMA[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4061
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4063
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4065
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4067
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4068
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4069
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4070
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4072
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4073
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4074
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4078
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4082
if (v->SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4084
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4086
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4092
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4097
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4098
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4099
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4102
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4103
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4105
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4106
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4155
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4156
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4161
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4164
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4169
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4172
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4177
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4182
|| !(v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4183
v->Output[k] == dm_dp2p0 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4184
v->Output[k] == dm_edp)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4185
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4188
if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4191
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4195
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4198
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4201
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4204
if (v->DSCEnabled[k] && v->HActive[k] > DCN314_MAX_DSC_IMAGE_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4205
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4206
if (v->HActive[k] / 2 > DCN314_MAX_DSC_IMAGE_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4207
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4210
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4214
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN314_MAX_FMT_420_BUFFER_WIDTH
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4215
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4216
if (v->Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4218
} else if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4219
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4222
if (v->HActive[k] / 4 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4225
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4229
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4230
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4231
v->NoOfDPP[i][j][k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4232
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4233
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4234
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4235
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4236
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4238
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4239
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4240
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4241
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4242
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4244
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4245
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4246
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4249
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4257
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4258
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4259
if (v->NoOfDPP[i][j][k] == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4261
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4262
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4275
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4276
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4277
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4278
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4279
NumberOfNonSplitPlaneOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4294
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4295
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4296
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4297
v->MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4298
v->NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4299
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4302
v->MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4303
v->NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4304
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4309
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4312
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4315
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4322
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4323
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4347
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4348
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4349
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4355
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4356
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4357
if (v->PixelClockBackEnd[k] > 3200) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4358
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4359
} else if (v->PixelClockBackEnd[k] > 1360) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4360
v->NumberOfDSCSlices[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4361
} else if (v->PixelClockBackEnd[k] > 680) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4362
v->NumberOfDSCSlices[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4363
} else if (v->PixelClockBackEnd[k] > 340) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4364
v->NumberOfDSCSlices[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4366
v->NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4369
v->NumberOfDSCSlices[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4374
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4375
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4376
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4377
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4378
if (v->Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4379
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4380
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4381
v->OutputBppPerState[i][k] = TruncToValidBPP(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4384
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4385
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4386
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4387
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4389
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4390
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4391
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4392
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4393
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4394
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4395
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4396
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4397
if (v->DSCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4398
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4400
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4401
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4403
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4406
v->RequiresDSC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4408
if (v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4409
v->RequiresFEC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4411
v->RequiresFEC[i][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4414
if (v->Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4416
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4417
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4420
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4421
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4422
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4423
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4424
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4426
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4427
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4428
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4429
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4430
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4431
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4432
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4433
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4434
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4435
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4439
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4440
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4441
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4442
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4443
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4445
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4446
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4447
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4448
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4449
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4450
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4451
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4453
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4458
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4459
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4462
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4463
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4464
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4465
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4466
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4468
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4469
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4470
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4471
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4472
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4473
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4474
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4475
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4476
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4477
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4481
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4482
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4483
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4484
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4485
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4487
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4488
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4489
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4490
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4491
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4492
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4493
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4495
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4500
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4501
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4504
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4505
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4506
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4507
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4508
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4510
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4511
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4512
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4513
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4514
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4515
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4516
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4517
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4518
v->ForcedOutputLinkBPP[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4519
v->RequiresDSC[i][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4523
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4524
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4525
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4526
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4527
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4529
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4530
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4531
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4532
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4533
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4534
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4535
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4537
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4546
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4547
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4548
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4549
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4550
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4552
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4553
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4554
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4555
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4556
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4557
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4558
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4559
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4566
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4567
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4568
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4569
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4570
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4572
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4573
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4574
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4575
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4576
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4577
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4578
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4579
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4586
v->OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4587
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4588
v->HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4589
v->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4590
v->ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4592
v->Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4593
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4594
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4595
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4596
v->AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4597
v->AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4598
v->ODMCombineEnablePerState[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4599
v->OutputBppPerState[i][k] = v->Outbpp;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4606
v->OutputBppPerState[i][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4613
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4614
if (v->BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4615
&& (v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4616
v->Output[k] == dm_edp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4617
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4624
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4625
if (v->BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4626
&& (v->Output[k] == dm_dp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4627
v->Output[k] == dm_edp ||
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4628
v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4629
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4632
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4642
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4643
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4644
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4645
|| v->Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4656
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4657
if (v->RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4658
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4660
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4674
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4675
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4678
v->BPP = v->OutputBppPerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4680
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4681
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4682
v->DSCDelayPerState[i][k] = dscceComputeDelay(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4683
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4685
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4686
v->NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4687
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4688
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4689
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4690
v->DSCDelayPerState[i][k] = 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4692
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4694
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4695
v->NumberOfDSCSlices[k] / 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4696
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4697
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4699
v->DSCDelayPerState[i][k] = 4.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4701
v->DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4703
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4704
v->NumberOfDSCSlices[k] / 4,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4705
v->OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4706
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4708
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelayPerState[i][k] / v->HActive[k], 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4709
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4711
v->DSCDelayPerState[i][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4714
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4716
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4717
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4727
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4728
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4729
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4730
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4794
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4795
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4796
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4797
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4798
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4799
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4800
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4801
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4802
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4807
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4808
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4809
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4816
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4817
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4818
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4819
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4820
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4821
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4822
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4823
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4824
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4828
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4829
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4830
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4834
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4835
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4836
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4838
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4839
&& v->SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4850
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4851
v->Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4852
v->Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4853
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4854
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4855
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4856
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4857
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4858
v->ViewportHeightChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4865
v->PitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4867
&v->MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4870
&v->PTEBufferSizeNotExceededC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4872
&v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4876
&v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4885
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4887
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4888
v->VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4889
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4891
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4892
v->ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4893
&v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4894
&v->MaxNumSwC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4901
v->PrefetchLinesC[i][j][k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4902
v->PTEBufferSizeNotExceededC[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4906
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4907
v->Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4908
v->Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4909
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4910
v->SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4911
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4912
v->SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4913
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4914
v->ViewportHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4921
v->PitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4922
v->DCCMetaPitchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4923
&v->MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4926
&v->PTEBufferSizeNotExceededY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4928
&v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4932
&v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4934
&v->dpte_group_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4940
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4942
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4943
v->vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4944
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4946
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4947
v->ViewportYStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4948
&v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4949
&v->MaxNumSwY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4950
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4951
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4952
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4956
v->SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4957
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4958
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4959
v->DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4960
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4963
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4964
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4967
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4968
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4969
&v->meta_row_bandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4970
&v->dpte_row_bandwidth[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4981
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4982
if (v->MetaRowBytes[i][j][k] > 24064)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4994
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4996
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4997
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4998
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4999
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5000
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5003
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5004
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5005
v->VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5006
v->VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5007
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5008
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5009
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5010
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5011
&v->UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5012
&v->UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5013
&v->UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5014
&NotUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5018
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5019
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5024
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5025
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5026
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5027
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5034
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5035
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5036
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5037
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5038
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5046
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5047
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5048
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5049
v->WritebackDelayTime[k] = v->WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5051
v->WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5052
v->WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5053
v->WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5054
v->WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5055
v->WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5056
v->WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5057
v->WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5058
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5060
v->WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5063
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5064
v->WritebackDelayTime[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5065
v->WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5080
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5082
if (v->BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5083
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5088
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5089
v->MaximumVStartup[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5091
v->VTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5092
v->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5093
v->VBlankNom[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5094
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5095
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5097
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5099
v->WritebackDelayTime[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5100
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5156
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5157
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5204
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5205
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5206
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5207
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5208
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5209
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5210
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5211
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5212
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5213
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5255
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5258
i, j, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5261
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5263
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5264
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5265
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5266
v->SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5267
v->HTotal[k] / v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5270
v->CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5271
v->CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5272
v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5273
v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5274
v->BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5275
v->BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5276
v->DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5277
v->DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5278
&v->UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5279
&v->UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5280
&v->UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5281
&v->NotUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5285
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5286
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5287
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5292
v->VActivePixelBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5293
+ v->VActiveCursorBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5294
+ v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5295
* (v->meta_row_bandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5296
+ v->dpte_row_bandwidth[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5297
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5298
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5299
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5300
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5301
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5302
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5303
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5307
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5308
if (v->NotUrgentLatencyHidingPre[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5318
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5319
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5320
|| v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5326
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5327
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5333
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5334
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5339
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5340
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5349
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5352
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5353
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5354
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5355
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5356
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5357
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5358
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5361
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5363
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5364
+ v->DPTEBytesPerRow[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5367
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5370
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5374
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5375
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5376
v->DPTEBytesPerRow[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5379
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5382
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5383
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5384
+ v->VActiveCursorBandwidth[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5385
v->NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5386
* (v->final_flip_bw[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5387
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5388
* v->UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5389
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5390
* v->UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5391
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5398
if (v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5463
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5464
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5473
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5474
if (v->CursorWidth[k][0] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5475
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5483
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5484
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5485
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5486
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5488
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5490
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5491
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5492
&& v->SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5493
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5494
if (v->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5495
v->AlignedDCCMetaPitchC[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5496
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5497
64.0 * v->Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5499
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5502
v->AlignedCPitch[k] = v->PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5503
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5505
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5506
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5511
for (k = 0; k < v->NumberOfActivePlanes; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5512
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5514
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5515
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5516
&& v->SourcePixelFormat[k] != dm_rgbe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5517
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5518
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5624
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5625
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5626
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5679
int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5697
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5698
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5715
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5717
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5718
/ (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5722
double EffectiveDETBufferSizeY = DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5726
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5730
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5732
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5734
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5738
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5741
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5742
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5743
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5744
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5745
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5746
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5747
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5754
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5758
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5761
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5763
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5767
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5769
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5771
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5774
if (v->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5776
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5777
if (v->WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5781
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5787
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5788
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5789
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5790
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5791
PlaneWithMinActiveDRAMClockChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5794
if (v->BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5805
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5806
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5807
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5808
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5814
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5815
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5867
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5869
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5871
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5872
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5874
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5876
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5879
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5880
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5882
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5886
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5887
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5888
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5890
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5892
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5896
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5897
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5902
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5903
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6017
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6019
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6020
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6021
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6023
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6026
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6027
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6029
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6030
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6032
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6036
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6037
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6039
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6042
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6043
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6045
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6046
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6048
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6053
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6054
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6055
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6057
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6059
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6060
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6061
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6062
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6063
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6065
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6066
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6068
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6070
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6071
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6074
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6075
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6076
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6077
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6078
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6079
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6080
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6081
dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6082
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6083
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6084
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6085
dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6089
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6092
cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6093
if (NumberOfCursors[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6094
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6095
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6097
CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6099
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6100
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6102
CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6105
CursorRequestDeliveryTime[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6106
CursorRequestDeliveryTimePrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6109
dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6110
dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6111
dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6183
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6185
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6186
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6187
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6188
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6190
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6192
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6193
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6194
DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6196
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6200
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6201
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6202
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6203
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6204
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6205
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6206
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6207
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6209
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6216
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6217
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6218
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6219
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6220
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6221
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6222
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6224
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6225
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6226
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6227
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6228
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6229
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6231
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6238
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6239
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6240
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6243
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6244
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6245
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6246
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6247
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6248
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6252
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6254
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6255
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6257
dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6259
dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6260
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6261
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6262
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6263
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6264
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6265
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6266
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6268
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6269
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6271
dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6273
dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6274
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6275
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6276
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6279
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6280
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6281
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6282
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6283
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6284
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6313
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6315
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6316
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6317
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6318
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6319
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6320
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6322
num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6326
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6327
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6328
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6330
num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6333
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6334
num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6335
+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6336
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6337
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6339
num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6340
+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6345
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6346
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6347
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6349
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6353
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6354
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6356
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6359
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6360
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6361
+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6363
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6368
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6369
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6370
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6371
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6374
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6375
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6376
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6377
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6381
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6382
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6383
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6384
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6475
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6482
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6483
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6484
if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6485
|| DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6490
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6491
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6493
+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6494
if (ReadBandwidthPlaneChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6495
if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6496
|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6502
+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6503
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6505
+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6508
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6510
TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6559
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6560
LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6561
/ BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6562
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6563
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6565
dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6566
dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6567
dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6568
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6569
dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6570
dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6571
dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6572
dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6573
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6574
dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6575
dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6576
dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6579
if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6580
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6583
FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6584
VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6585
BytePerPixelYCriticalPlane = BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6586
SwathWidthYCriticalPlane = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6587
LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6588
MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6634
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6635
if (WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6665
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6666
if (v->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6758
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6792
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6793
if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6794
|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6795
if (SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6796
|| (SourcePixelFormat[k] == dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6797
&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6798
&& SourceScan[k] != dm_vert)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6799
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6800
} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6801
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6803
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6805
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6807
if (SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6808
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6809
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6810
} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6811
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6812
MinimumSwathHeightC = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6813
} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6814
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6815
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6816
} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6817
MinimumSwathHeightY = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6818
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6820
MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6821
MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6825
RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6826
RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6827
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6831
RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6832
RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6833
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6839
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6840
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6845
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6846
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6851
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6852
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6856
SwathHeightY[k] = MinimumSwathHeightY;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6857
SwathHeightC[k] = MinimumSwathHeightC;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6864
if (SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6865
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6866
DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6868
DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6869
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6871
DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6872
DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6875
if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6876
|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6878
ViewportSizeSupportPerPlane[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6880
ViewportSizeSupportPerPlane[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6918
int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6924
for (k = 0; k < NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6925
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6926
SwathWidthSingleDPPY[k] = ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6928
SwathWidthSingleDPPY[k] = ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6932
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6933
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6936
MainPlaneODMCombine = ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6938
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6944
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6946
SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6947
else if (DPPPerPlane[k] == 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6948
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6950
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6953
dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6954
dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6957
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6958
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6959
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6961
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6962
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6966
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6967
SwathWidthC[k] = SwathWidthSingleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6970
int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6971
int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6974
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6977
if (SourceScan[k] != dm_vert) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6978
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6979
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6980
swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6981
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6982
int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6984
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6986
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6988
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6991
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6992
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6993
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6994
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6995
int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6997
swath_width_chroma_ub[k] = dml_min(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6999
(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7001
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7073
int HostVMDynamicLevels = 0, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7089
for (k = 0; k < NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7090
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7118
int dummy1, i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7140
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7142
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7145
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7146
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7173
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7178
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7179
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7180
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7181
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7182
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7183
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7184
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7185
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7186
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7187
DynamicMetadataVMExtraLatency[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7188
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7190
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7194
- DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7199
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7200
/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7201
DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7204
DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7205
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7208
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7210
if (v->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7219
v->RequiredDPPCLK[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7222
v->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7223
v->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7224
v->VTotal[k] - v->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7225
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7226
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7227
v->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7236
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7237
- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7239
DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7240
DCFCLKRequiredForPeakBandwidthPerPlane[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7243
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7248
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7249
DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7256
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7259
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7260
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7265
2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7266
(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1144
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1146
for (k = 0; k < num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1147
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c
1148
pipe_index_in_combine[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2738
for (int k = start_index; k < end_index; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2739
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2740
swap_table_entries(&table[k], &table[k+1]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1020
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1021
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1023
+ mode_lib->vba.DPPPerPlane[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1024
* (v->PDEAndMetaPTEBytesFrame[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1025
+ v->MetaRowByte[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1026
if (v->use_one_row_for_frame_flip[k][0][0]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1029
+ 2 * v->PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
103
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1033
+ v->PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1037
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
104
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1046
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1047
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1048
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1051
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1052
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1053
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1054
mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1055
v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1056
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1057
v->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1058
v->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1059
v->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1060
v->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1061
v->Use_One_Row_For_Frame_Flip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1064
&v->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1065
&v->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1066
&v->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1067
&v->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
107
mode_lib->vba.ODMCombineEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
108
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1124
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1125
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1128
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1143
for (uint k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1144
dml_print("DML::%s: ImmediateFlipRequirement[%d] = %d\n", __func__, k, mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
116
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
117
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
118
mode_lib->vba.HRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
119
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
120
mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
123
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1235
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1236
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1237
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1238
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
124
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1240
v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1241
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1244
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1245
v->WritebackAllowFCLKChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
125
mode_lib->vba.htaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
126
mode_lib->vba.HTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
127
mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
128
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
131
&v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
132
&v->DPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1366
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1368
v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1373
v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1377
v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1380
v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1382
if (!mode_lib->vba.DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1383
v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1387
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1389
dml_print("DML::%s: Calculate DCC configuration for surface k=%d\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1392
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1394
mode_lib->vba.SourcePixelFormat[k], mode_lib->vba.SurfaceWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1395
mode_lib->vba.SurfaceWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1396
mode_lib->vba.SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1397
mode_lib->vba.SurfaceHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1399
v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
140
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1400
v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1401
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1402
v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1403
v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1404
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1405
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1406
(enum dm_rotation_angle) mode_lib->vba.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1408
&v->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1409
&v->DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
141
v->DPPCLK_calculated[k] = v->DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1410
&v->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1411
&v->DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1412
&v->DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1413
&v->DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1417
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1419
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1420
/ mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1422
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1423
v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1426
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1429
dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1430
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1431
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1432
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1435
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1436
if (mode_lib->vba.DynamicMetadataEnable[k] && mode_lib->vba.DynamicMetadataVMEnabled)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1437
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1439
isInterlaceTiming = (mode_lib->vba.Interlace[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
144
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1442
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1443
mode_lib->vba.VFrontPorch[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1444
mode_lib->vba.VTotal[k]) - mode_lib->vba.VFrontPorch[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1446
dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1447
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1448
+ dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1449
/ mode_lib->vba.PixelClock[k]), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1451
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1453
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1454
/ mode_lib->vba.HTotal[k]) <= (isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1455
- mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1456
(int) (mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1457
- mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1458
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
146
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1460
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1463
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1464
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1465
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1466
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1467
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, mode_lib->vba.HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1468
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, mode_lib->vba.VTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1469
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, mode_lib->vba.VActive[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
147
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1470
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, mode_lib->vba.VFrontPorch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1471
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1472
dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1473
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1474
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1475
v->VREADY_AT_OR_AFTER_VSYNC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1481
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1482
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1483
&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1484
WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1485
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1486
/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1487
/ mode_lib->vba.PixelClock[k]) * 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1488
} else if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1489
WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1490
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1491
/ (mode_lib->vba.HTotal[k] * mode_lib->vba.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1492
/ mode_lib->vba.PixelClock[k]) * 8;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1498
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1499
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
150
&v->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1500
+ v->ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1503
__func__, k, v->TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1505
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1507
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
151
&v->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
152
&v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
153
&v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
154
&v->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
155
&v->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
156
&v->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
157
&v->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
158
&v->BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
159
&v->BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
160
&v->BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
161
&v->BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1728
unsigned int k, m;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1748
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1749
if (mode_lib->vba.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1750
&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1751
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1752
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1753
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1754
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1755
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1756
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1757
|| mode_lib->vba.HRatio[k] != 1.0 || mode_lib->vba.htaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1758
|| mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1760
} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1761
|| mode_lib->vba.htaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1762
|| (mode_lib->vba.htaps[k] > 1.0 && (mode_lib->vba.htaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1763
|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1764
|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1765
|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1766
|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1767
|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1768
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1769
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1770
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1771
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1772
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1773
&& (mode_lib->vba.VTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1774
|| mode_lib->vba.VTAPsChroma[k] > 8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1775
|| mode_lib->vba.HTAPsChroma[k] < 1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1776
|| mode_lib->vba.HTAPsChroma[k] > 8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1777
|| (mode_lib->vba.HTAPsChroma[k] > 1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1778
&& mode_lib->vba.HTAPsChroma[k] % 2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1780
|| mode_lib->vba.HRatioChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1782
|| mode_lib->vba.VRatioChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1784
|| mode_lib->vba.HRatioChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1785
> mode_lib->vba.HTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1786
|| mode_lib->vba.VRatioChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1787
> mode_lib->vba.VTAPsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1794
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1795
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1796
&& (!(!IsVertical((enum dm_rotation_angle) mode_lib->vba.SourceScan[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1797
|| mode_lib->vba.DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1802
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1804
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1805
mode_lib->vba.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1808
&mode_lib->vba.BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1809
&mode_lib->vba.BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1810
&mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1811
&mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1812
&mode_lib->vba.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1813
&mode_lib->vba.Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1814
&mode_lib->vba.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1815
&mode_lib->vba.Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1816
&mode_lib->vba.MacroTileHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1817
&mode_lib->vba.MacroTileHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1818
&mode_lib->vba.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1819
&mode_lib->vba.MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1823
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1824
if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1825
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1826
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1828
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1829
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1832
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1833
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1834
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1835
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1836
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1839
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1840
if (mode_lib->vba.WritebackEnable[k] == true && mode_lib->vba.WritebackPixelFormat[k] == dm_444_64) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1841
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1842
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1843
/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1844
/ mode_lib->vba.PixelClock[k]) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1845
} else if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1846
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1847
* mode_lib->vba.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1848
/ (mode_lib->vba.WritebackSourceHeight[k] * mode_lib->vba.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1849
/ mode_lib->vba.PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1851
v->WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1858
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1859
if (mode_lib->vba.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1860
&& (v->WriteBandwidth[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1870
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1871
if (mode_lib->vba.WritebackEnable[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1880
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1881
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1882
if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1883
|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackMaxVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1884
|| mode_lib->vba.WritebackHRatio[k] < mode_lib->vba.WritebackMinHSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1885
|| mode_lib->vba.WritebackVRatio[k] < mode_lib->vba.WritebackMinVSCLRatio
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1886
|| mode_lib->vba.WritebackHTaps[k] > mode_lib->vba.WritebackMaxHSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1887
|| mode_lib->vba.WritebackVTaps[k] > mode_lib->vba.WritebackMaxVSCLTaps
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1888
|| mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1889
|| mode_lib->vba.WritebackVRatio[k] > mode_lib->vba.WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1890
|| (mode_lib->vba.WritebackHTaps[k] > 2.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1891
&& ((mode_lib->vba.WritebackHTaps[k] % 2) == 1))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1894
if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1901
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1902
dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(mode_lib->vba.HRatio[k], mode_lib->vba.HRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1903
mode_lib->vba.VRatio[k], mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1905
mode_lib->vba.PixelClock[k], mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1906
mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1907
mode_lib->vba.VTAPsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1909
&mode_lib->vba.PSCL_FACTOR[k], &mode_lib->vba.PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1910
&mode_lib->vba.MinDPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1913
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1915
if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1917
} else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1918
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1920
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1921
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1923
} else if (mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1925
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1926
mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1932
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 || mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1933
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1939
* dml_max(mode_lib->vba.HRatio[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1940
/ (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1941
if (v->BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1945
* dml_max(mode_lib->vba.HRatioChroma[k], 1.0) / mode_lib->vba.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1946
/ (mode_lib->vba.VTAPsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1947
+ dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1950
v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1952
v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2024
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2025
if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_reduce_voltage_and_clocks)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2027
if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_always_when_possible)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2040
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2043
mode_lib->vba.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2044
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2045
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2046
mode_lib->vba.ODMUse[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
205
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2052
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2056
mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
206
v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2066
mode_lib->vba.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2067
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2068
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2069
mode_lib->vba.ODMUse[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
207
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2075
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2079
mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
208
v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
209
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2092
(mode_lib->vba.BlendingAndTiming[k] == k),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2093
mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2094
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2095
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2096
mode_lib->vba.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2097
mode_lib->vba.PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2098
mode_lib->vba.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2099
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
210
* mode_lib->vba.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2100
mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2101
mode_lib->vba.AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2102
mode_lib->vba.AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2105
mode_lib->vba.DSCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2106
mode_lib->vba.OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2107
mode_lib->vba.OutputLinkDPRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2110
&mode_lib->vba.RequiresDSC[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2111
&mode_lib->vba.RequiresFEC[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2112
&mode_lib->vba.OutputBppPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2113
&mode_lib->vba.OutputTypePerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2114
&mode_lib->vba.OutputRatePerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2115
&mode_lib->vba.RequiredSlots[i][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2117
if (mode_lib->vba.RequiresDSC[i][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2118
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2119
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2126
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2127
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
213
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2136
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2137
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2138
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2139
mode_lib->vba.NoOfDPP[i][j][k] = 4;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2140
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2141
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2142
mode_lib->vba.NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2143
} else if (mode_lib->vba.MPCCombineUse[k] == dm_mpc_never) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2144
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2145
mode_lib->vba.NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2147
mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
215
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2151
mode_lib->vba.SingleDPPViewportSizeSupportPerSurface[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2152
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2153
mode_lib->vba.NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2155
mode_lib->vba.MPCCombine[i][j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2156
mode_lib->vba.NoOfDPP[i][j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2160
mode_lib->vba.MPCCombine[i][j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2161
mode_lib->vba.NoOfDPP[i][j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2169
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2170
if (mode_lib->vba.NoOfDPP[i][j][k] == 1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2173
if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2174
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_10
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2175
|| mode_lib->vba.SourcePixelFormat[k] == dm_420_12
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2176
|| mode_lib->vba.SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2198
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2199
if (mode_lib->vba.MPCCombineUse[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2201
mode_lib->vba.MPCCombineUse[k] != dm_mpc_reduce_voltage &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2202
mode_lib->vba.ReadBandwidthLuma[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2203
mode_lib->vba.ReadBandwidthChroma[k] >
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2205
(mode_lib->vba.ODMCombineEnablePerState[i][k] !=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2207
mode_lib->vba.ODMCombineEnablePerState[i][k] !=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2209
mode_lib->vba.MPCCombine[i][j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2211
mode_lib->vba.ReadBandwidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2212
+ mode_lib->vba.ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2213
NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2228
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2229
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2233
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2234
mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2235
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2236
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2237
mode_lib->vba.WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2238
mode_lib->vba.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2239
mode_lib->vba.WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2240
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2241
mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2248
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2250
mode_lib->vba.RequiredDISPCLKPerSurface[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2253
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2254
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2263
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2264
mode_lib->vba.RequiredDPPCLK[i][j][k] = mode_lib->vba.RequiredDPPCLKThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2281
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2282
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2284
if (mode_lib->vba.Output[k] == dm_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2286
if (mode_lib->vba.OutputMultistreamId[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2287
== k || mode_lib->vba.OutputMultistreamEn[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2301
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2302
if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2303
|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2304
|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2305
|| mode_lib->vba.DSCInputBitPerComponent[k] > mode_lib->vba.MaximumDSCBitsPerComponent) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2312
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2313
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2314
TotalSlots = mode_lib->vba.RequiredSlots[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2316
if (mode_lib->vba.OutputMultistreamId[j] == k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2319
if (mode_lib->vba.Output[k] == dm_dp && TotalSlots > 63)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2321
if (mode_lib->vba.Output[k] == dm_dp2p0 && TotalSlots > 64)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2326
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2327
if (mode_lib->vba.BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2328
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2329
|| mode_lib->vba.Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2330
|| mode_lib->vba.Output[k] == dm_hdmi)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2331
&& mode_lib->vba.OutputBppPerState[i][k] == 0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2332
(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2351
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2352
if (mode_lib->vba.BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2353
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2354
|| mode_lib->vba.Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2355
|| mode_lib->vba.Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2356
if (mode_lib->vba.OutputFormat[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2357
== dm_420 && mode_lib->vba.Interlace[k] == 1 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2361
if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2363
if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2367
if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2368
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2369
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2370
&& mode_lib->vba.Output[k] != dm_dp && mode_lib->vba.Output[k] != dm_edp)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2371
|| ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2372
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2373
|| mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2374
&& mode_lib->vba.Output[k] != dm_dp2p0))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2377
if (mode_lib->vba.OutputMultistreamEn[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2378
if (mode_lib->vba.OutputMultistreamId[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2379
&& mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2381
if (mode_lib->vba.OutputMultistreamId[k] == k && mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2384
if (mode_lib->vba.OutputMultistreamId[k] == j
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2385
&& mode_lib->vba.ForcedOutputLinkBPP[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2390
if ((mode_lib->vba.Output[k] == dm_edp || mode_lib->vba.Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2391
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2394
if (mode_lib->vba.OutputMultistreamEn[k] == true && mode_lib->vba.OutputMultistreamId[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2399
if (mode_lib->vba.Output[k] != dm_dp
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2400
&& (mode_lib->vba.ODMUse[k] == dm_odm_split_policy_1to2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2401
|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2402
|| mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2405
if ((mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to2
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2406
&& mode_lib->vba.OutputLinkDPLanes[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2407
|| (mode_lib->vba.ODMUse[k] == dm_odm_mso_policy_1to4
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2408
&& mode_lib->vba.OutputLinkDPLanes[k] < 4))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2415
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2416
if (mode_lib->vba.BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2417
&& dml32_RequiredDTBCLK(mode_lib->vba.RequiresDSC[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2418
mode_lib->vba.PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2419
mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2420
mode_lib->vba.OutputBppPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2421
mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2422
mode_lib->vba.HActive[k], mode_lib->vba.AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2423
mode_lib->vba.AudioSampleLayout[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2433
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2434
if (mode_lib->vba.BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2435
&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2436
&& mode_lib->vba.Output[k] == dm_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2439
if (mode_lib->vba.BlendingAndTiming[k] == k
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2440
&& mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2441
&& (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_edp
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2442
|| mode_lib->vba.Output[k] == dm_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2450
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2451
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2452
if (mode_lib->vba.Output[k] == dm_dp || mode_lib->vba.Output[k] == dm_dp2p0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2453
|| mode_lib->vba.Output[k] == dm_edp) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2454
if (mode_lib->vba.OutputFormat[k] == dm_420) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2456
} else if (mode_lib->vba.OutputFormat[k] == dm_444) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2458
} else if (mode_lib->vba.OutputFormat[k] == dm_n422) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2463
if (mode_lib->vba.RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2464
if (mode_lib->vba.ODMCombineEnablePerState[i][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2466
if (mode_lib->vba.PixelClockBackEnd[k] / 12.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2468
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2470
if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2473
if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor > (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2490
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2491
if (mode_lib->vba.RequiresDSC[i][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2492
if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2493
if (mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2497
if (mode_lib->vba.NumberOfDSCSlices[k] > 16)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2499
} else if (mode_lib->vba.ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2500
if (mode_lib->vba.HActive[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2504
if (mode_lib->vba.NumberOfDSCSlices[k] > 8)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2507
if (mode_lib->vba.HActive[k] > mode_lib->vba.MaximumPixelsPerLinePerDSCUnit)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2510
if (mode_lib->vba.NumberOfDSCSlices[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2521
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2522
mode_lib->vba.DSCDelayPerState[i][k] = dml32_DSCDelayRequirement(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2523
mode_lib->vba.RequiresDSC[i][k], mode_lib->vba.ODMCombineEnablePerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2524
mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2525
mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2526
mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2527
mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2528
mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2532
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2535
if (mode_lib->vba.BlendingAndTiming[k] == m &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2537
mode_lib->vba.DSCDelayPerState[i][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2549
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2550
mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2551
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2552
mode_lib->vba.ODMCombineEnableThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2553
mode_lib->vba.ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2620
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2621
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2622
mode_lib->vba.swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2623
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2624
mode_lib->vba.swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2625
mode_lib->vba.SwathWidthYAllStates[i][j][k] = mode_lib->vba.SwathWidthYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2626
mode_lib->vba.SwathWidthCAllStates[i][j][k] = mode_lib->vba.SwathWidthCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2627
mode_lib->vba.SwathHeightYAllStates[i][j][k] = mode_lib->vba.SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2628
mode_lib->vba.SwathHeightCAllStates[i][j][k] = mode_lib->vba.SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2633
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2634
mode_lib->vba.DETBufferSizeInKByteThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2635
mode_lib->vba.DETBufferSizeYAllStates[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2636
mode_lib->vba.DETBufferSizeYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2637
mode_lib->vba.DETBufferSizeCAllStates[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2638
mode_lib->vba.DETBufferSizeCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2643
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2644
mode_lib->vba.cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2645
* mode_lib->vba.CursorBPP[k][0] / 8.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2646
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2687
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2688
mode_lib->vba.swath_width_luma_ub_this_state[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2689
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2690
mode_lib->vba.swath_width_chroma_ub_this_state[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2691
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2692
mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2693
mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2694
mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2695
mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2696
mode_lib->vba.DETBufferSizeInKByteThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2697
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2698
mode_lib->vba.DETBufferSizeYThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2699
mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2700
mode_lib->vba.DETBufferSizeCThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2701
mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2702
mode_lib->vba.RequiredDPPCLKThisState[k] = mode_lib->vba.RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2703
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2707
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2708
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2711
+ mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2716
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2717
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2718
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2719
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2720
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2721
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2722
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2723
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2724
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2725
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2726
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2727
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2728
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2729
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2730
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2731
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2732
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2733
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2734
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2735
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2736
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2737
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2739
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2740
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2741
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2742
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2743
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2744
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2745
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2746
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2747
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2748
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2749
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2750
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2751
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2752
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2753
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2754
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2824
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2825
mode_lib->vba.PrefetchLinesY[i][j][k] = mode_lib->vba.PrefetchLinesYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2826
mode_lib->vba.PrefetchLinesC[i][j][k] = mode_lib->vba.PrefetchLinesCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2827
mode_lib->vba.meta_row_bandwidth[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2828
mode_lib->vba.meta_row_bandwidth_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2829
mode_lib->vba.dpte_row_bandwidth[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2830
mode_lib->vba.dpte_row_bandwidth_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2831
mode_lib->vba.DPTEBytesPerRow[i][j][k] = mode_lib->vba.DPTEBytesPerRowThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2832
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2833
mode_lib->vba.PDEAndMetaPTEBytesPerFrameThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2834
mode_lib->vba.MetaRowBytes[i][j][k] = mode_lib->vba.MetaRowBytesThisState[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2835
mode_lib->vba.use_one_row_for_frame[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2836
mode_lib->vba.use_one_row_for_frame_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2837
mode_lib->vba.use_one_row_for_frame_flip[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2838
mode_lib->vba.use_one_row_for_frame_flip_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2842
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2843
if (mode_lib->vba.PTEBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2848
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2849
if (mode_lib->vba.DCCMetaBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2862
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2864
mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2865
mode_lib->vba.swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2866
mode_lib->vba.swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2867
mode_lib->vba.SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2868
mode_lib->vba.SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2869
(double) mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2872
mode_lib->vba.CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2873
mode_lib->vba.CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2874
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2875
mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2876
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2877
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2878
mode_lib->vba.DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2879
mode_lib->vba.DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2881
&mode_lib->vba.UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2882
&mode_lib->vba.UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2883
&mode_lib->vba.UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2884
&mode_lib->vba.NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2914
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2915
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2916
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2917
mode_lib->vba.WritebackDelayTime[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2920
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2921
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2922
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2923
mode_lib->vba.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2924
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2925
mode_lib->vba.WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2926
mode_lib->vba.WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2927
mode_lib->vba.HTotal[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2930
mode_lib->vba.WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2934
== k && mode_lib->vba.WritebackEnable[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2935
mode_lib->vba.WritebackDelayTime[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2936
dml_max(mode_lib->vba.WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2952
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2954
if (mode_lib->vba.BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2955
mode_lib->vba.WritebackDelayTime[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2961
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2962
mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2964
dml_floor((mode_lib->vba.VTotal[k] -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2965
mode_lib->vba.VActive[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2966
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2968
mode_lib->vba.WritebackDelayTime[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2969
(mode_lib->vba.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2970
mode_lib->vba.PixelClock[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2973
if (mode_lib->vba.MaximumVStartup[i][j][k] > 1023)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2974
mode_lib->vba.MaximumVStartup[i][j][k] = 1023;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2977
mode_lib->vba.MaximumVStartup[i][j][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2998
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3000
|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3004
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3007
|| ((mode_lib->vba.ImmediateFlipRequirement[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3009
&& (mode_lib->vba.ImmediateFlipRequirement[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3017
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3020
((mode_lib->vba.HostVMEnable == true || mode_lib->vba.ImmediateFlipRequirement[k] !=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3022
(mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3023
mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3027
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3030
|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3031
|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3032
&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3033
|| ((mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_disable
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3034
|| mode_lib->vba.UseMALLForStaticScreen[k] == dm_use_mall_static_screen_optimize)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3035
&& (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3042
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3043
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3045
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3047
if (mode_lib->vba.UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3139
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3140
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3141
+ mode_lib->vba.ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3173
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3174
mode_lib->vba.NoOfDPPThisState[k] = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3175
mode_lib->vba.swath_width_luma_ub_this_state[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3176
mode_lib->vba.swath_width_luma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3177
mode_lib->vba.swath_width_chroma_ub_this_state[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3178
mode_lib->vba.swath_width_chroma_ub_all_states[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3179
mode_lib->vba.SwathWidthYThisState[k] = mode_lib->vba.SwathWidthYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3180
mode_lib->vba.SwathWidthCThisState[k] = mode_lib->vba.SwathWidthCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3181
mode_lib->vba.SwathHeightYThisState[k] = mode_lib->vba.SwathHeightYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3182
mode_lib->vba.SwathHeightCThisState[k] = mode_lib->vba.SwathHeightCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3187
mode_lib->vba.DETBufferSizeInKByteThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3188
mode_lib->vba.DETBufferSizeInKByteAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3189
mode_lib->vba.DETBufferSizeYThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3190
mode_lib->vba.DETBufferSizeYAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3191
mode_lib->vba.DETBufferSizeCThisState[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3192
mode_lib->vba.DETBufferSizeCAllStates[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3257
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3260
mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3262
mode_lib->vba.DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3268
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3270
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3272
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3273
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3274
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3275
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3276
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3277
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3278
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3279
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3280
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3281
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3282
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3283
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HActive = mode_lib->vba.HActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3284
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3285
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3286
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3287
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3288
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3292
mode_lib->vba.NoTimeForPrefetch[i][j][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3295
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3298
v->DSCDelayPerState[i][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3299
v->SwathWidthYThisState[k] / v->HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3300
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3301
v->MaximumVStartup[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3305
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3306
v->MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3307
v->DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3308
v->PrefetchLinesY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3309
v->SwathWidthYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3310
v->PrefillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3311
v->MaxNumSwY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3312
v->PrefetchLinesC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3313
v->SwathWidthCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3314
v->PrefillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3315
v->MaxNumSwC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3316
v->swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3317
v->swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3318
v->SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3319
v->SwathHeightCThisState[k], v->TWait,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3325
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3326
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3327
&v->LineTimesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3328
&v->PrefetchBW[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3329
&v->LinesForMetaPTE[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3330
&v->LinesForMetaAndDPTERow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3331
&v->VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3332
&v->VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3333
&v->RequiredPrefetchPixelDataBWLuma[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3334
&v->RequiredPrefetchPixelDataBWChroma[0][0][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3335
&v->NoTimeForDynamicMetadata[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3336
&v->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3337
&v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3346
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3348
mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3349
mode_lib->vba.swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
335
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3350
mode_lib->vba.swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3351
mode_lib->vba.SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3352
mode_lib->vba.SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3353
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3355
mode_lib->vba.CursorWidth[k][0], mode_lib->vba.CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3356
mode_lib->vba.VRatioPreY[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3357
mode_lib->vba.VRatioPreC[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3358
mode_lib->vba.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3359
mode_lib->vba.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
336
if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3360
mode_lib->vba.DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3361
mode_lib->vba.DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3363
&mode_lib->vba.UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3364
&mode_lib->vba.UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3365
&mode_lib->vba.UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3366
&mode_lib->vba.NotUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3368
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3369
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPreY[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
337
v->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
339
if (mode_lib->vba.OutputFormat[k] == dm_420)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3403
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3404
if (mode_lib->vba.LineTimesForPrefetch[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3405
< 2.0 || mode_lib->vba.LinesForMetaPTE[k] >= 32.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3406
|| mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3407
|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
341
else if (mode_lib->vba.OutputFormat[k] == dm_444)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3413
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3414
if (mode_lib->vba.NoTimeForDynamicMetadata[i][j][k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3419
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3420
if (mode_lib->vba.VRatioPreY[i][j][k] > mode_lib->vba.MaxVRatioPre
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3421
|| mode_lib->vba.VRatioPreC[i][j][k] > mode_lib->vba.MaxVRatioPre
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3422
|| mode_lib->vba.NoTimeForPrefetch[i][j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3427
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3428
if (mode_lib->vba.LinesForMetaAndDPTERow[k] >= 16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3429
|| mode_lib->vba.LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
343
else if (mode_lib->vba.OutputFormat[k] == dm_n422)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3455
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3456
if (!(mode_lib->vba.ImmediateFlipRequirement[k] ==
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3460
+ mode_lib->vba.NoOfDPP[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3461
* mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3462
+ mode_lib->vba.MetaRowBytes[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3463
if (mode_lib->vba.use_one_row_for_frame_flip[i][j][k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3466
* mode_lib->vba.DPTEBytesPerRow[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
347
if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3470
+ mode_lib->vba.DPTEBytesPerRow[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3475
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
348
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3484
mode_lib->vba.PDEAndMetaPTEBytesPerFrame[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3485
mode_lib->vba.MetaRowBytes[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3486
mode_lib->vba.DPTEBytesPerRow[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3489
mode_lib->vba.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3490
(mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3491
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3492
mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3493
mode_lib->vba.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3494
mode_lib->vba.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3495
mode_lib->vba.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3496
mode_lib->vba.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3497
mode_lib->vba.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3498
mode_lib->vba.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3499
mode_lib->vba.use_one_row_for_frame_flip[i][j][k], // 24
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3502
&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3503
&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3504
&mode_lib->vba.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3505
&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
351
else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
352
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3536
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3537
if (!(mode_lib->vba.ImmediateFlipRequirement[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3539
&& (mode_lib->vba.ImmediateFlipSupportedForPipe[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
356
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3566
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3567
mode_lib->vba.use_one_row_for_frame_this_state[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3568
mode_lib->vba.use_one_row_for_frame[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3621
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3622
if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3623
if (mode_lib->vba.CursorBPP[k][0] == 64 && mode_lib->vba.Cursor64BppSupport == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
363
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3630
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3631
mode_lib->vba.AlignedYPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3632
dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3633
mode_lib->vba.MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3634
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3635
mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3636
dml_max(mode_lib->vba.DCCMetaPitchY[k], mode_lib->vba.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3637
64.0 * mode_lib->vba.Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3639
mode_lib->vba.AlignedDCCMetaPitchY[k] = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
364
v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3641
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 && mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3642
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3643
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3644
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3645
&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3646
mode_lib->vba.AlignedCPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3647
dml_max(mode_lib->vba.PitchC[k], mode_lib->vba.SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3648
mode_lib->vba.MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3649
if (mode_lib->vba.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
365
mode_lib->vba.ODMCombineEnabled[k], mode_lib->vba.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3650
mode_lib->vba.AlignedDCCMetaPitchC[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3651
dml_max(mode_lib->vba.DCCMetaPitchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3652
mode_lib->vba.SurfaceWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3653
64.0 * mode_lib->vba.Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3655
mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3658
mode_lib->vba.AlignedCPitch[k] = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3659
mode_lib->vba.AlignedDCCMetaPitchC[k] = mode_lib->vba.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
366
mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3661
if (mode_lib->vba.AlignedYPitch[k] > mode_lib->vba.PitchY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3662
|| mode_lib->vba.AlignedCPitch[k] > mode_lib->vba.PitchC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3663
|| mode_lib->vba.AlignedDCCMetaPitchY[k] > mode_lib->vba.DCCMetaPitchY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3664
|| mode_lib->vba.AlignedDCCMetaPitchC[k] > mode_lib->vba.DCCMetaPitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
367
mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3670
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3671
if (mode_lib->vba.ViewportWidth[k] > mode_lib->vba.SurfaceWidthY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3672
|| mode_lib->vba.ViewportHeight[k] > mode_lib->vba.SurfaceHeightY[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3674
if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3675
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3676
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3677
&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3678
&& mode_lib->vba.SourcePixelFormat[k] != dm_rgbe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3679
if (mode_lib->vba.ViewportWidthChroma[k] > mode_lib->vba.SurfaceWidthC[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
368
mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3680
|| mode_lib->vba.ViewportHeightChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3681
> mode_lib->vba.SurfaceHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
369
mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
370
mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3714
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3715
mode_lib->vba.MPCCombineEnable[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3716
mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3717
mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3718
mode_lib->vba.SwathHeightY[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3719
mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3720
mode_lib->vba.SwathHeightC[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3721
mode_lib->vba.SwathHeightCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3722
mode_lib->vba.DETBufferSizeInKByte[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3723
mode_lib->vba.DETBufferSizeInKByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3724
mode_lib->vba.DETBufferSizeY[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3725
mode_lib->vba.DETBufferSizeYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3726
mode_lib->vba.DETBufferSizeC[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3727
mode_lib->vba.DETBufferSizeCAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3728
mode_lib->vba.OutputType[k] = mode_lib->vba.OutputTypePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3729
mode_lib->vba.OutputRate[k] = mode_lib->vba.OutputRatePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
373
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3740
for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3741
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3742
mode_lib->vba.ODMCombineEnabled[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3743
mode_lib->vba.ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3745
mode_lib->vba.ODMCombineEnabled[k] = dm_odm_combine_mode_disabled;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3748
mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3749
mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
375
if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3750
mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
376
v->DSCDelay[k] = v->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
379
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
380
v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
381
&& (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
423
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
424
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
425
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
426
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
427
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
428
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
429
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
430
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
431
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
432
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
433
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
434
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
435
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
436
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
437
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
438
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
439
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
440
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
441
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
442
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
443
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
444
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
445
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
446
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
447
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
448
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
449
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
450
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
451
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
452
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
453
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
454
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
455
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
456
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
457
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
458
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
459
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
460
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
572
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
573
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
574
if (mode_lib->vba.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
576
+ mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
599
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
600
if (mode_lib->vba.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
601
if (mode_lib->vba.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
602
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
604
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
605
mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
606
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
607
mode_lib->vba.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
608
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
609
mode_lib->vba.WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
610
mode_lib->vba.WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
611
mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
613
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
615
if (mode_lib->vba.BlendingAndTiming[j] == k &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
617
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
618
dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
62
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
628
mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
634
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
636
if (mode_lib->vba.BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
637
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
648
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
649
dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
650
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
651
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
652
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
653
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
654
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
657
mode_lib->vba.CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
658
mode_lib->vba.CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
659
mode_lib->vba.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
660
mode_lib->vba.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
661
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
662
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
663
mode_lib->vba.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
664
mode_lib->vba.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
667
&v->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
668
&v->UrgBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
669
&v->UrgBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
670
&v->NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
672
v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
695
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
696
v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
698
dml_floor((mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
699
mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]) - dml_max(1.0,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
700
dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
701
/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
704
if (v->MaxVStartupLines[k] > 1023)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
705
v->MaxVStartupLines[k] = 1023;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
708
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
709
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, mode_lib->vba.VoltageLevel);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
711
k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
716
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
717
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
721
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
723
|| (mode_lib->vba.ImmediateFlipRequirement[k] == dm_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
748
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
754
mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
756
mode_lib->vba.DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
763
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
765
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
767
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
768
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
769
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
770
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
771
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
772
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
773
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
774
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
775
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
776
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
777
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HTotal = mode_lib->vba.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
778
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HActive = mode_lib->vba.HActive[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
779
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
780
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
781
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
782
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY = v->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
783
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC = v->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
785
v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
787
k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
790
v->DSCDelay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
791
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
792
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
793
v->MaxVStartupLines[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
797
v->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
798
v->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
799
v->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
800
v->PrefetchSourceLinesY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
801
v->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
802
v->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
803
v->MaxNumSwathY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
804
v->PrefetchSourceLinesC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
805
v->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
806
v->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
807
v->MaxNumSwathC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
808
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
809
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
810
v->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
811
v->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
819
&v->DSTXAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
820
&v->DSTYAfterScaler[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
821
&v->DestinationLinesForPrefetch[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
822
&v->PrefetchBandwidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
823
&v->DestinationLinesToRequestVMInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
824
&v->DestinationLinesToRequestRowInVBlank[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
825
&v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
826
&v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
827
&v->RequiredPrefetchPixDataBWLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
828
&v->RequiredPrefetchPixDataBWChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
829
&v->NotEnoughTimeForDynamicMetadata[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
830
&v->Tno_bw[k], &v->prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
831
&v->Tdmdl_vm[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
832
&v->Tdmdl[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
833
&v->TSetup[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
834
&v->VUpdateOffsetPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
835
&v->VUpdateWidthPix[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
836
&v->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
840
__func__, k, mode_lib->vba.ErrorResult[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
842
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
845
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
846
dml32_CalculateUrgentBurstFactor(mode_lib->vba.UsesMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
847
v->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
848
v->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
849
mode_lib->vba.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
85
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
850
mode_lib->vba.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
851
mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
854
mode_lib->vba.CursorWidth[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
855
mode_lib->vba.CursorBPP[k][0],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
856
v->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
857
v->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
858
v->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
859
v->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
86
if (mode_lib->vba.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
860
mode_lib->vba.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
861
mode_lib->vba.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
863
&v->UrgBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
864
&v->UrgBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
865
&v->UrgBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
866
&v->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
868
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
869
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
872
dml_print("DML::%s: k=%0d DPPPerSurface=%d\n", __func__, k, mode_lib->vba.DPPPerPlane[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
873
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
874
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
875
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
876
v->UrgBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
877
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
878
v->UrgBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
880
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
881
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, mode_lib->vba.VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
883
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
884
dml_print("DML::%s: k=%0d ReadBandwidthSurfaceLuma=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
885
v->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
886
dml_print("DML::%s: k=%0d ReadBandwidthSurfaceChroma=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
887
v->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
888
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
889
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
89
mode_lib->vba.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
890
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
891
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
892
v->RequiredPrefetchPixDataBWLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
893
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
894
v->RequiredPrefetchPixDataBWChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
895
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
896
dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
899
if (v->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
90
mode_lib->vba.PixelClock[k], mode_lib->vba.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
902
if (v->VRatioPrefetchY[k] > v->MaxVRatioPre
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
903
|| v->VRatioPrefetchC[k] > v->MaxVRatioPre)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
91
mode_lib->vba.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
92
mode_lib->vba.WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
93
mode_lib->vba.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
94
mode_lib->vba.WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
95
mode_lib->vba.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
958
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
959
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
96
mode_lib->vba.HTotal[k], mode_lib->vba.WritebackLineBufferSize,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
995
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
996
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1002
if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1003
DETBufferSizeInKByte[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1004
} else if (DETSizeOverride[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1005
DETBufferSizeInKByte[k] = DETSizeOverride[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1007
(ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1008
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1009
DETBufferSizeInKByte[k] = minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1011
(ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1015
dml_print("DML::%s: k=%d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1016
dml_print("DML::%s: k=%d DETSizeOverride = %d\n", __func__, k, DETSizeOverride[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1017
dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1023
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1024
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1025
TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1029
for (uint k = 0; k < NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1030
dml_print("DML::%s: k=%d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1035
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1037
if (UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1038
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1039
} else if (DETSizeOverride[k] > 0 || (((double) (ForceSingleDPP ? 1 : DPPPerSurface[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1040
(double) DETBufferSizeInKByte[k] / (double) MaxTotalDETInKByte) >=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1041
((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1042
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1044
ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1046
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1049
dml_print("DML::%s: k=%d DETPieceAssignedToThisSurfaceAlready = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1050
DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1051
dml_print("DML::%s: k=%d BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1060
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1062
dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[k] = %f\n", __func__, j, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1063
ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1064
dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[k] = %f\n", __func__, j, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1065
ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1066
dml_print("DML::%s: j=%d k=%d, ReadBandwidthLuma[Next] = %f\n", __func__, j, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1068
dml_print("DML::%s: j=%d k=%d, ReadBandwidthChroma[Next] = %f\n", __func__, j, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1070
dml_print("DML::%s: j=%d k=%d, NextSurfaceToAssignDETPiece = %d\n", __func__, j, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1073
if (!DETPieceAssignedToThisSurfaceAlready[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1075
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] <
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1078
NextSurfaceToAssignDETPiece = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1083
__func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1085
__func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1122
if (NextDETBufferPieceInKByte > nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1124
nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1125
NextDETBufferPieceInKByte = nomDETInKByte * (ForceSingleDPP ? 1 : DPPPerSurface[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1174
for (uint k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1176
__func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1562
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1564
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1565
Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1566
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1569
for (k = 0; k < NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1570
Dppclk[k] = *GlobalDPPCLK / 255 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1805
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1810
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1811
if (ViewportStationary[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1812
SurfaceSizeInMALL[k] = dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1813
dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1814
ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1815
ReadBlockWidthY[k])) * dml_min(dml_ceil(SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1816
ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1817
ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1818
dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) * BytesPerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1820
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1821
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1822
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1823
dml_floor(ViewportXStartC[k] + ViewportWidthC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1824
ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1825
dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1826
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1827
dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1828
ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1829
dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1830
BytesPerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1832
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1833
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1834
(dml_min(dml_ceil(DCCMetaPitchY[k], 8 * Read256BytesBlockWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1835
dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1836
Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1837
- dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1838
* dml_min(dml_ceil(SurfaceHeightY[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1839
Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1840
ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1841
Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1842
Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256) + (64 * 1024);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1843
if (Read256BytesBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1844
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1845
dml_min(dml_ceil(DCCMetaPitchC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1846
Read256BytesBlockWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1847
dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1848
* Read256BytesBlockWidthC[k] - 1, 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1849
Read256BytesBlockWidthC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1850
dml_floor(ViewportXStartC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1851
Read256BytesBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1852
dml_min(dml_ceil(SurfaceHeightC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1853
Read256BytesBlockHeightC[k]),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1854
dml_floor(ViewportYStartC[k] + ViewportHeightC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1855
8 * Read256BytesBlockHeightC[k] - 1, 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1856
Read256BytesBlockHeightC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1857
dml_floor(ViewportYStartC[k], 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1858
Read256BytesBlockHeightC[k])) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1859
BytesPerPixelC[k] / 256;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1863
SurfaceSizeInMALL[k] = dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1864
ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1865
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1866
ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1867
BytesPerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1868
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1869
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1870
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1871
ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1872
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1873
ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1874
BytesPerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1876
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1877
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1878
(dml_ceil(dml_min(DCCMetaPitchY[k], ViewportWidthY[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1879
Read256BytesBlockWidthY[k] - 1), 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1880
Read256BytesBlockWidthY[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1881
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1882
Read256BytesBlockHeightY[k] - 1), 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1883
Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256) + (64 * 1024);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1885
if (Read256BytesBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1886
SurfaceSizeInMALL[k] = SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1887
dml_ceil(dml_min(DCCMetaPitchC[k], ViewportWidthC[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1888
Read256BytesBlockWidthC[k] - 1), 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1889
Read256BytesBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1890
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1891
Read256BytesBlockHeightC[k] - 1), 8 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1892
Read256BytesBlockHeightC[k]) *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1893
BytesPerPixelC[k] / 256;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1899
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1901
if (UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1902
TotalSurfaceSizeInMALLForSubVP = TotalSurfaceSizeInMALLForSubVP + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1903
else if (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1904
TotalSurfaceSizeInMALLForSS = TotalSurfaceSizeInMALLForSS + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1975
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1992
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1994
vm_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1995
dpte_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1997
vm_group_bytes[k] = 2048;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1998
if (GPUVMMinPageSizeKBytes[k] >= 64 && IsVertical(myPipe[k].SourceRotation))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
1999
dpte_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2001
dpte_group_bytes[k] = 2048;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2003
vm_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2004
dpte_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2007
if (myPipe[k].SourcePixelFormat == dm_420_8 || myPipe[k].SourcePixelFormat == dm_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2008
myPipe[k].SourcePixelFormat == dm_420_12 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2009
myPipe[k].SourcePixelFormat == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2010
if ((myPipe[k].SourcePixelFormat == dm_420_10 || myPipe[k].SourcePixelFormat == dm_420_12) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2011
!IsVertical(myPipe[k].SourceRotation)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2012
PTEBufferSizeInRequestsForLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2014
PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsForLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2016
PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2017
PTEBufferSizeInRequestsForChroma[k] = PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2021
myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2022
myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2023
myPipe[k].DPPPerSurface,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2024
myPipe[k].BlockHeight256BytesC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2025
myPipe[k].BlockWidth256BytesC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2026
myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2027
myPipe[k].SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2028
myPipe[k].BytePerPixelC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2029
myPipe[k].SourceRotation,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2030
SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2031
myPipe[k].ViewportHeightChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2032
myPipe[k].ViewportXStartC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2033
myPipe[k].ViewportYStartC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2038
GPUVMMinPageSizeKBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2040
PTEBufferSizeInRequestsForChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2041
myPipe[k].PitchC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2042
myPipe[k].DCCMetaPitchC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2043
myPipe[k].BlockWidthC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2044
myPipe[k].BlockHeightC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2047
&MetaRowByteC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2048
&PixelPTEBytesPerRowC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2049
&dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2050
&dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2051
&dpte_row_height_linear_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2052
&PixelPTEBytesPerRowC_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2053
&dpte_row_width_chroma_ub_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2054
&dpte_row_height_chroma_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2055
&meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2056
&meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2057
&meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2058
&meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2059
&PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2060
&PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2061
&PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2062
&dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2063
&meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2065
PrefetchSourceLinesC[k] = dml32_CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2066
myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2067
myPipe[k].VTapsChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2068
myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2069
myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2070
myPipe[k].SwathHeightC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2071
myPipe[k].SourceRotation,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2072
myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2073
SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2074
myPipe[k].ViewportHeightChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2075
myPipe[k].ViewportXStartC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2076
myPipe[k].ViewportYStartC,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2079
&VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2080
&MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2082
PTEBufferSizeInRequestsForLuma[k] = PTEBufferSizeInRequestsLuma + PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2083
PTEBufferSizeInRequestsForChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2084
PixelPTEBytesPerRowC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2086
MetaRowByteC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2087
MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2088
PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2089
dpte_row_height_chroma_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2090
dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2091
PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2095
myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2096
myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2097
myPipe[k].DPPPerSurface,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2098
myPipe[k].BlockHeight256BytesY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2099
myPipe[k].BlockWidth256BytesY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2100
myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2101
myPipe[k].SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2102
myPipe[k].BytePerPixelY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2103
myPipe[k].SourceRotation,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2104
SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2105
myPipe[k].ViewportHeight,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2106
myPipe[k].ViewportXStart,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2107
myPipe[k].ViewportYStart,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2112
GPUVMMinPageSizeKBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2114
PTEBufferSizeInRequestsForLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2115
myPipe[k].PitchY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2116
myPipe[k].DCCMetaPitchY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2117
myPipe[k].BlockWidthY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2118
myPipe[k].BlockHeightY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2121
&MetaRowByteY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2122
&PixelPTEBytesPerRowY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2123
&dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2124
&dpte_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2125
&dpte_row_height_linear_luma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2126
&PixelPTEBytesPerRowY_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2127
&dpte_row_width_luma_ub_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2128
&dpte_row_height_luma_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2129
&meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2130
&meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2131
&meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2132
&meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2133
&PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2134
&PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2135
&PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2136
&dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2137
&meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2139
PrefetchSourceLinesY[k] = dml32_CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2140
myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2141
myPipe[k].VTaps,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2142
myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2143
myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2144
myPipe[k].SwathHeightY,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2145
myPipe[k].SourceRotation,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2146
myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2147
SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2148
myPipe[k].ViewportHeight,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2149
myPipe[k].ViewportXStart,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2150
myPipe[k].ViewportYStart,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2153
&VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2154
&MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2156
PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2157
MetaRowByte[k] = MetaRowByteY[k] + MetaRowByteC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2159
if (PixelPTEBytesPerRowY[k] <= 64 * PTEBufferSizeInRequestsForLuma[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2160
PixelPTEBytesPerRowC[k] <= 64 * PTEBufferSizeInRequestsForChroma[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2161
PTEBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2163
PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2166
one_row_per_frame_fits_in_buffer[k] = (PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2167
PTEBufferSizeInRequestsForLuma[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2168
PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * PTEBufferSizeInRequestsForChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2180
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2181
PTE_BUFFER_MODE[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2182
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2183
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2184
(GPUVMMinPageSizeKBytes[k] > 64);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2185
BIGK_FRAGMENT_SIZE[k] = dml_log2(GPUVMMinPageSizeKBytes[k] * 1024) - 12;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2188
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2190
dml_print("DML::%s: k=%d, SurfaceSizeInMALL = %d\n", __func__, k, SurfaceSizeInMALL[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2191
dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2193
use_one_row_for_frame[k] = myPipe[k].FORCE_ONE_ROW_FOR_FRAME || UsesMALLForStaticScreen[k] ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2194
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport) ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2195
(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2196
(GPUVMMinPageSizeKBytes[k] > 64 && IsVertical(myPipe[k].SourceRotation));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2198
use_one_row_for_frame_flip[k] = use_one_row_for_frame[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2199
!(UseMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2201
if (use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2202
dpte_row_height_luma[k] = dpte_row_height_luma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2203
dpte_row_width_luma_ub[k] = dpte_row_width_luma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2204
PixelPTEBytesPerRowY[k] = PixelPTEBytesPerRowY_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2205
dpte_row_height_chroma[k] = dpte_row_height_chroma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2206
dpte_row_width_chroma_ub[k] = dpte_row_width_chroma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2207
PixelPTEBytesPerRowC[k] = PixelPTEBytesPerRowC_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2208
PTEBufferSizeNotExceeded[k] = one_row_per_frame_fits_in_buffer[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2211
if (MetaRowByte[k] <= DCCMetaBufferSizeBytes)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2212
DCCMetaBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2214
DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2216
PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY[k] + PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2217
if (use_one_row_for_frame[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2218
PixelPTEBytesPerRow[k] = PixelPTEBytesPerRow[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2222
myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2223
myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2224
myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2225
myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2226
myPipe[k].HTotal / myPipe[k].PixelClock,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2227
MetaRowByteY[k], MetaRowByteC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2228
meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2229
meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2230
PixelPTEBytesPerRowY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2231
PixelPTEBytesPerRowC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2232
dpte_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2233
dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2236
&meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2237
&dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2239
dml_print("DML::%s: k=%d, use_one_row_for_frame = %d\n", __func__, k, use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2241
__func__, k, use_one_row_for_frame_flip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2243
__func__, k, UseMALLForPStateChange[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2244
dml_print("DML::%s: k=%d, dpte_row_height_luma = %d\n", __func__, k, dpte_row_height_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2246
__func__, k, dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2247
dml_print("DML::%s: k=%d, PixelPTEBytesPerRowY = %d\n", __func__, k, PixelPTEBytesPerRowY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2249
__func__, k, dpte_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2251
__func__, k, dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2252
dml_print("DML::%s: k=%d, PixelPTEBytesPerRowC = %d\n", __func__, k, PixelPTEBytesPerRowC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2253
dml_print("DML::%s: k=%d, PixelPTEBytesPerRow = %d\n", __func__, k, PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2255
__func__, k, PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2256
dml_print("DML::%s: k=%d, PTE_BUFFER_MODE = %d\n", __func__, k, PTE_BUFFER_MODE[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2257
dml_print("DML::%s: k=%d, BIGK_FRAGMENT_SIZE = %d\n", __func__, k, BIGK_FRAGMENT_SIZE[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2618
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2624
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2625
UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dm_use_mall_static_screen_enable);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2626
if (UsesMALLForStaticScreen[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2627
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2629
dml_print("DML::%s: k=%d, UsesMALLForStaticScreen = %d\n", __func__, k, UsesMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2630
dml_print("DML::%s: k=%d, TotalSurfaceSizeInMALL = %d\n", __func__, k, TotalSurfaceSizeInMALL);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2638
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2639
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2640
!UsesMALLForStaticScreen[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2641
UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2642
one_row_per_frame_fits_in_buffer[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2644
SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2646
SurfaceToAddToMALL = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2649
__func__, k, UseMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2831
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2837
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2839
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2840
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2841
/ PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2843
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2845
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2848
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2849
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2850
DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2852
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2853
/ Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2857
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2858
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2859
BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2860
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2863
DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2866
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2869
dml_print("DML::%s: k=%d, PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2870
dml_print("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2874
for (k = 0; k < NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2875
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2886
for (k = 0; k < NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2887
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
2980
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3003
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3005
+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3006
/ (15.75 * HTotal[k] / PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3009
for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3010
NoOfDPPState[k] = NoOfDPP[i][j][k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3022
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3026
PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3027
* swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3028
+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3029
* BytePerPixelC[k]) / NormalEfficiency
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3031
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3032
+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3035
+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3037
+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3038
+ PixelDCFCLKCyclesRequiredInPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3039
PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3040
* HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3041
DynamicMetadataVMExtraLatency[k] = (GPUVMEnable == true &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3042
DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3047
UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3049
DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3055
PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3060
DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3065
ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k] / (PrefetchTime *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3066
PixelDCFCLKCyclesRequiredInPrefetch[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3068
DCFCLKRequiredForPeakBandwidthPerSurface[k] = NoOfDPPState[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3069
PixelDCFCLKCyclesRequiredInPrefetch[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3070
PrefetchPixelLinesTime[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3074
DCFCLKRequiredForPeakBandwidthPerSurface[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3075
DCFCLKRequiredForPeakBandwidthPerSurface[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3076
NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3080
DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3082
if (DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3091
RequiredDPPCLKPerSurface[i][j][k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3094
PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3095
HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3096
VTotal[k] - VActive[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3097
DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3098
DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3099
Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3110
AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3111
PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3112
TdmecPipe - TdmsksPipe - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3114
DCFCLKRequiredForPeakBandwidthPerSurface[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3115
dml_max(DCFCLKRequiredForPeakBandwidthPerSurface[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3118
DCFCLKRequiredForPeakBandwidthPerSurface[k] = DCFCLKPerState[i];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3122
for (k = 0; k <= NumberOfActiveSurfaces - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3124
DCFCLKRequiredForPeakBandwidthPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3129
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3132
MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3133
PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3134
if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3140
PrefetchPixelLinesTime[k] / 4),
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3142
PixelDCFCLKCyclesRequiredInPrefetch[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3166
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3185
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3186
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3401
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3507
v->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3508
v->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3531
if (v->DynamicMetadataEnable[k] == false)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3535
if (v->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3555
*Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3591
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4290
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4354
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4355
if (v->WritebackEnable[k] == true)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4398
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4399
TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4400
SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) / (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4403
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4405
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4406
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4410
dml_print("DML::%s: k=%d, v->MaxLineBufferLines = %d\n", __func__, k, v->MaxLineBufferLines);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4411
dml_print("DML::%s: k=%d, v->LineBufferSizeFinal = %d\n", __func__, k, v->LineBufferSizeFinal);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4412
dml_print("DML::%s: k=%d, v->LBBitPerPixel = %d\n", __func__, k, v->LBBitPerPixel[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4413
dml_print("DML::%s: k=%d, v->HRatio = %f\n", __func__, k, v->HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4414
dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4417
EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4418
EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4419
EffectiveDETBufferSizeY = DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4424
* (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4425
/ (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4428
LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4429
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4430
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4433
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4437
- (1.0 - 1.0 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4438
/ v->PixelClock[k] / v->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4441
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4442
LinesInDETC[k] = DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4443
LinesInDETCRoundedDownToSwath[k] = dml_floor(LinesInDETC[k], SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4444
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4445
/ v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4447
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4448
/ v->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4451
- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightC[k] * v->HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4452
/ v->PixelClock[k] / v->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4460
ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4462
ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4464
USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.USRRetrainingWatermark;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4466
if (v->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4468
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4469
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4470
if (v->WritebackPixelFormat[k] == dm_444_64)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4479
ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4481
ActiveFCLKChangeLatencyMargin[k] = dml_min(ActiveFCLKChangeLatencyMargin[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4484
MaxActiveDRAMClockChangeLatencySupported[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4485
(v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4487
(ActiveDRAMClockChangeLatencyMargin[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4508
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4509
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4511
ActiveFCLKChangeLatencyMargin[k] < MinActiveFCLKChangeMargin)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4513
MinActiveFCLKChangeMargin = ActiveFCLKChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4514
SurfaceWithMinActiveFCLKChangeMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4521
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4522
if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4523
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4525
ActiveFCLKChangeLatencyMargin[k] <
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4527
SecondMinActiveFCLKChangeMarginOneDisplayInVBLank = ActiveFCLKChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4543
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4544
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4545
(USRRetrainingLatencyMargin[k] < 0)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4550
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4551
if (v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4552
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4553
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4554
ActiveDRAMClockChangeLatencyMargin[k] < 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4559
LastSurfaceWithoutMargin = k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4561
!SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4567
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4568
if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4570
else if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4597
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4603
dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4604
src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4605
src_y_ahead_l = dml_floor(DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k], SwathHeightY[k]) + LBLatencyHidingSourceLinesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4606
sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4609
dml_print("DML::%s: k=%d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4610
dml_print("DML::%s: k=%d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4611
dml_print("DML::%s: k=%d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4612
dml_print("DML::%s: k=%d, SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4613
dml_print("DML::%s: k=%d, LBLatencyHidingSourceLinesY = %d\n", __func__, k, LBLatencyHidingSourceLinesY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4614
dml_print("DML::%s: k=%d, dst_y_pstate = %d\n", __func__, k, dst_y_pstate);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4615
dml_print("DML::%s: k=%d, src_y_pstate_l = %d\n", __func__, k, src_y_pstate_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4616
dml_print("DML::%s: k=%d, src_y_ahead_l = %d\n", __func__, k, src_y_ahead_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4617
dml_print("DML::%s: k=%d, v->meta_row_height = %d\n", __func__, k, v->meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4618
dml_print("DML::%s: k=%d, sub_vp_lines_l = %d\n", __func__, k, sub_vp_lines_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4620
SubViewportLinesNeededInMALL[k] = sub_vp_lines_l;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4622
if (BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4623
src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4624
src_y_ahead_c = dml_floor(DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k], SwathHeightC[k]) + LBLatencyHidingSourceLinesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4625
sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4626
SubViewportLinesNeededInMALL[k] = dml_max(sub_vp_lines_l, sub_vp_lines_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4629
dml_print("DML::%s: k=%d, src_y_pstate_c = %d\n", __func__, k, src_y_pstate_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4630
dml_print("DML::%s: k=%d, src_y_ahead_c = %d\n", __func__, k, src_y_ahead_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4631
dml_print("DML::%s: k=%d, v->meta_row_height_chroma = %d\n", __func__, k, v->meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4632
dml_print("DML::%s: k=%d, sub_vp_lines_c = %d\n", __func__, k, sub_vp_lines_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
468
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4728
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4730
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4733
dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4734
dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4735
dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4736
dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4737
dml_print("DML::%s: k=%d : swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4738
dml_print("DML::%s: k=%d : swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4739
dml_print("DML::%s: k=%d : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4740
dml_print("DML::%s: k=%d : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4741
dml_print("DML::%s: k=%d : DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4742
dml_print("DML::%s: k=%d : PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4743
dml_print("DML::%s: k=%d : Dppclk = %f\n", __func__, k, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4746
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4747
DisplayPipeLineDeliveryTimeLuma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4748
swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4750
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4753
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4754
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4756
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4757
DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4758
swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4760
DisplayPipeLineDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4761
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4765
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4766
DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4767
swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4769
DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4770
swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4773
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4774
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4776
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4777
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4778
DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4780
DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4781
swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4786
__func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4788
__func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4790
__func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4792
__func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4796
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4797
if (!IsVertical(SourceRotation[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4798
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4800
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4802
dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4805
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4806
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4807
DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4808
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4809
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4810
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4812
if (!IsVertical(SourceRotation[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4813
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4815
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4817
dml_print("DML::%s: k=%d : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4819
DisplayPipeRequestDeliveryTimeChroma[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4820
DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4821
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4822
DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4826
__func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4828
__func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4830
__func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4832
__func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4836
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4839
cursor_req_per_width = dml_ceil((double) CursorWidth[k][0] * (double) CursorBPP[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4841
if (NumberOfCursors[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4842
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4843
CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4844
HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4846
CursorRequestDeliveryTime[k] = (double) CursorWidth[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4847
PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4849
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4850
CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4851
HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4853
CursorRequestDeliveryTimePrefetch[k] = (double) CursorWidth[k][0] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4854
PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4857
CursorRequestDeliveryTime[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4858
CursorRequestDeliveryTimePrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4862
__func__, k, NumberOfCursors[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4864
__func__, k, CursorRequestDeliveryTime[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4866
__func__, k, CursorRequestDeliveryTimePrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4941
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4943
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4944
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4945
if (BytePerPixelC[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4946
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4948
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4949
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4950
if (BytePerPixelC[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4951
DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4953
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4956
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4957
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4958
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4959
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4960
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4961
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4962
if (!IsVertical(SourceRotation[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4963
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4965
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4972
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4973
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4974
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4975
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4976
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4977
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4978
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4979
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4980
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4981
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4983
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4984
meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4985
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4986
meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4987
meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4989
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4990
if (!IsVertical(SourceRotation[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4992
meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4995
meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5002
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5003
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5004
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5005
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5006
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5007
HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5010
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5011
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5012
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5013
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5014
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5015
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5019
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5021
if (!IsVertical(SourceRotation[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5022
dpte_group_width_luma = (double) dpte_group_bytes[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5023
(double) PTERequestSizeY[k] * PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5025
dpte_group_width_luma = (double) dpte_group_bytes[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5026
(double) PTERequestSizeY[k] * PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5029
if (use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5030
dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5033
dpte_groups_per_row_luma_ub = dml_ceil((double) dpte_row_width_luma_ub[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5038
__func__, k, use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5040
__func__, k, dpte_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5042
__func__, k, PTERequestSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5044
__func__, k, PixelPTEReqWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5046
__func__, k, PixelPTEReqHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5048
__func__, k, dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5050
__func__, k, dpte_group_width_luma);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5052
__func__, k, dpte_groups_per_row_luma_ub);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5055
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5056
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5057
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5058
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5059
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5060
HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5061
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5062
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5063
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5064
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5066
if (!IsVertical(SourceRotation[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5067
dpte_group_width_chroma = (double) dpte_group_bytes[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5068
(double) PTERequestSizeC[k] * PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5070
dpte_group_width_chroma = (double) dpte_group_bytes[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5071
(double) PTERequestSizeC[k] * PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5074
if (use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5075
dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5078
dpte_groups_per_row_chroma_ub = dml_ceil((double) dpte_row_width_chroma_ub[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5083
__func__, k, dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5085
__func__, k, dpte_group_width_chroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5087
__func__, k, dpte_groups_per_row_chroma_ub);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5089
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5090
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5091
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5092
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5093
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5094
HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5097
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5098
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5099
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5100
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5101
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5102
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5106
__func__, k, DestinationLinesToRequestRowInVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5108
__func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5110
__func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5112
__func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5114
__func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5116
__func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5118
__func__, k, TimePerMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5120
__func__, k, TimePerMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5122
__func__, k, TimePerMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5124
__func__, k, TimePerChromaMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5126
__func__, k, TimePerChromaMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5128
__func__, k, TimePerChromaMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5130
__func__, k, time_per_pte_group_nom_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5132
__func__, k, time_per_pte_group_vblank_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5134
__func__, k, time_per_pte_group_flip_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5136
__func__, k, time_per_pte_group_nom_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5138
__func__, k, time_per_pte_group_vblank_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5140
__func__, k, time_per_pte_group_flip_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
515
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
516
RoundedUpMaxSwathSizeBytesY[k] = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5169
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
517
RoundedUpMaxSwathSizeBytesC[k] = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5177
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5180
dml_print("DML::%s: k=%0d, DCCEnable = %d\n", __func__, k, DCCEnable[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5181
dml_print("DML::%s: k=%0d, vm_group_bytes = %d\n", __func__, k, vm_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5183
__func__, k, dpde0_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5185
__func__, k, dpde0_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5187
__func__, k, meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5189
__func__, k, meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
519
dml_print("DML::%s: k=%0d DPPPerSurface = %d\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5192
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5193
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5194
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5196
(double) (dpde0_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5197
(double) (vm_group_bytes[k]), 1.0) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5198
dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5199
(double) (vm_group_bytes[k]), 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
520
dml_print("DML::%s: k=%0d swath_width_luma_ub = %d\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5202
(double) (dpde0_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5203
(double) (vm_group_bytes[k]), 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5207
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5209
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
521
dml_print("DML::%s: k=%0d BytePerPixDETY = %f\n", __func__, k, BytePerPixDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5210
(double) (vm_group_bytes[k]), 1.0) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5211
dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5212
(double) (vm_group_bytes[k]), 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5215
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5216
(double) (vm_group_bytes[k]), 1.0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5219
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
522
dml_print("DML::%s: k=%0d MaximumSwathHeightY = %d\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5221
(double) (dpde0_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5222
(double) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5223
dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5224
(double) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5225
dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5226
(double) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5227
dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5228
(double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
523
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5231
(double) (dpde0_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5232
(double) (vm_group_bytes[k]), 1) + dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5233
(double) (meta_pte_bytes_per_frame_ub_l[k]) /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5234
(double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5239
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
524
RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5240
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5241
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5242
dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5244
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5248
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5249
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
525
dml_print("DML::%s: k=%0d swath_width_chroma_ub = %d\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5250
meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5252
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5255
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5256
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5257
64 + dpde0_bytes_per_frame_ub_c[k] / 64 +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5258
meta_pte_bytes_per_frame_ub_l[k] / 64 +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5259
meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
526
dml_print("DML::%s: k=%0d BytePerPixDETC = %f\n", __func__, k, BytePerPixDETC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5261
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] /
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5262
64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5267
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5268
HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5269
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
527
dml_print("DML::%s: k=%0d MaximumSwathHeightC = %d\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5270
HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5271
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5272
HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5273
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] *
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5274
HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5277
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5278
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5279
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
528
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5280
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5284
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5285
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5286
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5287
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
529
RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5291
dml_print("DML::%s: k=%0d, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5292
dml_print("DML::%s: k=%0d, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5293
dml_print("DML::%s: k=%0d, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5294
dml_print("DML::%s: k=%0d, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
532
if (SourcePixelFormat[k] == dm_420_10) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
533
RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
534
RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
538
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
539
TotalActiveDPP = TotalActiveDPP + (ForceSingleDPP ? 1 : DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
540
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
541
SourcePixelFormat[k] == dm_420_12 || SourcePixelFormat[k] == dm_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5689
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5696
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5697
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5698
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5699
if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5700
|| (!IsVertical(SourceRotation[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5701
&& BlockHeight256BytesY[k] > SwathHeightY[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5702
|| DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5708
+ ReadBandwidthSurfaceLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5709
/ dml_min(NetDCCRateLuma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5713
__func__, k, ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5715
__func__, k, NetDCCRateLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5717
__func__, k, MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5720
+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5722
+ ReadBandwidthSurfaceLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5725
if (ReadBandwidthSurfaceChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5726
if ((IsVertical(SourceRotation[k]) && BlockWidth256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5727
|| (!IsVertical(SourceRotation[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5728
&& BlockHeight256BytesC[k] > SwathHeightC[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5729
|| DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5736
+ ReadBandwidthSurfaceChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5737
/ dml_min(NetDCCRateChroma[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5741
__func__, k, ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5743
__func__, k, NetDCCRateChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5745
__func__, k, MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5748
+ ReadBandwidthSurfaceChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5749
* DCCFractionOfZeroSizeRequestsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5751
+ ReadBandwidthSurfaceChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5752
* DCCFractionOfZeroSizeRequestsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5757
+ ReadBandwidthSurfaceLuma[k] + ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5760
+ DPPPerSurface[k] * (meta_row_bw[k] + dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5835
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5836
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5837
LinesInDETY = ((double) DETBufferSizeY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5839
* ReadBandwidthSurfaceLuma[k] / TotalDataReadBandwidth)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5840
/ BytePerPixelDETY[k] / SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5841
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5842
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((double) HTotal[k] / PixelClock[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5843
/ VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5845
dml_print("DML::%s: k=%0d, DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5846
dml_print("DML::%s: k=%0d, BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5847
dml_print("DML::%s: k=%0d, SwathWidthY = %d\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5849
__func__, k, ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5850
dml_print("DML::%s: k=%0d, TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5851
dml_print("DML::%s: k=%0d, LinesInDETY = %f\n", __func__, k, LinesInDETY);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5853
__func__, k, LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5854
dml_print("DML::%s: k=%0d, HTotal = %d\n", __func__, k, HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5855
dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5856
dml_print("DML::%s: k=%0d, VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5857
dml_print("DML::%s: k=%0d, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5858
dml_print("DML::%s: k=%0d, PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5862
bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5868
dml_floor((double) VTotal[k] / 2.0, 1.0) : VTotal[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5869
* (double) HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5872
dml_floor((double) VActive[k] / 2.0, 1.0) : VActive[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5873
* (double) HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5874
BytePerPixelYCriticalSurface = BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5875
SwathWidthYCriticalSurface = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5876
SwathHeightYCriticalSurface = SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5877
BlockWidth256BytesYCriticalSurface = BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5878
LinesToFinishSwathTransferStutterCriticalSurface = SwathHeightY[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5880
DETBufferSizeYCriticalSurface = DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5881
MinTTUVBlankCriticalSurface = MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5882
doublePlaneCriticalSurface = (ReadBandwidthSurfaceChroma[k] == 0);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5883
doublePipeCriticalSurface = (DPPPerSurface[k] == 1);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5887
__func__, k, FoundCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5889
__func__, k, *StutterPeriod);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5891
__func__, k, MinTTUVBlankCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5893
__func__, k, FrameTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5895
__func__, k, VActiveTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5897
__func__, k, BytePerPixelYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5899
__func__, k, SwathWidthYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5901
__func__, k, SwathHeightYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5903
__func__, k, BlockWidth256BytesYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5905
__func__, k, doublePlaneCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5907
__func__, k, doublePipeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5909
__func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5958
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5959
if (WritebackEnable[k])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
596
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
598
DETBufferSizeInKByteForSwathCalculation = (UseMALLForPStateChange[k] ==
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
599
dm_use_mall_pstate_change_phantom_pipe ? 1024 : DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5996
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5997
if (UseMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
5998
if (BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6000
doublePixelClock = PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6001
doubleHTotal = HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6002
doubleVTotal = VTotal[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6003
} else if (doublePixelClock != PixelClock[k] || doubleHTotal != HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6004
|| doubleVTotal != VTotal[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
601
dml_print("DML::%s: k=%0d DETBufferSizeInKByteForSwathCalculation = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
605
if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
607
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
608
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
609
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
610
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
611
} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
612
RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6122
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6127
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6128
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6133
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6134
VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
614
SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
615
SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
616
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
617
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6176
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
618
} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6182
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6183
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6189
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
619
RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <=
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6190
ActiveBandwidthPerSurface = ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6194
TotalPrefetchBandwidth = TotalPrefetchBandwidth + PrefetchBW[k] * VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6196
*MaxPrefetchBandwidth = *MaxPrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6198
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
621
SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
622
SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6225
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6228
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6229
CalculateBandwidthAvailableForImmediateFlip_val = CalculateBandwidthAvailableForImmediateFlip_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
623
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6230
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
624
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
626
SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6262
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6264
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6265
if (ImmediateFlipRequirement[k] != dm_immediate_flip_not_required) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6266
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6267
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6268
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
627
SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6270
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6271
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6272
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
628
RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
629
RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6298
int k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6312
for (k = 0; k < NumberOfActiveSurfaces; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6313
SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6315
if (SwathHeightC[k] != 0)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6316
SwathSizePerSurfaceC[k] = SwathHeightC[k] * SwathWidthC[k] * BytePerPixelInDETC[k] * NumOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6318
SwathSizePerSurfaceC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
632
if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 >
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6320
SwathSizeAllSurfaces += SwathSizePerSurfaceY[k] + SwathSizePerSurfaceC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6326
for (k = 0; k < NumberOfActiveSurfaces; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6327
double LineTime = HTotal[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6330
if (UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6331
DETSwathLatencyHidingYUs = (dml_floor(DETBufferSizeY[k] / BytePerPixelInDETY[k] / SwathWidthY[k], 1.0) - SwathHeightY[k]) / VRatioY[k] * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6333
if (SwathHeightC[k] != 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
6334
DETSwathLatencyHidingCUs = (dml_floor(DETBufferSizeC[k] / BytePerPixelInDETC[k] / SwathWidthC[k], 1.0) - SwathHeightC[k]) / VRatioC[k] * LineTime;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
634
|| SwathWidth[k] > MaximumSwathWidthLuma[k] || (SwathHeightC[k] > 0 &&
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
635
SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
637
ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
639
ViewportSizeSupportPerSurface[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
642
if (SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
644
dml_print("DML::%s: k=%0d All DET for plane0\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
646
DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
647
DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
650
dml_print("DML::%s: k=%0d Half DET for plane0, half for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
652
DETBufferSizeY[k] = DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
653
DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
656
dml_print("DML::%s: k=%0d 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
658
DETBufferSizeY[k] = dml_floor(DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
659
DETBufferSizeC[k] = DETBufferSizeInKByte[k] * 1024 - DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
663
dml_print("DML::%s: k=%0d SwathHeightY = %d\n", __func__, k, SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
664
dml_print("DML::%s: k=%0d SwathHeightC = %d\n", __func__, k, SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
666
k, RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
668
k, RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
669
dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesY = %d\n", __func__, k, RoundedUpSwathSizeBytesY);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
670
dml_print("DML::%s: k=%0d RoundedUpSwathSizeBytesC = %d\n", __func__, k, RoundedUpSwathSizeBytesC);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
671
dml_print("DML::%s: k=%0d DETBufferSizeInKByte = %d\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
672
dml_print("DML::%s: k=%0d DETBufferSizeY = %d\n", __func__, k, DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
673
dml_print("DML::%s: k=%0d DETBufferSizeC = %d\n", __func__, k, DETBufferSizeC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
674
dml_print("DML::%s: k=%0d ViewportSizeSupportPerSurface = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
675
ViewportSizeSupportPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
719
unsigned int k, j;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
732
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
733
if (!IsVertical(SourceRotation[k]))
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
734
SwathWidthdoubleDPPY[k] = ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
736
SwathWidthdoubleDPPY[k] = ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
739
dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
740
dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
743
MainSurfaceODMMode = ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
745
if (BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
750
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
753
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
754
dml_round(HActive[k] / 4.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
756
SwathWidthY[k] = dml_min(SwathWidthdoubleDPPY[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
757
dml_round(HActive[k] / 2.0 * HRatio[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
758
} else if (DPPPerSurface[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
759
SwathWidthY[k] = SwathWidthdoubleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
761
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
766
dml_print("DML::%s: k=%d HActive=%d\n", __func__, k, HActive[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
767
dml_print("DML::%s: k=%d HRatio=%f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
768
dml_print("DML::%s: k=%d MainSurfaceODMMode=%d\n", __func__, k, MainSurfaceODMMode);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
769
dml_print("DML::%s: k=%d SwathWidthdoubleDPPY=%d\n", __func__, k, SwathWidthdoubleDPPY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
770
dml_print("DML::%s: k=%d SwathWidthY=%d\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
773
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
774
SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
775
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
776
SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
778
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
779
SwathWidthdoubleDPPC[k] = SwathWidthdoubleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
783
SwathWidthY[k] = SwathWidthdoubleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
784
SwathWidthC[k] = SwathWidthdoubleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
787
surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
788
surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
790
if (!IsVertical(SourceRotation[k])) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
791
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
792
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
793
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
794
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
795
dml_floor(ViewportXStart[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
796
SwathWidthY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
797
Read256BytesBlockWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
798
Read256BytesBlockWidthY[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
799
dml_floor(ViewportXStart[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
800
Read256BytesBlockWidthY[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
802
swath_width_luma_ub[k] = dml_min(surface_width_ub_l,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
803
dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
804
Read256BytesBlockWidthY[k]) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
805
Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
807
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
808
surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
809
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
810
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
811
dml_floor(ViewportXStartC[k] + SwathWidthC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
812
Read256BytesBlockWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
813
Read256BytesBlockWidthC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
814
dml_floor(ViewportXStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
815
Read256BytesBlockWidthC[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
817
swath_width_chroma_ub[k] = dml_min(surface_width_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
818
dml_ceil(SwathWidthC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
819
Read256BytesBlockWidthC[k]) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
820
Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
823
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
826
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
827
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
829
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
830
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
831
SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
832
Read256BytesBlockHeightY[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
833
dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
835
swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
836
Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
838
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
839
surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
840
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
841
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
842
dml_floor(ViewportYStartC[k] + SwathWidthC[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
843
Read256BytesBlockHeightC[k] - 1,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
844
Read256BytesBlockHeightC[k]) -
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
845
dml_floor(ViewportYStartC[k],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
846
Read256BytesBlockHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
848
swath_width_chroma_ub[k] = dml_min(surface_height_ub_c,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
849
dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
850
Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
853
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
858
dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
859
dml_print("DML::%s: k=%d surface_height_ub_l=%0d\n", __func__, k, surface_height_ub_l);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
860
dml_print("DML::%s: k=%d surface_width_ub_c=%0d\n", __func__, k, surface_width_ub_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
861
dml_print("DML::%s: k=%d surface_height_ub_c=%0d\n", __func__, k, surface_height_ub_c);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
862
dml_print("DML::%s: k=%d Read256BytesBlockWidthY=%0d\n", __func__, k, Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
863
dml_print("DML::%s: k=%d Read256BytesBlockHeightY=%0d\n", __func__, k, Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
864
dml_print("DML::%s: k=%d Read256BytesBlockWidthC=%0d\n", __func__, k, Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
865
dml_print("DML::%s: k=%d Read256BytesBlockHeightC=%0d\n", __func__, k, Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
866
dml_print("DML::%s: k=%d ViewportStationary=%0d\n", __func__, k, ViewportStationary[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
867
dml_print("DML::%s: k=%d DPPPerSurface=%0d\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
868
dml_print("DML::%s: k=%d swath_width_luma_ub=%0d\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
869
dml_print("DML::%s: k=%d swath_width_chroma_ub=%0d\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
870
dml_print("DML::%s: k=%d MaximumSwathHeightY=%0d\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
871
dml_print("DML::%s: k=%d MaximumSwathHeightC=%0d\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
938
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
964
for (k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
965
DETBufferSizeInKByte[k] = nomDETInKByte;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
966
if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
967
SourcePixelFormat[k] == dm_420_12) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
977
if (2.0 * ((double) RoundedUpMaxSwathSizeBytesY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
978
(double) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
984
dml_print("DML::%s: k=%0d minDET = %d\n", __func__, k, minDET);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
985
dml_print("DML::%s: k=%0d max_minDET = %d\n", __func__, k, max_minDET);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
986
dml_print("DML::%s: k=%0d minDET_pipe = %d\n", __func__, k, minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
987
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesY = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
988
RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
989
dml_print("DML::%s: k=%0d RoundedUpMaxSwathSizeBytesC = %d\n", __func__, k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
990
RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
994
minDET_pipe = dml_max(128, dml_ceil(((double)RoundedUpMaxSwathSizeBytesY[k] +
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
995
(double)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, 64));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
998
__func__, k, minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
723
unsigned int k,
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
304
unsigned int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
306
for (k = 0; k < num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
307
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c
308
pipe_index_in_combine[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
280
for (int k = start_index; k < end_index; k++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
281
if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
sys/dev/pci/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
282
swap_table_entries(&table[k], &table[k+1]);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1050
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1053
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1054
mode_lib->vba.PixelClockBackEnd[k] = mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1055
if (mode_lib->vba.Interlace[k] == 1
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1057
mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1079
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1101
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1102
pipe_idx = get_pipe_idx(mode_lib, k);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1107
total_pipes += mode_lib->vba.DPPPerPlane[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1110
mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
1112
mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
221
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
224
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
225
immediate_flip_bw += mode_lib->vba.ImmediateFlipBW[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
234
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
238
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
239
total_prefetch_bw += mode_lib->vba.PrefetchBandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
248
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
251
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
252
size += mode_lib->vba.SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
521
unsigned int j, k;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
526
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
527
visited[k] = false;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
742
for (k = 0; k < DC__NUM_CURSOR__MAX; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
743
switch (k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
783
for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
784
display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
785
display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
787
if (src_k->is_hsplit && !visited[k]
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
789
mode_lib->vba.pipe_plane[k] =
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
809
visited[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
843
for (k = j + 1; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
844
if (!PlaneVisited[k] && OTGInstPlane[j] == OTGInstPlane[k]) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
848
mode_lib->vba.BlendingAndTiming[k] = j;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
849
PlaneVisited[k] = true;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
865
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
866
if (pipes[k].pipe.src.unbounded_req_mode == 0)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
872
for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
873
ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
881
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
882
mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].pipe.src.vm;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
884
(pipes[k].pipe.src.gpuvm_levels_force_en
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
886
< pipes[k].pipe.src.gpuvm_levels_force) ?
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
887
pipes[k].pipe.src.gpuvm_levels_force :
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
890
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable || !!pipes[k].pipe.src.hostvm || !!pipes[k].pipe.src.vm;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
892
(pipes[k].pipe.src.hostvm_levels_force_en
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
894
< pipes[k].pipe.src.hostvm_levels_force) ?
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
895
pipes[k].pipe.src.hostvm_levels_force :
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
908
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
909
mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
910
mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
912
if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
913
if (mode_lib->vba.ForceOneRowForFrame[k] ||
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
914
(mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) ||
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
915
(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) ||
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
916
(mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) {
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
919
__func__, mode_lib->vba.PteBufferMode[k], k);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
921
__func__, mode_lib->vba.ForceOneRowForFrame[k]);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
923
__func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
925
__func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
927
__func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
949
int k = 0;
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
951
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++)
sys/dev/pci/drm/amd/display/dc/dml/display_mode_vba.c
952
mode_lib->vba.CachedActiveDRAMClockChangeLatencyMargin[k] = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10133
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
10134
clk_cfg.dppclk_option[k] = dml_use_required_freq;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2698
for (dml_uint_t k = 0; k < num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2699
display_cfg->output.PixelClockBackEnd[k] = display_cfg->timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2700
if (display_cfg->timing.Interlace[k] == 1 && ptoi_supported == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2701
display_cfg->timing.PixelClock[k] = 2 * display_cfg->timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2853
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2854
if (p->WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2890
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2891
s->TotalPixelBW = s->TotalPixelBW + p->DPPPerSurface[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2892
* (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * p->VRatio[k] + p->SwathWidthC[k] * p->BytePerPixelDETC[k] * p->VRatioChroma[k]) / (p->HTotal[k] / p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2895
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2897
s->LBLatencyHidingSourceLinesY[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthY[k] / dml_max(p->HRatio[k], 1.0)), 1)) - (p->VTaps[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2898
s->LBLatencyHidingSourceLinesC[k] = (dml_uint_t)(dml_min((dml_float_t)p->MaxLineBufferLines, dml_floor((dml_float_t)p->LineBufferSize / (dml_float_t)p->LBBitPerPixel[k] / ((dml_float_t)p->SwathWidthC[k] / dml_max(p->HRatioChroma[k], 1.0)), 1)) - (p->VTapsChroma[k] - 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2902
dml_print("DML::%s: k=%u, MaxLineBufferLines = %u\n", __func__, k, p->MaxLineBufferLines);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2903
dml_print("DML::%s: k=%u, LineBufferSize = %u\n", __func__, k, p->LineBufferSize);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2904
dml_print("DML::%s: k=%u, LBBitPerPixel = %u\n", __func__, k, p->LBBitPerPixel[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2905
dml_print("DML::%s: k=%u, HRatio = %f\n", __func__, k, p->HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2906
dml_print("DML::%s: k=%u, VTaps = %u\n", __func__, k, p->VTaps[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2909
s->EffectiveLBLatencyHidingY = s->LBLatencyHidingSourceLinesY[k] / p->VRatio[k] * (p->HTotal[k] / p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2910
s->EffectiveLBLatencyHidingC = s->LBLatencyHidingSourceLinesC[k] / p->VRatioChroma[k] * (p->HTotal[k] / p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2912
s->EffectiveDETBufferSizeY = p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2914
s->EffectiveDETBufferSizeY = s->EffectiveDETBufferSizeY + p->CompressedBufferSizeInkByte * 1024 * (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * p->VRatio[k]) / (p->HTotal[k] / p->PixelClock[k]) / s->TotalPixelBW;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2917
s->LinesInDETY[k] = (dml_float_t)s->EffectiveDETBufferSizeY / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2918
s->LinesInDETYRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETY[k], p->SwathHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2919
s->FullDETBufferingTimeY = s->LinesInDETYRoundedDownToSwath[k] * (p->HTotal[k] / p->PixelClock[k]) / p->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2921
s->ActiveClockChangeLatencyHidingY = s->EffectiveLBLatencyHidingY + s->FullDETBufferingTimeY - ((dml_float_t)p->DSTXAfterScaler[k] / (dml_float_t)p->HTotal[k] + (dml_float_t)p->DSTYAfterScaler[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2924
s->ActiveClockChangeLatencyHidingY = s->ActiveClockChangeLatencyHidingY - (1.0 - 1.0 / (dml_float_t)p->NumberOfActiveSurfaces) * (dml_float_t)p->SwathHeightY[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k] / p->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2927
if (p->BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2928
s->LinesInDETC[k] = p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2929
s->LinesInDETCRoundedDownToSwath[k] = (dml_uint_t)(dml_floor(s->LinesInDETC[k], p->SwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2930
s->FullDETBufferingTimeC = s->LinesInDETCRoundedDownToSwath[k] * (p->HTotal[k] / p->PixelClock[k]) / p->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2931
s->ActiveClockChangeLatencyHidingC = s->EffectiveLBLatencyHidingC + s->FullDETBufferingTimeC - ((dml_float_t)p->DSTXAfterScaler[k] / (dml_float_t)p->HTotal[k] + (dml_float_t)p->DSTYAfterScaler[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2933
s->ActiveClockChangeLatencyHidingC = s->ActiveClockChangeLatencyHidingC - (1.0 - 1.0 / (dml_float_t)p->NumberOfActiveSurfaces) * (dml_float_t)p->SwathHeightC[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k] / p->VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2940
s->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->UrgentWatermark - p->Watermark->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2941
s->ActiveFCLKChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->UrgentWatermark - p->Watermark->FCLKChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2942
s->USRRetrainingLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->USRRetrainingWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2944
if (p->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2945
s->WritebackLatencyHiding = (dml_float_t)p->WritebackInterfaceBufferSize * 1024.0 / ((dml_float_t)p->WritebackDestinationWidth[k] * (dml_float_t)p->WritebackDestinationHeight[k] / ((dml_float_t)p->WritebackSourceHeight[k] * (dml_float_t)p->HTotal[k] / p->PixelClock[k]) * 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2946
if (p->WritebackPixelFormat[k] == dml_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2953
s->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(s->ActiveDRAMClockChangeLatencyMargin[k], s->WritebackFCLKChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2954
s->ActiveFCLKChangeLatencyMargin[k] = dml_min(s->ActiveFCLKChangeLatencyMargin[k], s->WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2956
p->MaxActiveDRAMClockChangeLatencySupported[k] = (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2957
p->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2961
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2962
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && (s->USRRetrainingLatencyMargin[k] < 0)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2968
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2969
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && ((!s->FoundCriticalSurface)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2970
|| ((s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency) < *p->MaxActiveFCLKChangeLatencySupported))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2972
*p->MaxActiveFCLKChangeLatencySupported = s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2992
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2993
if ((p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) && (s->ActiveFCLKChangeLatencyMargin[k] < 0)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2994
if (!(p->PrefetchMode[k] <= 1)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2997
s->FCLKChangeSupportNumber = ((p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2998
s->LastSurfaceWithoutMargin = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
2999
} else if (((s->FCLKChangeSupportNumber == 1) && (p->DRRDisplay[k] || (!s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k]))) || (s->FCLKChangeSupportNumber == 2))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3013
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3014
if (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3016
else if (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3021
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3022
if (((s->DRAMClockChangeMethod == 0) && (s->ActiveDRAMClockChangeLatencyMargin[k] < 0)) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3023
((s->DRAMClockChangeMethod == 1) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_full_frame)) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3024
((s->DRAMClockChangeMethod == 2) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_sub_viewport) && (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3025
if (p->PrefetchMode[k] != 0) { // Don't need to support DRAM clock change, PrefetchMode 0 means needs DRAM clock change support
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3028
s->DRAMClockChangeSupportNumber = (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3029
s->LastSurfaceWithoutMargin = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3030
} else if (((s->DRAMClockChangeSupportNumber == 1) && (p->DRRDisplay[k] || !s->SynchronizedSurfaces[s->LastSurfaceWithoutMargin][k])) || (s->DRAMClockChangeSupportNumber == 2)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3068
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3069
s->dst_y_pstate = (dml_uint_t)(dml_ceil((p->mmSOCParameters.DRAMClockChangeLatency + p->mmSOCParameters.UrgentLatency) / (p->HTotal[k] / p->PixelClock[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3070
s->src_y_pstate_l = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatio[k], p->SwathHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3071
s->src_y_ahead_l = (dml_uint_t)(dml_floor(p->DETBufferSizeY[k] / p->BytePerPixelDETY[k] / p->SwathWidthY[k], p->SwathHeightY[k]) + s->LBLatencyHidingSourceLinesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3072
s->sub_vp_lines_l = s->src_y_pstate_l + s->src_y_ahead_l + p->meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3075
dml_print("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3076
dml_print("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3077
dml_print("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3078
dml_print("DML::%s: k=%u, SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3079
dml_print("DML::%s: k=%u, LBLatencyHidingSourceLinesY = %u\n", __func__, k, s->LBLatencyHidingSourceLinesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3080
dml_print("DML::%s: k=%u, dst_y_pstate = %u\n", __func__, k, s->dst_y_pstate);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3081
dml_print("DML::%s: k=%u, src_y_pstate_l = %u\n", __func__, k, s->src_y_pstate_l);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3082
dml_print("DML::%s: k=%u, src_y_ahead_l = %u\n", __func__, k, s->src_y_ahead_l);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3083
dml_print("DML::%s: k=%u, meta_row_height = %u\n", __func__, k, p->meta_row_height[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3084
dml_print("DML::%s: k=%u, sub_vp_lines_l = %u\n", __func__, k, s->sub_vp_lines_l);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3086
p->SubViewportLinesNeededInMALL[k] = s->sub_vp_lines_l;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3088
if (p->BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3089
s->src_y_pstate_c = (dml_uint_t)(dml_ceil(s->dst_y_pstate * p->VRatioChroma[k], p->SwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3090
s->src_y_ahead_c = (dml_uint_t)(dml_floor(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3091
s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3092
p->SubViewportLinesNeededInMALL[k] = (dml_uint_t)(dml_max(s->sub_vp_lines_l, s->sub_vp_lines_c));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3095
dml_print("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3096
dml_print("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3097
dml_print("DML::%s: k=%u, meta_row_height_chroma = %u\n", __func__, k, p->meta_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3098
dml_print("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3138
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3140
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3141
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3143
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3145
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3148
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3149
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3151
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3155
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3156
DCFClkDeepSleepPerSurface[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3157
__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3159
DCFClkDeepSleepPerSurface[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3161
DCFClkDeepSleepPerSurface[k] = dml_max(DCFClkDeepSleepPerSurface[k], PixelClock[k] / 16);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3164
dml_print("DML::%s: k=%u, PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3165
dml_print("DML::%s: k=%u, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3169
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3170
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3182
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3183
*DCFClkDeepSleep = dml_max(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3305
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3308
dml_print("DML::%s: k=%u : HRatio = %f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3309
dml_print("DML::%s: k=%u : VRatio = %f\n", __func__, k, VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3310
dml_print("DML::%s: k=%u : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3311
dml_print("DML::%s: k=%u : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3312
dml_print("DML::%s: k=%u : swath_width_luma_ub = %u\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3313
dml_print("DML::%s: k=%u : swath_width_chroma_ub = %u\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3314
dml_print("DML::%s: k=%u : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3315
dml_print("DML::%s: k=%u : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3316
dml_print("DML::%s: k=%u : DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3317
dml_print("DML::%s: k=%u : PixelClock = %f\n", __func__, k, PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3318
dml_print("DML::%s: k=%u : Dppclk = %f\n", __func__, k, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3321
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3322
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3324
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3327
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3328
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3330
if (VRatioChroma[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3331
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3333
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3337
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3338
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerSurface[k] / HRatio[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3340
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3343
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3344
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3346
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3347
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerSurface[k] / HRatioChroma[k] / PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3349
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3353
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3354
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3355
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3356
dml_print("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3360
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3361
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3362
req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3364
req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3367
dml_print("DML::%s: k=%u : req_per_swath_ub = %f (Luma)\n", __func__, k, req_per_swath_ub);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3370
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3371
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3372
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3373
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3374
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3376
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3377
req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3379
req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3382
dml_print("DML::%s: k=%u : req_per_swath_ub = %f (Chroma)\n", __func__, k, req_per_swath_ub);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3384
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3385
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3388
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3389
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3390
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3391
dml_print("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3395
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3397
cursor_req_per_width = (dml_uint_t)(dml_ceil((dml_float_t) CursorWidth[k] * (dml_float_t) CursorBPP[k] / 256.0 / 8.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3398
if (NumberOfCursors[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3399
if (VRatio[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3400
CursorRequestDeliveryTime[k] = (dml_float_t) CursorWidth[k] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3402
CursorRequestDeliveryTime[k] = (dml_float_t) CursorWidth[k] / PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3404
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3405
CursorRequestDeliveryTimePrefetch[k] = (dml_float_t) CursorWidth[k] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3407
CursorRequestDeliveryTimePrefetch[k] = (dml_float_t) CursorWidth[k] / PSCL_THROUGHPUT[k] / Dppclk[k] / cursor_req_per_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3410
CursorRequestDeliveryTime[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3411
CursorRequestDeliveryTimePrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3414
dml_print("DML::%s: k=%u : NumberOfCursors = %u\n", __func__, k, NumberOfCursors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3415
dml_print("DML::%s: k=%u : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3416
dml_print("DML::%s: k=%u : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3492
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3493
DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3494
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3495
DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3497
DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3499
DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3500
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3501
DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3503
DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3507
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3508
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3509
meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3510
min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3511
meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3512
meta_row_remainder = meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3513
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3514
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3516
meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3523
TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3524
TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3525
TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3526
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3527
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3528
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3529
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3531
meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3532
min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3533
meta_chunk_per_row_int_chroma = (dml_uint_t)((dml_float_t) meta_row_width_chroma[k] / meta_chunk_width_chroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3534
meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3535
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3536
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3538
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3545
TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3546
TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3547
TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3550
TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3551
TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3552
TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3553
TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3554
TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3555
TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3559
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3561
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3562
dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3564
dpte_group_width_luma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeY[k] * PixelPTEReqHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3567
if (use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3568
dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma / 2.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3570
dpte_groups_per_row_luma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_luma_ub[k] / (dml_float_t) dpte_group_width_luma, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3573
dml_print("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3574
dml_print("DML::%s: k=%u, dpte_group_bytes = %u\n", __func__, k, dpte_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3575
dml_print("DML::%s: k=%u, PTERequestSizeY = %u\n", __func__, k, PTERequestSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3576
dml_print("DML::%s: k=%u, PixelPTEReqWidthY = %u\n", __func__, k, PixelPTEReqWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3577
dml_print("DML::%s: k=%u, PixelPTEReqHeightY = %u\n", __func__, k, PixelPTEReqHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3578
dml_print("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3579
dml_print("DML::%s: k=%u, dpte_group_width_luma = %u\n", __func__, k, dpte_group_width_luma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3580
dml_print("DML::%s: k=%u, dpte_groups_per_row_luma_ub = %u\n", __func__, k, dpte_groups_per_row_luma_ub);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3582
time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3583
time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3584
time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3585
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3586
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3587
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3588
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3590
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3591
dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3593
dpte_group_width_chroma = (dml_uint_t)((dml_float_t) dpte_group_bytes[k] / (dml_float_t) PTERequestSizeC[k] * PixelPTEReqHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3596
if (use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3597
dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma / 2.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3599
dpte_groups_per_row_chroma_ub = (dml_uint_t)(dml_ceil((dml_float_t) dpte_row_width_chroma_ub[k] / (dml_float_t) dpte_group_width_chroma, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3601
dml_print("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3602
dml_print("DML::%s: k=%u, dpte_group_width_chroma = %u\n", __func__, k, dpte_group_width_chroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3603
dml_print("DML::%s: k=%u, dpte_groups_per_row_chroma_ub = %u\n", __func__, k, dpte_groups_per_row_chroma_ub);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3605
time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3606
time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3607
time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3610
time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3611
time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3612
time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3613
time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3614
time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3615
time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3618
dml_print("DML::%s: k=%u, DestinationLinesToRequestRowInVBlank = %f\n", __func__, k, DestinationLinesToRequestRowInVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3619
dml_print("DML::%s: k=%u, DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, k, DestinationLinesToRequestRowInImmediateFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3621
dml_print("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_L = %f\n", __func__, k, DST_Y_PER_PTE_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3622
dml_print("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_C = %f\n", __func__, k, DST_Y_PER_PTE_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3623
dml_print("DML::%s: k=%u, DST_Y_PER_META_ROW_NOM_L = %f\n", __func__, k, DST_Y_PER_META_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3624
dml_print("DML::%s: k=%u, DST_Y_PER_META_ROW_NOM_C = %f\n", __func__, k, DST_Y_PER_META_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3625
dml_print("DML::%s: k=%u, TimePerMetaChunkNominal = %f\n", __func__, k, TimePerMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3626
dml_print("DML::%s: k=%u, TimePerMetaChunkVBlank = %f\n", __func__, k, TimePerMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3627
dml_print("DML::%s: k=%u, TimePerMetaChunkFlip = %f\n", __func__, k, TimePerMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3628
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkNominal = %f\n", __func__, k, TimePerChromaMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3629
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkVBlank = %f\n", __func__, k, TimePerChromaMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3630
dml_print("DML::%s: k=%u, TimePerChromaMetaChunkFlip = %f\n", __func__, k, TimePerChromaMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3631
dml_print("DML::%s: k=%u, time_per_pte_group_nom_luma = %f\n", __func__, k, time_per_pte_group_nom_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3632
dml_print("DML::%s: k=%u, time_per_pte_group_vblank_luma = %f\n", __func__, k, time_per_pte_group_vblank_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3633
dml_print("DML::%s: k=%u, time_per_pte_group_flip_luma = %f\n", __func__, k, time_per_pte_group_flip_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3634
dml_print("DML::%s: k=%u, time_per_pte_group_nom_chroma = %f\n", __func__, k, time_per_pte_group_nom_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3635
dml_print("DML::%s: k=%u, time_per_pte_group_vblank_chroma = %f\n", __func__, k, time_per_pte_group_vblank_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3636
dml_print("DML::%s: k=%u, time_per_pte_group_flip_chroma = %f\n", __func__, k, time_per_pte_group_flip_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3672
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3675
dml_print("DML::%s: k=%u, DCCEnable = %u\n", __func__, k, DCCEnable[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3676
dml_print("DML::%s: k=%u, vm_group_bytes = %u\n", __func__, k, vm_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3677
dml_print("DML::%s: k=%u, dpde0_bytes_per_frame_ub_l = %u\n", __func__, k, dpde0_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3678
dml_print("DML::%s: k=%u, dpde0_bytes_per_frame_ub_c = %u\n", __func__, k, dpde0_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3679
dml_print("DML::%s: k=%u, meta_pte_bytes_per_frame_ub_l = %u\n", __func__, k, meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3680
dml_print("DML::%s: k=%u, meta_pte_bytes_per_frame_ub_c = %u\n", __func__, k, meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3683
if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3684
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3685
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3686
num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3687
dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_c[k] / (dml_float_t) vm_group_bytes[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3689
num_group_per_lower_vm_stage = (dml_uint_t) (dml_ceil((dml_float_t) dpde0_bytes_per_frame_ub_l[k] / (dml_float_t) vm_group_bytes[k], 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3693
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3694
num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3695
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3697
num_group_per_lower_vm_stage = (dml_uint_t)(dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3700
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3701
num_group_per_lower_vm_stage = (dml_uint_t)(2.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3702
dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3703
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3704
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_c[k]) / (dml_float_t) (vm_group_bytes[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3706
num_group_per_lower_vm_stage = (dml_uint_t)(1.0 + dml_ceil((dml_float_t) (dpde0_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3707
dml_ceil((dml_float_t) (meta_pte_bytes_per_frame_ub_l[k]) / (dml_float_t) (vm_group_bytes[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3712
if (DCCEnable[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3713
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3714
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3716
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3720
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3721
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3723
num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3726
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3727
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3729
num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3734
TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3735
TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3736
TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3737
TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3740
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3741
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3742
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3743
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3747
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3748
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3749
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3750
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3754
dml_print("DML::%s: k=%u, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3755
dml_print("DML::%s: k=%u, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3756
dml_print("DML::%s: k=%u, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3757
dml_print("DML::%s: k=%u, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3813
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3814
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3815
if (p->DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3816
if ((dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockWidth256BytesY[k] > p->SwathHeightY[k]) || (!dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockHeight256BytesY[k] > p->SwathHeightY[k]) || p->DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3821
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] / dml_min(p->NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3823
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3824
dml_print("DML::%s: k=%u, NetDCCRateLuma = %f\n", __func__, k, p->NetDCCRateLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3825
dml_print("DML::%s: k=%u, MaximumEffectiveCompressionLuma = %f\n", __func__, k, MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3827
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->DCCFractionOfZeroSizeRequestsLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3828
TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3830
if (p->ReadBandwidthSurfaceChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3831
if ((dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockWidth256BytesC[k] > p->SwathHeightC[k]) || (!dml_is_vertical_rotation(p->SourceScan[k]) && p->BlockHeight256BytesC[k] > p->SwathHeightC[k]) || p->DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3836
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] / dml_min(p->NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3838
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, p->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3839
dml_print("DML::%s: k=%u, NetDCCRateChroma = %f\n", __func__, k, p->NetDCCRateChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3840
dml_print("DML::%s: k=%u, MaximumEffectiveCompressionChroma = %f\n", __func__, k, MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3842
TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->DCCFractionOfZeroSizeRequestsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3843
TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3846
TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] + p->ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3848
TotalRowReadBandwidth = TotalRowReadBandwidth + p->DPPPerSurface[k] * (p->meta_row_bw[k] + p->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3903
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3904
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3905
LinesInDETY = ((dml_float_t)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3906
LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3907
DETBufferingTimeY = LinesInDETYRoundedDownToSwath * ((dml_float_t)p->HTotal[k] / p->PixelClock[k]) / p->VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3909
dml_print("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3910
dml_print("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3911
dml_print("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3912
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3913
dml_print("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, p->TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3914
dml_print("DML::%s: k=%u, LinesInDETY = %f\n", __func__, k, LinesInDETY);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3915
dml_print("DML::%s: k=%u, LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3916
dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, p->HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3917
dml_print("DML::%s: k=%u, PixelClock = %f\n", __func__, k, p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3918
dml_print("DML::%s: k=%u, VRatio = %f\n", __func__, k, p->VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3919
dml_print("DML::%s: k=%u, DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3920
dml_print("DML::%s: k=%u,PixelClock = %f\n", __func__, k, p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3924
dml_bool_t isInterlaceTiming = p->Interlace[k] && !p->ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3928
FrameTimeCriticalSurface = (isInterlaceTiming ? dml_floor((dml_float_t)p->VTotal[k]/2.0, 1.0) : p->VTotal[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3929
VActiveTimeCriticalSurface = (isInterlaceTiming ? dml_floor((dml_float_t)p->VActive[k]/2.0, 1.0) : p->VActive[k]) * (dml_float_t)p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3930
BytePerPixelYCriticalSurface = p->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3931
SwathWidthYCriticalSurface = p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3932
SwathHeightYCriticalSurface = p->SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3933
BlockWidth256BytesYCriticalSurface = p->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3934
LinesToFinishSwathTransferStutterCriticalSurface = p->SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3935
DETBufferSizeYCriticalSurface = p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3936
MinTTUVBlankCriticalSurface = p->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3937
SinglePlaneCriticalSurface = (p->ReadBandwidthSurfaceChroma[k] == 0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3938
SinglePipeCriticalSurface = (p->DPPPerSurface[k] == 1);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3941
dml_print("DML::%s: k=%u, FoundCriticalSurface = %u\n", __func__, k, FoundCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3942
dml_print("DML::%s: k=%u, StutterPeriod = %f\n", __func__, k, *p->StutterPeriod);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3943
dml_print("DML::%s: k=%u, MinTTUVBlankCriticalSurface = %f\n", __func__, k, MinTTUVBlankCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3944
dml_print("DML::%s: k=%u, FrameTimeCriticalSurface = %f\n", __func__, k, FrameTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3945
dml_print("DML::%s: k=%u, VActiveTimeCriticalSurface = %f\n", __func__, k, VActiveTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3946
dml_print("DML::%s: k=%u, BytePerPixelYCriticalSurface = %u\n", __func__, k, BytePerPixelYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3947
dml_print("DML::%s: k=%u, SwathWidthYCriticalSurface = %f\n", __func__, k, SwathWidthYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3948
dml_print("DML::%s: k=%u, SwathHeightYCriticalSurface = %f\n", __func__, k, SwathHeightYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3949
dml_print("DML::%s: k=%u, BlockWidth256BytesYCriticalSurface = %u\n", __func__, k, BlockWidth256BytesYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3950
dml_print("DML::%s: k=%u, SinglePlaneCriticalSurface = %u\n", __func__, k, SinglePlaneCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3951
dml_print("DML::%s: k=%u, SinglePipeCriticalSurface = %u\n", __func__, k, SinglePipeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3952
dml_print("DML::%s: k=%u, LinesToFinishSwathTransferStutterCriticalSurface = %f\n", __func__, k, LinesToFinishSwathTransferStutterCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3985
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
3986
if (p->WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4016
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4017
if (p->UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4018
if (p->BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4020
SinglePixelClock = p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4021
SingleHTotal = p->HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4022
SingleVTotal = p->VTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4023
} else if (SinglePixelClock != p->PixelClock[k] || SingleHTotal != p->HTotal[k] || SingleVTotal != p->VTotal[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4108
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4109
dml_print("DML::%s: DPPPerSurface[%u] = %u\n", __func__, k, p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4149
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4150
RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(p->swath_width_luma_ub[k] * p->BytePerPixDETY[k] * MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4151
RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(p->swath_width_chroma_ub[k] * p->BytePerPixDETC[k] * MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4153
dml_print("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4154
dml_print("DML::%s: k=%u swath_width_luma_ub = %u\n", __func__, k, p->swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4155
dml_print("DML::%s: k=%u BytePerPixDETY = %f\n", __func__, k, p->BytePerPixDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4156
dml_print("DML::%s: k=%u MaximumSwathHeightY = %u\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4157
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4158
dml_print("DML::%s: k=%u swath_width_chroma_ub = %u\n", __func__, k, p->swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4159
dml_print("DML::%s: k=%u BytePerPixDETC = %f\n", __func__, k, p->BytePerPixDETC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4160
dml_print("DML::%s: k=%u MaximumSwathHeightC = %u\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4161
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4163
if (p->SourcePixelFormat[k] == dml_420_10) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4164
RoundedUpMaxSwathSizeBytesY[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesY[k], 256));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4165
RoundedUpMaxSwathSizeBytesC[k] = (dml_uint_t)(dml_ceil((dml_float_t) RoundedUpMaxSwathSizeBytesC[k], 256));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4169
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4170
TotalActiveDPP = TotalActiveDPP + (p->ForceSingleDPP ? 1 : p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4171
if (p->DPPPerSurface[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4172
SurfaceDoingUnboundedRequest = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4173
if (p->SourcePixelFormat[k] == dml_420_8 || p->SourcePixelFormat[k] == dml_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4174
p->SourcePixelFormat[k] == dml_420_12 || p->SourcePixelFormat[k] == dml_rgbe_alpha
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4175
|| p->SurfaceTiling[k] == dml_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4215
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4217
DETBufferSizeInKByteForSwathCalculation = (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe ? 1024 : p->DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4219
dml_print("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation = %u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4222
if (RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4223
p->SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4224
p->SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4225
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4226
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4227
} else if (RoundedUpMaxSwathSizeBytesY[k] >= 1.5 * RoundedUpMaxSwathSizeBytesC[k] && RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4228
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4229
p->SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4230
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4231
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4232
} else if (RoundedUpMaxSwathSizeBytesY[k] < 1.5 * RoundedUpMaxSwathSizeBytesC[k] && RoundedUpMaxSwathSizeBytesY[k] + RoundedUpMaxSwathSizeBytesC[k] / 2 <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4233
p->SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4234
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4235
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4236
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4238
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4239
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4240
RoundedUpSwathSizeBytesY[k] = RoundedUpMaxSwathSizeBytesY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4241
RoundedUpSwathSizeBytesC[k] = RoundedUpMaxSwathSizeBytesC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4244
if ((RoundedUpMaxSwathSizeBytesY[k] / 2 + RoundedUpMaxSwathSizeBytesC[k] / 2 > DETBufferSizeInKByteForSwathCalculation * 1024 / 2) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4245
p->SwathWidth[k] > p->MaximumSwathWidthLuma[k] || (p->SwathHeightC[k] > 0 && p->SwathWidthChroma[k] > p->MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4247
p->ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4249
p->ViewportSizeSupportPerSurface[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4252
if (p->SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4254
dml_print("DML::%s: k=%u All DET for plane0\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4256
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4257
p->DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4258
} else if (RoundedUpSwathSizeBytesY[k] <= 1.5 * RoundedUpSwathSizeBytesC[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4260
dml_print("DML::%s: k=%u Half DET for plane0, half for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4262
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4263
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4266
dml_print("DML::%s: k=%u 2/3 DET for plane0, 1/3 for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4268
p->DETBufferSizeY[k] = (dml_uint_t)(dml_floor(p->DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4269
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 - p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4273
dml_print("DML::%s: k=%u SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4274
dml_print("DML::%s: k=%u SwathHeightC = %u\n", __func__, k, p->SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4275
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4276
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4277
dml_print("DML::%s: k=%u RoundedUpSwathSizeBytesY = %u\n", __func__, k, RoundedUpSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4278
dml_print("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4279
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, p->DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4280
dml_print("DML::%s: k=%u DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4281
dml_print("DML::%s: k=%u DETBufferSizeC = %u\n", __func__, k, p->DETBufferSizeC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4282
dml_print("DML::%s: k=%u ViewportSizeSupportPerSurface = %u\n", __func__, k, p->ViewportSizeSupportPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4345
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4346
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4347
SwathWidthSingleDPPY[k] = ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4349
SwathWidthSingleDPPY[k] = ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4353
dml_print("DML::%s: k=%u ViewportWidth=%u\n", __func__, k, ViewportWidth[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4354
dml_print("DML::%s: k=%u ViewportHeight=%u\n", __func__, k, ViewportHeight[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4355
dml_print("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4358
MainSurfaceODMMode = ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4360
if (BlendingAndTiming[k] == j) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4366
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4369
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k], true)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4371
SwathWidthY[k] = (dml_uint_t)(dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k], true)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4372
} else if (DPPPerSurface[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4373
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4375
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4380
dml_print("DML::%s: k=%u HActive=%u\n", __func__, k, HActive[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4381
dml_print("DML::%s: k=%u HRatio=%f\n", __func__, k, HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4382
dml_print("DML::%s: k=%u MainSurfaceODMMode=%u\n", __func__, k, MainSurfaceODMMode);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4383
dml_print("DML::%s: k=%u SwathWidthSingleDPPY=%u\n", __func__, k, SwathWidthSingleDPPY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4384
dml_print("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4387
if (SourcePixelFormat[k] == dml_420_8 || SourcePixelFormat[k] == dml_420_10 || SourcePixelFormat[k] == dml_420_12) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4388
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4389
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4391
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4392
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4396
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4397
SwathWidthC[k] = SwathWidthSingleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4400
surface_width_ub_l = (dml_uint_t)dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4401
surface_height_ub_l = (dml_uint_t)dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4403
if (!dml_is_vertical_rotation(SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4404
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4405
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4406
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4407
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_floor(ViewportXStart[k] + SwathWidthY[k] + Read256BytesBlockWidthY[k] - 1, Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStart[k], Read256BytesBlockWidthY[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4409
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4411
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4412
surface_width_ub_c = (dml_uint_t)dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4413
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4414
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_floor(ViewportXStartC[k] + SwathWidthC[k] + Read256BytesBlockWidthC[k] - 1, Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], Read256BytesBlockWidthC[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4416
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_width_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4419
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4422
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4423
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4425
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4426
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_floor(ViewportYStart[k] + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStart[k], Read256BytesBlockHeightY[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4428
swath_width_luma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_l, dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4430
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4431
surface_height_ub_c = (dml_uint_t)dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4432
if (ViewportStationary[k] && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4433
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_floor(ViewportYStartC[k] + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], Read256BytesBlockHeightC[k])));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4435
swath_width_chroma_ub[k] = (dml_uint_t)(dml_min(surface_height_ub_c, dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4438
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4443
dml_print("DML::%s: k=%u surface_width_ub_l=%u\n", __func__, k, surface_width_ub_l);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4444
dml_print("DML::%s: k=%u surface_height_ub_l=%u\n", __func__, k, surface_height_ub_l);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4445
dml_print("DML::%s: k=%u surface_width_ub_c=%u\n", __func__, k, surface_width_ub_c);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4446
dml_print("DML::%s: k=%u surface_height_ub_c=%u\n", __func__, k, surface_height_ub_c);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4447
dml_print("DML::%s: k=%u Read256BytesBlockWidthY=%u\n", __func__, k, Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4448
dml_print("DML::%s: k=%u Read256BytesBlockHeightY=%u\n", __func__, k, Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4449
dml_print("DML::%s: k=%u Read256BytesBlockWidthC=%u\n", __func__, k, Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4450
dml_print("DML::%s: k=%u Read256BytesBlockHeightC=%u\n", __func__, k, Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4451
dml_print("DML::%s: k=%u ViewportStationary=%u\n", __func__, k, ViewportStationary[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4452
dml_print("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4453
dml_print("DML::%s: k=%u swath_width_luma_ub=%u\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4454
dml_print("DML::%s: k=%u swath_width_chroma_ub=%u\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4455
dml_print("DML::%s: k=%u MaximumSwathHeightY=%u\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4456
dml_print("DML::%s: k=%u MaximumSwathHeightC=%u\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4550
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4551
ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4607
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4608
s->TotalMaxPrefetchFlipDPTERowBandwidth[j] = s->TotalMaxPrefetchFlipDPTERowBandwidth[j] + p->NoOfDPP[j][k] * p->DPTEBytesPerRow[j][k] / (15.75 * p->HTotal[k] / p->PixelClock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4611
for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4612
s->NoOfDPPState[k] = p->NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4623
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4627
s->PixelDCFCLKCyclesRequiredInPrefetch[k] = (p->PrefetchLinesY[j][k] * p->swath_width_luma_ub_all_states[j][k] * p->BytePerPixelY[k] + p->PrefetchLinesC[j][k] * p->swath_width_chroma_ub_all_states[j][k] * p->BytePerPixelC[k]) / s->NormalEfficiency / p->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4628
DCFCLKCyclesRequiredInPrefetch = 2 * s->ExtraLatencyCycles / s->NoOfDPPState[k] + p->PDEAndMetaPTEBytesPerFrame[j][k] / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth * (p->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * p->DPTEBytesPerRow[j][k] / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth + 2 * p->MetaRowBytes[j][k] / s->NormalEfficiency / p->ReturnBusWidth + s->PixelDCFCLKCyclesRequiredInPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4629
s->PrefetchPixelLinesTime[k] = dml_max(p->PrefetchLinesY[j][k], p->PrefetchLinesC[j][k]) * p->HTotal[k] / p->PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4630
s->DynamicMetadataVMExtraLatency[k] = (p->GPUVMEnable == true && p->DynamicMetadataEnable[k] == true && p->DynamicMetadataVMEnabled == true) ? p->UrgLatency * p->GPUVMMaxPageTableLevels * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4633
p->UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4635
p->DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4641
PrefetchTime = (p->MaximumVStartup[j][k] - 1) * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - p->UrgLatency * ((p->GPUVMMaxPageTableLevels <= 2 ? p->GPUVMMaxPageTableLevels : p->GPUVMMaxPageTableLevels - 2) * (p->HostVMEnable == true ? p->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - s->DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4645
ExpectedVRatioPrefetch = s->PrefetchPixelLinesTime[k] / (PrefetchTime * s->PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4646
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = s->NoOfDPPState[k] * s->PixelDCFCLKCyclesRequiredInPrefetch[k] / s->PrefetchPixelLinesTime[k] * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4648
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = s->DCFCLKRequiredForPeakBandwidthPerSurface[k] + s->NoOfDPPState[k] * s->DPTEBandwidth / s->NormalEfficiency / s->NormalEfficiency / p->ReturnBusWidth;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4651
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = p->DCFCLKPerState;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4653
if (p->DynamicMetadataEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4662
p->RequiredDPPCLKPerSurface[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4665
p->PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4666
p->HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4667
p->VTotal[k] - p->VActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4668
p->DynamicMetadataTransmittedBytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4669
p->DynamicMetadataLinesBeforeActiveRequired[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4670
p->Interlace[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4682
AllowedTimeForUrgentExtraLatency = p->MaximumVStartup[j][k] * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe - TdmsksPipe - s->DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4684
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = dml_max(s->DCFCLKRequiredForPeakBandwidthPerSurface[k], s->ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4686
s->DCFCLKRequiredForPeakBandwidthPerSurface[k] = p->DCFCLKPerState;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4691
for (dml_uint_t k = 0; k <= p->NumberOfActiveSurfaces - 1; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4692
s->DCFCLKRequiredForPeakBandwidth = s->DCFCLKRequiredForPeakBandwidth + s->DCFCLKRequiredForPeakBandwidthPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4695
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4697
MaximumTvmPlus2Tr0PlusTsw = (p->MaximumVStartup[j][k] - 2) * p->HTotal[k] / p->PixelClock[k] - s->MinimumTWait - s->DynamicMetadataVMExtraLatency[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4698
if (MaximumTvmPlus2Tr0PlusTsw <= s->MinimumTvmPlus2Tr0 + s->PrefetchPixelLinesTime[k] / 4) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4702
2 * s->ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - s->MinimumTvmPlus2Tr0 - s->PrefetchPixelLinesTime[k] / 4),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4703
(2 * s->ExtraLatencyCycles + s->PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - s->MinimumTvmPlus2Tr0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4761
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4762
if (ViewportStationary[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4763
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_min(dml_ceil(SurfaceWidthY[k], ReadBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) - dml_floor(ViewportXStartY[k], ReadBlockWidthY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4764
dml_min(dml_ceil(SurfaceHeightY[k], ReadBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) - dml_floor(ViewportYStartY[k], ReadBlockHeightY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4765
BytesPerPixelY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4767
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4768
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4769
dml_min(dml_ceil(SurfaceWidthC[k], ReadBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) - dml_floor(ViewportXStartC[k], ReadBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4770
dml_min(dml_ceil(SurfaceHeightC[k], ReadBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) - dml_floor(ViewportYStartC[k], ReadBlockHeightC[k])) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4772
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4773
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4774
dml_min(dml_ceil(SurfaceWidthY[k], 8 * Read256BytesBlockWidthY[k]), dml_floor(ViewportXStartY[k] + ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1, 8 * Read256BytesBlockWidthY[k]) - dml_floor(ViewportXStartY[k], 8 * Read256BytesBlockWidthY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4775
dml_min(dml_ceil(SurfaceHeightY[k], 8 * Read256BytesBlockHeightY[k]), dml_floor(ViewportYStartY[k] + ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1, 8 * Read256BytesBlockHeightY[k]) - dml_floor(ViewportYStartY[k], 8 * Read256BytesBlockHeightY[k])) * BytesPerPixelY[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4776
if (Read256BytesBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4777
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4778
dml_min(dml_ceil(SurfaceWidthC[k], 8 * Read256BytesBlockWidthC[k]), dml_floor(ViewportXStartC[k] + ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1, 8 * Read256BytesBlockWidthC[k]) - dml_floor(ViewportXStartC[k], 8 * Read256BytesBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4779
dml_min(dml_ceil(SurfaceHeightC[k], 8 * Read256BytesBlockHeightC[k]), dml_floor(ViewportYStartC[k] + ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1, 8 * Read256BytesBlockHeightC[k]) - dml_floor(ViewportYStartC[k], 8 * Read256BytesBlockHeightC[k])) * BytesPerPixelC[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4783
SurfaceSizeInMALL[k] = (dml_uint_t)(dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) * dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4784
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4785
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4786
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4787
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4789
if (DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4790
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4791
dml_ceil(dml_min(SurfaceWidthY[k], ViewportWidthY[k] + 8 * Read256BytesBlockWidthY[k] - 1), 8 * Read256BytesBlockWidthY[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4792
dml_ceil(dml_min(SurfaceHeightY[k], ViewportHeightY[k] + 8 * Read256BytesBlockHeightY[k] - 1), 8 * Read256BytesBlockHeightY[k]) * BytesPerPixelY[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4794
if (Read256BytesBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4795
SurfaceSizeInMALL[k] = (dml_uint_t)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4796
dml_ceil(dml_min(SurfaceWidthC[k], ViewportWidthC[k] + 8 * Read256BytesBlockWidthC[k] - 1), 8 * Read256BytesBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4797
dml_ceil(dml_min(SurfaceHeightC[k], ViewportHeightC[k] + 8 * Read256BytesBlockHeightC[k] - 1), 8 * Read256BytesBlockHeightC[k]) * BytesPerPixelC[k] / 256);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4803
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4804
if (UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4805
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4864
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4865
DETBufferSizeInKByte[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4866
if (SourcePixelFormat[k] == dml_420_8 || SourcePixelFormat[k] == dml_420_10 || SourcePixelFormat[k] == dml_420_12) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4876
if (2.0 * ((dml_float_t) RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t) RoundedUpMaxSwathSizeBytesC[k]) / 1024.0 <= minDET)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4882
dml_print("DML::%s: k=%u minDET = %u\n", __func__, k, minDET);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4883
dml_print("DML::%s: k=%u max_minDET = %u\n", __func__, k, max_minDET);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4884
dml_print("DML::%s: k=%u minDET_pipe = %u\n", __func__, k, minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4885
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesY = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4886
dml_print("DML::%s: k=%u RoundedUpMaxSwathSizeBytesC = %u\n", __func__, k, RoundedUpMaxSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4890
minDET_pipe = (dml_uint_t)(dml_max(128, dml_ceil(((dml_float_t)RoundedUpMaxSwathSizeBytesY[k] + (dml_float_t)RoundedUpMaxSwathSizeBytesC[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4892
dml_print("DML::%s: k=%u minDET_pipe = %u (assume each plane take half DET)\n", __func__, k, minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4896
if (UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4897
DETBufferSizeInKByte[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4898
} else if (DETSizeOverride[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4899
DETBufferSizeInKByte[k] = DETSizeOverride[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4900
DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * DETSizeOverride[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4901
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe <= DETBufferSizePoolInKByte) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4902
DETBufferSizeInKByte[k] = minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4903
DETBufferSizePoolInKByte = DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4907
dml_print("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4908
dml_print("DML::%s: k=%u DETSizeOverride = %u\n", __func__, k, DETSizeOverride[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4909
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4915
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4916
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4917
TotalBandwidth = TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4921
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4922
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4928
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4930
if (UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4931
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4932
} else if (DETSizeOverride[k] > 0 || (((dml_float_t) (ForceSingleDPP ? 1 : DPPPerSurface[k]) * (dml_float_t) DETBufferSizeInKByte[k] / (dml_float_t) MaxTotalDETInKByte) >= ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / TotalBandwidth))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4933
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4934
BandwidthOfSurfacesNotAssignedDETPiece = BandwidthOfSurfacesNotAssignedDETPiece - ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4936
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4939
dml_print("DML::%s: k=%u DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, k, DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4940
dml_print("DML::%s: k=%u BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, BandwidthOfSurfacesNotAssignedDETPiece);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4948
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4950
dml_print("DML::%s: j=%u k=%u, ReadBandwidthLuma[k] = %f\n", __func__, j, k, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4951
dml_print("DML::%s: j=%u k=%u, ReadBandwidthChroma[k] = %f\n", __func__, j, k, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4952
dml_print("DML::%s: j=%u k=%u, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, ReadBandwidthLuma[NextSurfaceToAssignDETPiece]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4953
dml_print("DML::%s: j=%u k=%u, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, ReadBandwidthChroma[NextSurfaceToAssignDETPiece]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4954
dml_print("DML::%s: j=%u k=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, k, NextSurfaceToAssignDETPiece);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4956
if (!DETPieceAssignedToThisSurfaceAlready[k] && (!NextPotentialSurfaceToAssignDETPieceFound ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4957
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] < ReadBandwidthLuma[NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[NextSurfaceToAssignDETPiece])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4958
NextSurfaceToAssignDETPiece = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4962
dml_print("DML::%s: j=%u k=%u, DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
4963
dml_print("DML::%s: j=%u k=%u, NextPotentialSurfaceToAssignDETPieceFound = %u\n", __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5011
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5012
dml_print("DML::%s: k=%u DETBufferSizeInKByte = %u (TotalReadBandWidth=%f)\n", __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5059
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5061
p->vm_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5062
p->dpte_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5064
p->vm_group_bytes[k] = 2048;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5065
if (p->GPUVMMinPageSizeKBytes[k] >= 64 && dml_is_vertical_rotation(p->myPipe[k].SourceScan)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5066
p->dpte_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5068
p->dpte_group_bytes[k] = 2048;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5071
p->vm_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5072
p->dpte_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5075
if (p->myPipe[k].SourcePixelFormat == dml_420_8 || p->myPipe[k].SourcePixelFormat == dml_420_10 ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5076
p->myPipe[k].SourcePixelFormat == dml_420_12 || p->myPipe[k].SourcePixelFormat == dml_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5077
if ((p->myPipe[k].SourcePixelFormat == dml_420_10 || p->myPipe[k].SourcePixelFormat == dml_420_12) && !dml_is_vertical_rotation(p->myPipe[k].SourceScan)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5078
s->PTEBufferSizeInRequestsForLuma[k] = (p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma) / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5079
s->PTEBufferSizeInRequestsForChroma[k] = s->PTEBufferSizeInRequestsForLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5081
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5082
s->PTEBufferSizeInRequestsForChroma[k] = p->PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5086
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5087
p->myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5088
p->myPipe[k].DPPPerSurface,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5089
p->myPipe[k].BlockHeight256BytesC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5090
p->myPipe[k].BlockWidth256BytesC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5091
p->myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5092
p->myPipe[k].SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5093
p->myPipe[k].BytePerPixelC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5094
p->myPipe[k].SourceScan,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5095
p->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5096
p->myPipe[k].ViewportHeightChroma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5097
p->myPipe[k].ViewportXStartC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5098
p->myPipe[k].ViewportYStartC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5101
p->GPUVMMinPageSizeKBytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5102
s->PTEBufferSizeInRequestsForChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5103
p->myPipe[k].PitchC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5104
p->myPipe[k].DCCMetaPitchC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5105
p->myPipe[k].BlockWidthC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5106
p->myPipe[k].BlockHeightC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5109
&s->MetaRowByteC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5110
&s->PixelPTEBytesPerRowC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5111
&s->PixelPTEBytesPerRowStorageC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5112
&p->dpte_row_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5113
&p->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5114
&p->dpte_row_height_linear_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5115
&s->PixelPTEBytesPerRowC_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5116
&s->dpte_row_width_chroma_ub_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5117
&s->dpte_row_height_chroma_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5118
&p->meta_req_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5119
&p->meta_req_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5120
&p->meta_row_width_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5121
&p->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5122
&p->PixelPTEReqWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5123
&p->PixelPTEReqHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5124
&p->PTERequestSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5125
&p->dpde0_bytes_per_frame_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5126
&p->meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5128
p->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines (
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5129
p->myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5130
p->myPipe[k].VTapsChroma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5131
p->myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5132
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5133
p->myPipe[k].SwathHeightC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5134
p->myPipe[k].SourceScan,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5135
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5136
p->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5137
p->myPipe[k].ViewportHeightChroma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5138
p->myPipe[k].ViewportXStartC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5139
p->myPipe[k].ViewportYStartC,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5142
&p->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5143
&p->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5145
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5146
s->PTEBufferSizeInRequestsForChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5147
s->PixelPTEBytesPerRowC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5148
s->PixelPTEBytesPerRowStorageC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5150
s->MetaRowByteC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5151
p->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5152
p->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5153
s->dpte_row_height_chroma_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5154
s->dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5155
s->PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5159
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5160
p->myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5161
p->myPipe[k].DPPPerSurface,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5162
p->myPipe[k].BlockHeight256BytesY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5163
p->myPipe[k].BlockWidth256BytesY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5164
p->myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5165
p->myPipe[k].SurfaceTiling,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5166
p->myPipe[k].BytePerPixelY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5167
p->myPipe[k].SourceScan,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5168
p->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5169
p->myPipe[k].ViewportHeight,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5170
p->myPipe[k].ViewportXStart,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5171
p->myPipe[k].ViewportYStart,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5174
p->GPUVMMinPageSizeKBytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5175
s->PTEBufferSizeInRequestsForLuma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5176
p->myPipe[k].PitchY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5177
p->myPipe[k].DCCMetaPitchY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5178
p->myPipe[k].BlockWidthY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5179
p->myPipe[k].BlockHeightY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5182
&s->MetaRowByteY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5183
&s->PixelPTEBytesPerRowY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5184
&s->PixelPTEBytesPerRowStorageY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5185
&p->dpte_row_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5186
&p->dpte_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5187
&p->dpte_row_height_linear_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5188
&s->PixelPTEBytesPerRowY_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5189
&s->dpte_row_width_luma_ub_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5190
&s->dpte_row_height_luma_one_row_per_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5191
&p->meta_req_width[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5192
&p->meta_req_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5193
&p->meta_row_width[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5194
&p->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5195
&p->PixelPTEReqWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5196
&p->PixelPTEReqHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5197
&p->PTERequestSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5198
&p->dpde0_bytes_per_frame_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5199
&p->meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5201
p->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5202
p->myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5203
p->myPipe[k].VTaps,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5204
p->myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5205
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5206
p->myPipe[k].SwathHeightY,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5207
p->myPipe[k].SourceScan,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5208
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5209
p->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5210
p->myPipe[k].ViewportHeight,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5211
p->myPipe[k].ViewportXStart,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5212
p->myPipe[k].ViewportYStart,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5215
&p->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5216
&p->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5218
p->PDEAndMetaPTEBytesFrame[k] = (s->PDEAndMetaPTEBytesFrameY + s->PDEAndMetaPTEBytesFrameC) * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5219
p->MetaRowByte[k] = s->MetaRowByteY[k] + s->MetaRowByteC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5221
if (s->PixelPTEBytesPerRowStorageY[k] <= 64 * s->PTEBufferSizeInRequestsForLuma[k] && s->PixelPTEBytesPerRowStorageC[k] <= 64 * s->PTEBufferSizeInRequestsForChroma[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5222
p->PTEBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5224
p->PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5226
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY = %u\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5227
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC = %u\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5228
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowStorageY = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5229
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowStorageC = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5230
dml_print("DML::%s: k=%u, PTEBufferSizeInRequestsForLuma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5231
dml_print("DML::%s: k=%u, PTEBufferSizeInRequestsForChroma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5232
dml_print("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5235
s->one_row_per_frame_fits_in_buffer[k] = (s->PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForLuma[k] &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5236
s->PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5239
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrame = %u\n", __func__, k, p->PDEAndMetaPTEBytesFrame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5240
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrameY = %u\n", __func__, k, s->PDEAndMetaPTEBytesFrameY);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5241
dml_print("DML::%s: k=%u, PDEAndMetaPTEBytesFrameC = %u\n", __func__, k, s->PDEAndMetaPTEBytesFrameC);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5242
dml_print("DML::%s: k=%u, HostVMDynamicLevels = %u\n", __func__, k, s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5243
dml_print("DML::%s: k=%u, one_row_per_frame_fits_in_buffer = %u\n", __func__, k, s->one_row_per_frame_fits_in_buffer[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5244
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowY_one_row_per_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5245
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowC_one_row_per_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5258
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5259
if (p->PTEBufferModeOverrideEn[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5260
p->PTE_BUFFER_MODE[k] = p->PTEBufferModeOverrideVal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5262
p->PTE_BUFFER_MODE[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->UsesMALLForStaticScreen[k] || (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5263
(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) || (p->GPUVMMinPageSizeKBytes[k] > 64);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5264
p->BIGK_FRAGMENT_SIZE[k] = (dml_uint_t)(dml_log2(p->GPUVMMinPageSizeKBytes[k] * 1024) - 12);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5267
for (dml_uint_t k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5269
dml_print("DML::%s: k=%u, SurfaceSizeInMALL = %u\n", __func__, k, p->SurfaceSizeInMALL[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5270
dml_print("DML::%s: k=%u, UsesMALLForStaticScreen = %u\n", __func__, k, p->UsesMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5272
p->use_one_row_for_frame[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->UsesMALLForStaticScreen[k] || (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5273
(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) || (p->GPUVMMinPageSizeKBytes[k] > 64 && dml_is_vertical_rotation(p->myPipe[k].SourceScan));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5275
p->use_one_row_for_frame_flip[k] = p->use_one_row_for_frame[k] && !(p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5277
if (p->use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5278
p->dpte_row_height_luma[k] = s->dpte_row_height_luma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5279
p->dpte_row_width_luma_ub[k] = s->dpte_row_width_luma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5280
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5281
p->dpte_row_height_chroma[k] = s->dpte_row_height_chroma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5282
p->dpte_row_width_chroma_ub[k] = s->dpte_row_width_chroma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5283
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5284
p->PTEBufferSizeNotExceeded[k] = s->one_row_per_frame_fits_in_buffer[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5287
if (p->MetaRowByte[k] <= p->DCCMetaBufferSizeBytes) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5288
p->DCCMetaBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5290
p->DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5293
dml_print("DML::%s: k=%u, MetaRowByte = %u\n", __func__, k, p->MetaRowByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5294
dml_print("DML::%s: k=%u, DCCMetaBufferSizeBytes = %u\n", __func__, k, p->DCCMetaBufferSizeBytes);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5295
dml_print("DML::%s: k=%u, DCCMetaBufferSizeNotExceeded = %u\n", __func__, k, p->DCCMetaBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5298
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY[k] * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5299
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC[k] * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5300
p->PixelPTEBytesPerRow[k] = s->PixelPTEBytesPerRowY[k] + s->PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5301
if (p->use_one_row_for_frame[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5302
p->PixelPTEBytesPerRow[k] = p->PixelPTEBytesPerRow[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5306
p->myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5307
p->myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5308
p->myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5309
p->myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5310
p->myPipe[k].HTotal / p->myPipe[k].PixelClock,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5311
s->MetaRowByteY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5312
s->MetaRowByteC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5313
p->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5314
p->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5315
s->PixelPTEBytesPerRowY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5316
s->PixelPTEBytesPerRowC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5317
p->dpte_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5318
p->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5321
&p->meta_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5322
&p->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5324
dml_print("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5325
dml_print("DML::%s: k=%u, use_one_row_for_frame_flip = %u\n", __func__, k, p->use_one_row_for_frame_flip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5326
dml_print("DML::%s: k=%u, UseMALLForPStateChange = %u\n", __func__, k, p->UseMALLForPStateChange[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5327
dml_print("DML::%s: k=%u, dpte_row_height_luma = %u\n", __func__, k, p->dpte_row_height_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5328
dml_print("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5329
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowY = %u\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5330
dml_print("DML::%s: k=%u, dpte_row_height_chroma = %u\n", __func__, k, p->dpte_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5331
dml_print("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5332
dml_print("DML::%s: k=%u, PixelPTEBytesPerRowC = %u\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5333
dml_print("DML::%s: k=%u, PixelPTEBytesPerRow = %u\n", __func__, k, p->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5334
dml_print("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5335
dml_print("DML::%s: k=%u, PTE_BUFFER_MODE = %u\n", __func__, k, p->PTE_BUFFER_MODE[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5336
dml_print("DML::%s: k=%u, BIGK_FRAGMENT_SIZE = %u\n", __func__, k, p->BIGK_FRAGMENT_SIZE[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5702
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5703
Dppclk[k] = DPPCLKUsingSingleDPP[k] / DPPPerSurface[k] * (1 + DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5704
*GlobalDPPCLK = dml_max(*GlobalDPPCLK, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5709
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5710
Dppclk[k] = *GlobalDPPCLK / 255.0 * dml_ceil(Dppclk[k] * 255.0 / *GlobalDPPCLK, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5711
dml_print("DML::%s: Dppclk[%0d] = %f\n", __func__, k, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5731
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5732
UsesMALLForStaticScreen[k] = (UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5733
if (UsesMALLForStaticScreen[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5734
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5736
dml_print("DML::%s: k=%u, UsesMALLForStaticScreen = %u\n", __func__, k, UsesMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5737
dml_print("DML::%s: k=%u, TotalSurfaceSizeInMALL = %u\n", __func__, k, TotalSurfaceSizeInMALL);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5745
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5746
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCNFinal * 1024 * 1024 &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5747
!UsesMALLForStaticScreen[k] && UseMALLForStaticScreen[k] != dml_use_mall_static_screen_disable && one_row_per_frame_fits_in_buffer[k] &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5748
(!CanAddAnotherSurfaceToMALL || SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5750
SurfaceToAddToMALL = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5751
dml_print("DML::%s: k=%u, UseMALLForStaticScreen = %u (dis, en, optimize)\n", __func__, k, UseMALLForStaticScreen[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5936
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5937
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5942
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5943
VActiveBandwith = VActiveBandwith + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * meta_row_bandwidth[k] + NumberOfDPP[k] * dpte_row_bandwidth[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5986
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5987
if (NotUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5993
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5994
*PrefetchBandwidth = *PrefetchBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5995
ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k] + NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
5996
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6000
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6001
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6003
+ dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6004
ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6005
+ cursor_bw[k] * UrgentBurstFactorCursor[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6006
+ NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6007
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6008
+ PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6009
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6042
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6043
ret_val = ret_val - dml_max(ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6044
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) +
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6045
cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6047
dml_print("DML::%s: k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6048
dml_print("DML::%s: NumberOfDPP = %u\n", __func__, NumberOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6049
dml_print("DML::%s: ReadBandwidthLuma = %f\n", __func__, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6050
dml_print("DML::%s: UrgentBurstFactorLuma = %f\n", __func__, UrgentBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6051
dml_print("DML::%s: ReadBandwidthChroma = %f\n", __func__, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6052
dml_print("DML::%s: UrgentBurstFactorChroma = %f\n", __func__, UrgentBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6053
dml_print("DML::%s: cursor_bw = %f\n", __func__, cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6054
dml_print("DML::%s: UrgentBurstFactorCursor = %f\n", __func__, UrgentBurstFactorCursor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6056
dml_print("DML::%s: PrefetchBandwidthLuma = %f\n", __func__, PrefetchBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6057
dml_print("DML::%s: UrgentBurstFactorLumaPre = %f\n", __func__, UrgentBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6058
dml_print("DML::%s: PrefetchBandwidthChroma = %f\n", __func__, PrefetchBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6059
dml_print("DML::%s: UrgentBurstFactorChromaPre = %f\n", __func__, UrgentBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6060
dml_print("DML::%s: cursor_bw_pre = %f\n", __func__, cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6061
dml_print("DML::%s: UrgentBurstFactorCursorPre = %f\n", __func__, UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6099
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6100
if (ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6104
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6105
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6106
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6108
*TotalBandwidth = *TotalBandwidth + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6109
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k]) + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6110
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k]) + cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6113
dml_print("DML::%s: k = %u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6114
dml_print("DML::%s: ImmediateFlipRequirement = %u\n", __func__, ImmediateFlipRequirement[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6116
dml_print("DML::%s: NumberOfDPP = %u\n", __func__, NumberOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6117
dml_print("DML::%s: prefetch_vmrow_bw = %f\n", __func__, prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6118
dml_print("DML::%s: final_flip_bw = %f\n", __func__, final_flip_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6119
dml_print("DML::%s: ReadBandwidthLuma = %f\n", __func__, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6120
dml_print("DML::%s: UrgentBurstFactorLuma = %f\n", __func__, UrgentBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6121
dml_print("DML::%s: ReadBandwidthChroma = %f\n", __func__, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6122
dml_print("DML::%s: UrgentBurstFactorChroma = %f\n", __func__, UrgentBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6123
dml_print("DML::%s: cursor_bw = %f\n", __func__, cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6124
dml_print("DML::%s: UrgentBurstFactorCursor = %f\n", __func__, UrgentBurstFactorCursor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6125
dml_print("DML::%s: PrefetchBandwidthLuma = %f\n", __func__, PrefetchBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6126
dml_print("DML::%s: UrgentBurstFactorLumaPre = %f\n", __func__, UrgentBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6127
dml_print("DML::%s: PrefetchBandwidthChroma = %f\n", __func__, PrefetchBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6128
dml_print("DML::%s: UrgentBurstFactorChromaPre = %f\n", __func__, UrgentBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6129
dml_print("DML::%s: cursor_bw_pre = %f\n", __func__, cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6130
dml_print("DML::%s: UrgentBurstFactorCursorPre = %f\n", __func__, UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6131
dml_print("DML::%s: meta_row_bandwidth = %f\n", __func__, meta_row_bandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6132
dml_print("DML::%s: dpte_row_bandwidth = %f\n", __func__, dpte_row_bandwidth[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6137
for (dml_uint_t k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6138
if (UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6139
if (ImmediateFlipRequirement[k] != dml_immediate_flip_not_required)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6140
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6141
NumberOfDPP[k] * final_flip_bw[k] + ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6142
NumberOfDPP[k] * (final_flip_bw[k] + PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6143
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6145
*TotalBandwidthNotIncludingMALLPrefetch = *TotalBandwidthNotIncludingMALLPrefetch + dml_max3(NumberOfDPP[k] * prefetch_vmrow_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6146
NumberOfDPP[k] * (meta_row_bandwidth[k] + dpte_row_bandwidth[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6147
+ ReadBandwidthLuma[k] * UrgentBurstFactorLuma[k] + ReadBandwidthChroma[k] * UrgentBurstFactorChroma[k] + cursor_bw[k] * UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6148
NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * UrgentBurstFactorLumaPre[k] + PrefetchBandwidthChroma[k] * UrgentBurstFactorChromaPre[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6149
+ cursor_bw_pre[k] * UrgentBurstFactorCursorPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6221
dml_uint_t k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6223
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->ms.DSCDelayPerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6230
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(mode_lib->ms.SwathWidthYThisState[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6231
CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6238
CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6240
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6241
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6245
CalculatePrefetchSchedule_params->PDEAndMetaPTEBytesFrame = mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6246
CalculatePrefetchSchedule_params->MetaRowByte = mode_lib->ms.MetaRowBytes[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6247
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->ms.DPTEBytesPerRow[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6248
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->ms.PrefetchLinesY[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6249
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->ms.PrefillY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6250
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->ms.MaxNumSwY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6251
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->ms.PrefetchLinesC[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6252
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->ms.PrefillC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6253
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->ms.MaxNumSwC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6254
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->ms.swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6255
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->ms.swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6256
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->ms.SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6257
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->ms.SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6259
CalculatePrefetchSchedule_params->DestinationLinesForPrefetch = &mode_lib->ms.LineTimesForPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6260
CalculatePrefetchSchedule_params->DestinationLinesToRequestVMInVBlank = &mode_lib->ms.LinesForMetaPTE[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6261
CalculatePrefetchSchedule_params->DestinationLinesToRequestRowInVBlank = &mode_lib->ms.LinesForMetaAndDPTERow[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6262
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->ms.VRatioPreY[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6263
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->ms.VRatioPreC[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6264
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWLuma = &mode_lib->ms.RequiredPrefetchPixelDataBWLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6265
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWChroma = &mode_lib->ms.RequiredPrefetchPixelDataBWChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6266
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->ms.support.NoTimeForDynamicMetadata[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6267
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->ms.Tno_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6276
dml_uint_t j, k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6281
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6282
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6283
mode_lib->ms.swath_width_luma_ub_this_state[k] = mode_lib->ms.swath_width_luma_ub_all_states[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6284
mode_lib->ms.swath_width_chroma_ub_this_state[k] = mode_lib->ms.swath_width_chroma_ub_all_states[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6285
mode_lib->ms.SwathWidthYThisState[k] = mode_lib->ms.SwathWidthYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6286
mode_lib->ms.SwathWidthCThisState[k] = mode_lib->ms.SwathWidthCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6287
mode_lib->ms.SwathHeightYThisState[k] = mode_lib->ms.SwathHeightYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6288
mode_lib->ms.SwathHeightCThisState[k] = mode_lib->ms.SwathHeightCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6291
mode_lib->ms.DETBufferSizeInKByteThisState[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6292
mode_lib->ms.DETBufferSizeYThisState[k] = mode_lib->ms.DETBufferSizeYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6293
mode_lib->ms.DETBufferSizeCThisState[k] = mode_lib->ms.DETBufferSizeCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6343
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6344
CalculatePrefetchMode(mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k], &s->MinPrefetchMode[k], &s->MaxPrefetchMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6345
s->NextPrefetchMode[k] = s->MinPrefetchMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6352
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6353
mode_lib->ms.PrefetchMode[k] = s->NextPrefetchMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6355
mode_lib->ms.PrefetchMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6356
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6358
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6365
myPipe->Dppclk = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6367
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6369
myPipe->DPPPerSurface = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6370
myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6371
myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6372
myPipe->BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6373
myPipe->BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6374
myPipe->BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6375
myPipe->BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6376
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6377
myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6378
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6379
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6380
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6381
myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6382
myPipe->ODMMode = mode_lib->ms.ODMModePerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6383
myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6384
myPipe->BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6385
myPipe->BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6389
dml_print("DML::%s: Calling CalculatePrefetchSchedule for j=%u, k=%u\n", __func__, j, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6390
dml_print("DML::%s: MaximumVStartup = %u\n", __func__, s->MaximumVStartup[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6392
dml_print("DML::%s: NextPrefetchMode = %u\n", __func__, s->NextPrefetchMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6393
dml_print("DML::%s: AllowForPStateChangeOrStutterInVBlank = %u\n", __func__, mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6394
dml_print("DML::%s: PrefetchMode = %u\n", __func__, mode_lib->ms.PrefetchMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6399
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->MaxVStartup, s->MaximumVStartup[j][k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6400
CalculatePrefetchSchedule_params->MaxVStartup = s->MaximumVStartup[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6401
CalculatePrefetchSchedule_params->DSTXAfterScaler = &s->DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6402
CalculatePrefetchSchedule_params->DSTYAfterScaler = &s->DSTYAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6403
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->ms.prefetch_vmrow_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6411
set_calculate_prefetch_schedule_params(mode_lib, CalculatePrefetchSchedule_params, j, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6413
mode_lib->ms.support.NoTimeForPrefetch[j][k] =
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6418
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6420
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6421
mode_lib->ms.swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6422
mode_lib->ms.swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6423
mode_lib->ms.SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6424
mode_lib->ms.SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6425
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6428
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6429
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6430
mode_lib->ms.VRatioPreY[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6431
mode_lib->ms.VRatioPreC[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6432
mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6433
mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6434
mode_lib->ms.DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6435
mode_lib->ms.DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6437
&mode_lib->ms.UrgentBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6438
&mode_lib->ms.UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6439
&mode_lib->ms.UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6440
&mode_lib->ms.NotUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6442
mode_lib->ms.cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] *
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6443
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6444
mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.VRatioPreY[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6477
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6478
if (mode_lib->ms.LineTimesForPrefetch[k] < 2.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6479
|| mode_lib->ms.LinesForMetaPTE[k] >= 32.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6480
|| mode_lib->ms.LinesForMetaAndDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6481
|| mode_lib->ms.support.NoTimeForPrefetch[j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6487
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6488
if (mode_lib->ms.support.NoTimeForDynamicMetadata[j][k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6494
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6495
if (mode_lib->ms.support.NoTimeForPrefetch[j][k] == true ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6496
mode_lib->ms.VRatioPreY[j][k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6497
mode_lib->ms.VRatioPreC[j][k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6498
((s->MaxVStartup < s->MaximumVStartup[j][k] || mode_lib->ms.policy.EnhancedPrefetchScheduleAccelerationFinal == 0) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6499
(mode_lib->ms.VRatioPreY[j][k] > __DML_MAX_VRATIO_PRE__ || mode_lib->ms.VRatioPreC[j][k] > __DML_MAX_VRATIO_PRE__))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6505
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6506
if (mode_lib->ms.LinesForMetaAndDPTERow[k] >= 16 || mode_lib->ms.LinesForMetaPTE[k] >= 32) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6530
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6531
if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6532
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib->ms.MetaRowBytes[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6533
if (mode_lib->ms.use_one_row_for_frame_flip[j][k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6534
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (2 * mode_lib->ms.DPTEBytesPerRow[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6536
mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * mode_lib->ms.DPTEBytesPerRow[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6541
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6551
mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6552
mode_lib->ms.MetaRowBytes[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6553
mode_lib->ms.DPTEBytesPerRow[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6556
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6557
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6558
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6559
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6560
mode_lib->ms.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6561
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6562
mode_lib->ms.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6563
mode_lib->ms.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6564
mode_lib->ms.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6565
mode_lib->ms.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6566
mode_lib->ms.use_one_row_for_frame_flip[j][k], // 24
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6569
&mode_lib->ms.DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6570
&mode_lib->ms.DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6571
&mode_lib->ms.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6572
&mode_lib->ms.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6605
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6606
if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required) && (mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6616
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6617
s->NextPrefetchMode[k] = s->NextPrefetchMode[k] + 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6619
if (s->NextPrefetchMode[k] <= s->MaxPrefetchMode[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6632
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6633
mode_lib->ms.use_one_row_for_frame_this_state[k] = mode_lib->ms.use_one_row_for_frame[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6722
dml_uint_t j, k, m;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6747
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6748
if (mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k] == false
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6749
&& ((mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6750
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6751
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6752
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6753
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6754
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6755
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6756
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6757
|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6758
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6759
|| mode_lib->ms.cache_display_cfg.plane.VTaps[k] != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6761
} else if (mode_lib->ms.cache_display_cfg.plane.VTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.VTaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6762
|| mode_lib->ms.cache_display_cfg.plane.HTaps[k] < 1.0 || mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 8.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6763
|| (mode_lib->ms.cache_display_cfg.plane.HTaps[k] > 1.0 && (mode_lib->ms.cache_display_cfg.plane.HTaps[k] % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6764
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.ip.max_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6765
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.ip.max_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6766
|| mode_lib->ms.cache_display_cfg.plane.HRatio[k] > mode_lib->ms.cache_display_cfg.plane.HTaps[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6767
|| mode_lib->ms.cache_display_cfg.plane.VRatio[k] > mode_lib->ms.cache_display_cfg.plane.VTaps[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6768
|| (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6769
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6770
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6771
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6772
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6773
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6774
&& (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k] > 8 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] < 1 || mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 8 ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6775
(mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] > 1 && mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] % 2 == 1) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6776
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.ip.max_hscl_ratio ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6777
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.ip.max_vscl_ratio ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6778
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k] ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6779
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k] > mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6786
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6787
if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear && (!(!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) || mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6792
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6794
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6795
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6798
&mode_lib->ms.BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6799
&mode_lib->ms.BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6800
&mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6801
&mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6802
&mode_lib->ms.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6803
&mode_lib->ms.Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6804
&mode_lib->ms.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6805
&mode_lib->ms.Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6806
&mode_lib->ms.MacroTileHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6807
&mode_lib->ms.MacroTileHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6808
&mode_lib->ms.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6809
&mode_lib->ms.MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6813
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6814
if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6815
mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6816
mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6818
mode_lib->ms.SwathWidthYSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6819
mode_lib->ms.SwathWidthCSingleDPP[k] = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6822
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6823
mode_lib->ms.ReadBandwidthLuma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * dml_ceil(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6824
mode_lib->ms.ReadBandwidthChroma[k] = mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * dml_ceil(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k] / 2.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6826
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6827
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6828
&& mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6829
mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6830
* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6831
/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6832
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6833
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6834
} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6835
mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6836
* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6837
/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6838
* mode_lib->ms.cache_display_cfg.timing.HTotal[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6839
/ mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6841
mode_lib->ms.WriteBandwidth[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6847
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6848
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6849
(mode_lib->ms.WriteBandwidth[k] > mode_lib->ms.ip.writeback_interface_buffer_size_kbytes * 1024 / mode_lib->ms.state.writeback_latency_us)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6856
for (k = 0; k <= (dml_uint_t) mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6857
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6869
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6870
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6871
if (mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > mode_lib->ms.ip.writeback_max_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6872
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > mode_lib->ms.ip.writeback_max_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6873
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] < mode_lib->ms.ip.writeback_min_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6874
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] < mode_lib->ms.ip.writeback_min_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6875
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_hscl_taps
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6876
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_vscl_taps
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6877
|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6878
|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6879
|| (mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > 2.0 && ((mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] % 2) == 1))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6882
if (2.0 * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * (mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] - 1) * 57 > mode_lib->ms.ip.writeback_line_buffer_buffer_size) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6888
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6890
mode_lib->ms.cache_display_cfg.plane.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6891
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6892
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6893
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6896
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6897
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6898
mode_lib->ms.cache_display_cfg.plane.HTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6899
mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6900
mode_lib->ms.cache_display_cfg.plane.VTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6901
mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6903
&mode_lib->ms.PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6904
&mode_lib->ms.PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6905
&mode_lib->ms.MinDPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6908
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6909
if (mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6911
} else if (!dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6913
} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelC[k] > 0 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6915
} else if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6917
} else if (dml_is_vertical_rotation(mode_lib->ms.cache_display_cfg.plane.SourceScan[k]) && mode_lib->ms.BytePerPixelY[k] == 8 && mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6923
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10 || mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6928
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = mode_lib->ms.ip.line_buffer_size_bits * dml_max(mode_lib->ms.cache_display_cfg.plane.HRatio[k], 1.0) / mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6929
(mode_lib->ms.cache_display_cfg.plane.VTaps[k] + dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatio[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6930
if (mode_lib->ms.BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6935
* dml_max(mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k], 1.0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6936
/ mode_lib->ms.cache_display_cfg.plane.LBBitPerPixel[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6937
/ (mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k]
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6938
+ dml_max(dml_ceil(mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k], 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6940
mode_lib->ms.MaximumSwathWidthLuma[k] = dml_min(s->MaximumSwathWidthSupportLuma, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6941
mode_lib->ms.MaximumSwathWidthChroma[k] = dml_min(s->MaximumSwathWidthSupportChroma, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6945
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6946
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6947
mode_lib->ms.cache_display_cfg.output.DSCEnable[k] != dml_dsc_disable) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6948
mode_lib->ms.support.NumberOfDSCSlices[k] = mode_lib->ms.cache_display_cfg.output.DSCSlices[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6950
if (mode_lib->ms.support.NumberOfDSCSlices[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6951
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 4800) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6952
mode_lib->ms.support.NumberOfDSCSlices[k] = (dml_uint_t)(dml_ceil(mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 600, 4));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6953
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 2400) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6954
mode_lib->ms.support.NumberOfDSCSlices[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6955
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 1200) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6956
mode_lib->ms.support.NumberOfDSCSlices[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6957
} else if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] > 340) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6958
mode_lib->ms.support.NumberOfDSCSlices[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6960
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
6964
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7035
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7036
if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_as_needed_for_pstate_and_voltage)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7038
if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_as_possible)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7047
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7050
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7051
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7052
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7053
mode_lib->ms.policy.ODMUse[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7059
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7063
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7073
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7074
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7075
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7076
mode_lib->ms.policy.ODMUse[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7082
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7086
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7099
(mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7100
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7101
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7102
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7103
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7104
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7105
mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7106
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7107
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7108
mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7109
mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7112
mode_lib->ms.cache_display_cfg.output.DSCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7113
mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7114
mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7117
&mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7118
&mode_lib->ms.RequiresFEC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7119
&mode_lib->ms.OutputBppPerState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7120
&mode_lib->ms.OutputTypePerState[k], // VBA_DELTA, VBA uses a string to represent type and rate, but DML uses enum, don't want to rely on strng
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7121
&mode_lib->ms.OutputRatePerState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7122
&mode_lib->ms.RequiredSlots[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7124
if (mode_lib->ms.RequiresDSC[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7125
mode_lib->ms.ODMModePerState[k] = s->ODMModeNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7126
mode_lib->ms.RequiredDISPCLKPerSurface[j][k] = s->RequiredDISPCLKPerSurfaceNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7131
mode_lib->ms.ODMModePerState[k] = s->ODMModeDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7132
mode_lib->ms.RequiredDISPCLKPerSurface[j][k] = s->RequiredDISPCLKPerSurfaceDSC;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7139
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7140
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7141
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7142
mode_lib->ms.NoOfDPP[j][k] = 4;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7143
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7144
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7145
mode_lib->ms.NoOfDPP[j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7146
} else if (mode_lib->ms.policy.MPCCombineUse[k] == dml_mpc_disabled) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7147
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7148
mode_lib->ms.NoOfDPP[j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7149
} else if (RoundToDFSGranularity(mode_lib->ms.MinDPPCLKUsingSingleDPP[k] * (1 + mode_lib->ms.soc.dcn_downspread_percent / 100),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7151
mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7152
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7153
mode_lib->ms.NoOfDPP[j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7155
mode_lib->ms.MPCCombine[j][k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7156
mode_lib->ms.NoOfDPP[j][k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7159
mode_lib->ms.MPCCombine[j][k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7160
mode_lib->ms.NoOfDPP[j][k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7167
for (k = 0; k < (dml_uint_t) mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7168
if (mode_lib->ms.NoOfDPP[j][k] == 1)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7170
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_8
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7171
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_10
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7172
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_420_12
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7173
|| mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] == dml_rgbe_alpha
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7174
|| mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k] == dml_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7185
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7186
if (mode_lib->ms.policy.MPCCombineUse[k] != dml_mpc_disabled && mode_lib->ms.policy.MPCCombineUse[k] != dml_mpc_as_needed_for_voltage &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7187
mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k] > s->BWOfNonCombinedSurfaceOfMaximumBandwidth &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7188
(mode_lib->ms.ODMModePerState[k] != dml_odm_mode_combine_2to1 && mode_lib->ms.ODMModePerState[k] != dml_odm_mode_combine_4to1) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7189
mode_lib->ms.MPCCombine[j][k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7190
s->BWOfNonCombinedSurfaceOfMaximumBandwidth = mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7191
s->NumberOfNonCombinedSurfaceOfMaximumBandwidth = k;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7203
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7204
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7206
CalculateWriteBackDISPCLK(mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7207
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7208
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7209
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7210
mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7211
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7212
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7213
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7214
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7221
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7222
mode_lib->ms.RequiredDISPCLK[j] = dml_max(mode_lib->ms.RequiredDISPCLK[j], mode_lib->ms.RequiredDISPCLKPerSurface[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7225
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7226
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7238
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7239
mode_lib->ms.RequiredDPPCLKPerSurface[j][k] = mode_lib->ms.RequiredDPPCLKThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7255
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7256
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7258
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7260
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7262
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k || mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7275
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7276
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7277
!(mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 12.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7278
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 10.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7279
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] == 8.0
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7280
|| mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k] > (dml_uint_t) mode_lib->ms.ip.maximum_dsc_bits_per_component
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7287
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7288
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7289
s->TotalSlots = mode_lib->ms.RequiredSlots[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7291
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[j] == k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7294
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp && s->TotalSlots > 63)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7296
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 && s->TotalSlots > 64)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7301
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7302
if (mode_lib->ms.cache_display_cfg.output.OutputDisabled[k] == false &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7303
mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7304
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) && mode_lib->ms.OutputBppPerState[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7319
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7320
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7321
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7322
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420 && mode_lib->ms.cache_display_cfg.timing.Interlace[k] == 1 && mode_lib->ms.ip.ptoi_supported == true)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7325
if (mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] != 0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7327
if ((mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable || mode_lib->ms.cache_display_cfg.output.DSCEnable[k] == dml_dsc_enable_if_necessary) && mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 && !mode_lib->ms.ip.dsc422_native_support)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7330
if (((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr2 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_hbr3) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7331
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_edp) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7332
((mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr10 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr13p5 || mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_uhbr20) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7333
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp2p0))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7336
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7337
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.OutputLinkDPRate[k] == dml_dp_rate_na)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7339
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7342
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j && mode_lib->ms.cache_display_cfg.output.ForcedOutputLinkBPP[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7347
if ((mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7348
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7351
if (mode_lib->ms.cache_display_cfg.output.OutputMultistreamEn[k] == 1 && mode_lib->ms.cache_display_cfg.output.OutputMultistreamId[k] == j)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7355
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] != dml_dp && (mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_split_1to2 ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7356
mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to2 || mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to4))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7359
if ((mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to2 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 2) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7360
(mode_lib->ms.policy.ODMUse[k] == dml_odm_use_policy_mso_1to4 && mode_lib->ms.cache_display_cfg.output.OutputLinkDPLanes[k] < 4))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7366
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7367
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7368
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7370
mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7371
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7372
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7373
mode_lib->ms.OutputBppPerState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7374
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7375
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7376
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7377
mode_lib->ms.cache_display_cfg.output.AudioSampleRate[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7378
mode_lib->ms.cache_display_cfg.output.AudioSampleLayout[k]) > mode_lib->ms.state.dtbclk_mhz) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7385
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7386
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1 && mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7389
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k && mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1 && (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7390
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmi)) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7396
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7397
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7398
if (mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7399
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_dp2p0 ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7400
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7401
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7402
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7404
} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7406
} else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7412
dml_print("DML::%s: k=%u, RequiresDSC = %u\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7414
if (mode_lib->ms.RequiresDSC[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7415
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7416
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7418
dml_print("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7419
dml_print("DML::%s: k=%u, DSCCLKPerState = %f\n", __func__, k, mode_lib->ms.state.dscclk_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7420
dml_print("DML::%s: k=%u, DSCFormatFactor = %u\n", __func__, k, s->DSCFormatFactor);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7424
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7425
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7429
if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7446
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7447
if (mode_lib->ms.RequiresDSC[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7448
if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_4to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7449
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 4 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7452
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 16)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7454
} else if (mode_lib->ms.ODMModePerState[k] == dml_odm_mode_combine_2to1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7455
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > 2 * (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7458
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 8)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7461
if (mode_lib->ms.cache_display_cfg.timing.HActive[k] > (dml_uint_t) mode_lib->ms.ip.maximum_pixels_per_line_per_dsc_unit)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7464
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7474
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7475
mode_lib->ms.DSCDelayPerState[k] = DSCDelayRequirement(mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7476
mode_lib->ms.ODMModePerState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7477
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7478
mode_lib->ms.OutputBppPerState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7479
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7480
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7481
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7482
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7483
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7484
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7485
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7488
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7491
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m && mode_lib->ms.RequiresDSC[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7492
mode_lib->ms.DSCDelayPerState[k] = mode_lib->ms.DSCDelayPerState[m];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7501
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7502
mode_lib->ms.RequiredDPPCLKThisState[k] = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7503
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7504
mode_lib->ms.ODMModeThisState[k] = mode_lib->ms.ODMModePerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7572
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7573
mode_lib->ms.swath_width_luma_ub_all_states[j][k] = mode_lib->ms.swath_width_luma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7574
mode_lib->ms.swath_width_chroma_ub_all_states[j][k] = mode_lib->ms.swath_width_chroma_ub_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7575
mode_lib->ms.SwathWidthYAllStates[j][k] = mode_lib->ms.SwathWidthYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7576
mode_lib->ms.SwathWidthCAllStates[j][k] = mode_lib->ms.SwathWidthCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7577
mode_lib->ms.SwathHeightYAllStates[j][k] = mode_lib->ms.SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7578
mode_lib->ms.SwathHeightCAllStates[j][k] = mode_lib->ms.SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7581
mode_lib->ms.DETBufferSizeInKByteAllStates[j][k] = mode_lib->ms.DETBufferSizeInKByteThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7582
mode_lib->ms.DETBufferSizeYAllStates[j][k] = mode_lib->ms.DETBufferSizeYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7583
mode_lib->ms.DETBufferSizeCAllStates[j][k] = mode_lib->ms.DETBufferSizeCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7587
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7588
mode_lib->ms.cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7625
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7626
mode_lib->ms.swath_width_luma_ub_this_state[k] = mode_lib->ms.swath_width_luma_ub_all_states[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7627
mode_lib->ms.swath_width_chroma_ub_this_state[k] = mode_lib->ms.swath_width_chroma_ub_all_states[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7628
mode_lib->ms.SwathWidthYThisState[k] = mode_lib->ms.SwathWidthYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7629
mode_lib->ms.SwathWidthCThisState[k] = mode_lib->ms.SwathWidthCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7630
mode_lib->ms.SwathHeightYThisState[k] = mode_lib->ms.SwathHeightYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7631
mode_lib->ms.SwathHeightCThisState[k] = mode_lib->ms.SwathHeightCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7632
mode_lib->ms.DETBufferSizeInKByteThisState[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7633
mode_lib->ms.DETBufferSizeYThisState[k] = mode_lib->ms.DETBufferSizeYAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7634
mode_lib->ms.DETBufferSizeCThisState[k] = mode_lib->ms.DETBufferSizeCAllStates[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7635
mode_lib->ms.RequiredDPPCLKThisState[k] = mode_lib->ms.RequiredDPPCLKPerSurface[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7636
mode_lib->ms.NoOfDPPThisState[k] = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7640
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7641
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7642
mode_lib->ms.TotalNumberOfDCCActiveDPP[j] = mode_lib->ms.TotalNumberOfDCCActiveDPP[j] + mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7646
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7647
s->SurfParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7648
s->SurfParameters[k].DPPPerSurface = mode_lib->ms.NoOfDPP[j][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7649
s->SurfParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7650
s->SurfParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7651
s->SurfParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7652
s->SurfParameters[k].BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7653
s->SurfParameters[k].BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7654
s->SurfParameters[k].BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7655
s->SurfParameters[k].BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7656
s->SurfParameters[k].BlockWidthY = mode_lib->ms.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7657
s->SurfParameters[k].BlockHeightY = mode_lib->ms.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7658
s->SurfParameters[k].BlockWidthC = mode_lib->ms.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7659
s->SurfParameters[k].BlockHeightC = mode_lib->ms.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7660
s->SurfParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7661
s->SurfParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7662
s->SurfParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7663
s->SurfParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7664
s->SurfParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7665
s->SurfParameters[k].BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7666
s->SurfParameters[k].BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7667
s->SurfParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ms.ip.ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7668
s->SurfParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7669
s->SurfParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7670
s->SurfParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7671
s->SurfParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7672
s->SurfParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7673
s->SurfParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7674
s->SurfParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7675
s->SurfParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7676
s->SurfParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7677
s->SurfParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7678
s->SurfParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7679
s->SurfParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7680
s->SurfParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7681
s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7682
s->SurfParameters[k].SwathHeightY = mode_lib->ms.SwathHeightYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7683
s->SurfParameters[k].SwathHeightC = mode_lib->ms.SwathHeightCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7753
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7754
mode_lib->ms.PrefetchLinesY[j][k] = mode_lib->ms.PrefetchLinesYThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7755
mode_lib->ms.PrefetchLinesC[j][k] = mode_lib->ms.PrefetchLinesCThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7756
mode_lib->ms.meta_row_bandwidth[j][k] = mode_lib->ms.meta_row_bandwidth_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7757
mode_lib->ms.dpte_row_bandwidth[j][k] = mode_lib->ms.dpte_row_bandwidth_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7758
mode_lib->ms.DPTEBytesPerRow[j][k] = mode_lib->ms.DPTEBytesPerRowThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7759
mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] = mode_lib->ms.PDEAndMetaPTEBytesPerFrameThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7760
mode_lib->ms.MetaRowBytes[j][k] = mode_lib->ms.MetaRowBytesThisState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7761
mode_lib->ms.use_one_row_for_frame[j][k] = mode_lib->ms.use_one_row_for_frame_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7762
mode_lib->ms.use_one_row_for_frame_flip[j][k] = mode_lib->ms.use_one_row_for_frame_flip_this_state[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7767
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7768
if (mode_lib->ms.PTEBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7771
dml_print("DML::%s: j=%u k=%u, PTEBufferSizeNotExceededPerState[%u] = %u\n", __func__, j, k, k, mode_lib->ms.PTEBufferSizeNotExceededPerState[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7779
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7780
if (mode_lib->ms.DCCMetaBufferSizeNotExceededPerState[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7795
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7797
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7798
mode_lib->ms.swath_width_luma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7799
mode_lib->ms.swath_width_chroma_ub_this_state[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7800
mode_lib->ms.SwathHeightYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7801
mode_lib->ms.SwathHeightCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7802
(dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7805
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7806
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7807
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7808
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7809
mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7810
mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7811
mode_lib->ms.DETBufferSizeYThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7812
mode_lib->ms.DETBufferSizeCThisState[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7814
&mode_lib->ms.UrgentBurstFactorCursor[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7815
&mode_lib->ms.UrgentBurstFactorLuma[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7816
&mode_lib->ms.UrgentBurstFactorChroma[j][k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7817
&mode_lib->ms.NotUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7845
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7846
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7847
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7848
mode_lib->ms.WritebackDelayTime[k] = mode_lib->ms.state.writeback_latency_us + CalculateWriteBackDelay(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7849
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7850
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7851
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7852
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7853
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7854
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7855
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7856
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / mode_lib->ms.RequiredDISPCLK[j];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7858
mode_lib->ms.WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7861
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7862
mode_lib->ms.WritebackDelayTime[k] = dml_max(mode_lib->ms.WritebackDelayTime[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7876
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7878
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == m) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7879
mode_lib->ms.WritebackDelayTime[k] = mode_lib->ms.WritebackDelayTime[m];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7885
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7886
s->MaximumVStartup[j][k] = CalculateMaxVStartup(k,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7890
mode_lib->ms.WritebackDelayTime[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7892
s->MaxVStartupAllPlanes[j] = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes[j], s->MaximumVStartup[j][k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7894
dml_print("DML::%s: k=%u, MaxVStartupAllPlanes[%u] = %u\n", __func__, k, j, s->MaxVStartupAllPlanes[j]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7895
dml_print("DML::%s: k=%u, MaximumVStartup[%u][%u] = %u\n", __func__, k, j, k, s->MaximumVStartup[j][k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7910
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7911
s->ImmediateFlipRequiredFinal = s->ImmediateFlipRequiredFinal || (mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7915
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7917
((mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_required) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7918
(mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7923
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7925
mode_lib->ms.support.ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe || ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == true || mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7926
(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame || mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7930
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7932
((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_enable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)) ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7933
((mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_disable || mode_lib->ms.cache_display_cfg.plane.UseMALLForStaticScreen[k] == dml_use_mall_static_screen_optimize) && (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7940
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7941
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_full_frame)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7943
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_sub_viewport) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7945
if (mode_lib->ms.cache_display_cfg.timing.RefreshRate[k] > 120)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
7948
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8037
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8038
s->MaxTotalVActiveRDBandwidth = s->MaxTotalVActiveRDBandwidth + mode_lib->ms.ReadBandwidthLuma[k] + mode_lib->ms.ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8063
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8064
if (mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] > 0.0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8065
if (mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] == 64 && mode_lib->ms.ip.cursor_64bpp_support == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8073
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8074
mode_lib->ms.support.AlignedYPitch[k] = dml_ceil(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8075
dml_max(mode_lib->ms.cache_display_cfg.surface.PitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8076
mode_lib->ms.MacroTileWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8077
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8078
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k]), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8080
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8082
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8083
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8084
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8085
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_16
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8086
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8087
&& mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_mono_8) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8088
mode_lib->ms.support.AlignedCPitch[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.PitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), mode_lib->ms.MacroTileWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8089
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8090
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k], mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k]), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8092
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8095
mode_lib->ms.support.AlignedCPitch[k] = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8096
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8098
if (mode_lib->ms.support.AlignedYPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchY[k] || mode_lib->ms.support.AlignedCPitch[k] > mode_lib->ms.cache_display_cfg.surface.PitchC[k] ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8099
mode_lib->ms.support.AlignedDCCMetaPitchY[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k] || mode_lib->ms.support.AlignedDCCMetaPitchC[k] > mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8105
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8106
if (mode_lib->ms.cache_display_cfg.plane.ViewportWidth[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8108
if (mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_64 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_32 &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8109
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_16 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_444_8 && mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k] != dml_rgbe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8110
if (mode_lib->ms.cache_display_cfg.plane.ViewportWidthChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k] || mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k] > mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8227
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8228
mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8229
mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8230
mode_lib->ms.SwathHeightY[k] = mode_lib->ms.SwathHeightYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8231
mode_lib->ms.SwathHeightC[k] = mode_lib->ms.SwathHeightCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8232
mode_lib->ms.DETBufferSizeInKByte[k] = mode_lib->ms.DETBufferSizeInKByteAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8233
mode_lib->ms.DETBufferSizeY[k] = mode_lib->ms.DETBufferSizeYAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8234
mode_lib->ms.DETBufferSizeC[k] = mode_lib->ms.DETBufferSizeCAllStates[mode_lib->ms.support.MaximumMPCCombine][k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8244
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8245
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8246
mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMModePerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8248
mode_lib->ms.support.ODMMode[k] = dml_odm_mode_bypass;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8251
mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8252
mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8253
mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBppPerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8254
mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputTypePerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8255
mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRatePerState[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8256
mode_lib->ms.support.SubViewportLinesNeededInMALL[k] = mode_lib->ms.SubViewportLinesNeededInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8302
dml_uint_t j = 0, k = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8340
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8341
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8346
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8347
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8348
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8349
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8350
mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8351
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8352
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8353
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8354
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8362
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8363
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8365
mode_lib->ms.cache_display_cfg.hw.ODMMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8366
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8383
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8385
mode_lib->ms.cache_display_cfg.plane.HRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8386
mode_lib->ms.cache_display_cfg.plane.HRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8387
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8388
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8391
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8392
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8393
mode_lib->ms.cache_display_cfg.plane.HTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8394
mode_lib->ms.cache_display_cfg.plane.HTapsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8395
mode_lib->ms.cache_display_cfg.plane.VTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8396
mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8399
&locals->PSCL_THROUGHPUT[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8400
&locals->PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8401
&locals->DPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8413
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8414
if (clk_cfg->dppclk_option[k] == dml_use_required_freq)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8415
locals->Dppclk[k] = locals->Dppclk_calculated[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8416
else if (clk_cfg->dppclk_option[k] == dml_use_override_freq)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8417
locals->Dppclk[k] = clk_cfg->dppclk_mhz[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8419
locals->Dppclk[k] = mode_lib->ms.state.dppclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8421
dml_print("DML::%s: Using Dppclk[%0d] = %f\n", __func__, k, locals->Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8425
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8427
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8428
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8431
&locals->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8432
&locals->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8433
&locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8434
&locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8435
&locals->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8436
&locals->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8437
&locals->BlockWidth256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8438
&locals->BlockWidth256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8439
&locals->BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8440
&locals->BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8441
&locals->BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8442
&locals->BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8485
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8486
locals->ReadBandwidthSurfaceLuma[k] = locals->SwathWidthSingleDPPY[k] * locals->BytePerPixelY[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8487
locals->ReadBandwidthSurfaceChroma[k] = locals->SwathWidthSingleDPPC[k] * locals->BytePerPixelC[k] / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8488
dml_print("DML::%s: ReadBandwidthSurfaceLuma[%i] = %fBps\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8489
dml_print("DML::%s: ReadBandwidthSurfaceChroma[%i] = %fBps\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8583
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8584
if ((mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] != k) || !mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8585
locals->DSCCLK_calculated[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8587
if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_420)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8589
else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_444)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8591
else if (mode_lib->ms.cache_display_cfg.output.OutputFormat[k] == dml_n422 || mode_lib->ms.cache_display_cfg.output.OutputEncoder[k] == dml_hdmifrl)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8595
if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_4to1)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8596
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8597
else if (mode_lib->ms.cache_display_cfg.hw.ODMMode[k] == dml_odm_mode_combine_2to1)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8598
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8600
locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8605
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8606
locals->DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.cache_display_cfg.hw.DSCEnabled[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8607
mode_lib->ms.cache_display_cfg.hw.ODMMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8608
mode_lib->ms.cache_display_cfg.output.DSCInputBitPerComponent[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8609
mode_lib->ms.cache_display_cfg.output.OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8610
mode_lib->ms.cache_display_cfg.timing.HActive[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8611
mode_lib->ms.cache_display_cfg.timing.HTotal[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8612
mode_lib->ms.cache_display_cfg.hw.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8613
mode_lib->ms.cache_display_cfg.output.OutputFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8614
mode_lib->ms.cache_display_cfg.output.OutputEncoder[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8615
mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8616
mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8619
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8621
if (j != k && mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j && mode_lib->ms.cache_display_cfg.hw.DSCEnabled[j])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8622
locals->DSCDelay[k] = locals->DSCDelay[j];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8658
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8659
s->SurfaceParameters[k].PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8660
s->SurfaceParameters[k].DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8661
s->SurfaceParameters[k].SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8662
s->SurfaceParameters[k].ViewportHeight = mode_lib->ms.cache_display_cfg.plane.ViewportHeight[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8663
s->SurfaceParameters[k].ViewportHeightChroma = mode_lib->ms.cache_display_cfg.plane.ViewportHeightChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8664
s->SurfaceParameters[k].BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8665
s->SurfaceParameters[k].BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8666
s->SurfaceParameters[k].BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8667
s->SurfaceParameters[k].BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8668
s->SurfaceParameters[k].BlockWidthY = locals->BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8669
s->SurfaceParameters[k].BlockHeightY = locals->BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8670
s->SurfaceParameters[k].BlockWidthC = locals->BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8671
s->SurfaceParameters[k].BlockHeightC = locals->BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8672
s->SurfaceParameters[k].InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8673
s->SurfaceParameters[k].HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8674
s->SurfaceParameters[k].DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8675
s->SurfaceParameters[k].SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8676
s->SurfaceParameters[k].SurfaceTiling = mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8677
s->SurfaceParameters[k].BytePerPixelY = locals->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8678
s->SurfaceParameters[k].BytePerPixelC = locals->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8679
s->SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ms.ip.ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8680
s->SurfaceParameters[k].VRatio = mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8681
s->SurfaceParameters[k].VRatioChroma = mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8682
s->SurfaceParameters[k].VTaps = mode_lib->ms.cache_display_cfg.plane.VTaps[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8683
s->SurfaceParameters[k].VTapsChroma = mode_lib->ms.cache_display_cfg.plane.VTapsChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8684
s->SurfaceParameters[k].PitchY = mode_lib->ms.cache_display_cfg.surface.PitchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8685
s->SurfaceParameters[k].DCCMetaPitchY = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8686
s->SurfaceParameters[k].PitchC = mode_lib->ms.cache_display_cfg.surface.PitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8687
s->SurfaceParameters[k].DCCMetaPitchC = mode_lib->ms.cache_display_cfg.surface.DCCMetaPitchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8688
s->SurfaceParameters[k].ViewportStationary = mode_lib->ms.cache_display_cfg.plane.ViewportStationary[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8689
s->SurfaceParameters[k].ViewportXStart = mode_lib->ms.cache_display_cfg.plane.ViewportXStart[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8690
s->SurfaceParameters[k].ViewportYStart = mode_lib->ms.cache_display_cfg.plane.ViewportYStart[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8691
s->SurfaceParameters[k].ViewportXStartC = mode_lib->ms.cache_display_cfg.plane.ViewportXStartC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8692
s->SurfaceParameters[k].ViewportYStartC = mode_lib->ms.cache_display_cfg.plane.ViewportYStartC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8693
s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->ms.cache_display_cfg.plane.ForceOneRowForFrame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8694
s->SurfaceParameters[k].SwathHeightY = locals->SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8695
s->SurfaceParameters[k].SwathHeightC = locals->SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8799
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8800
s->TotalActiveDPP = s->TotalActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8801
if (mode_lib->ms.cache_display_cfg.surface.DCCEnable[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8802
s->TotalDCCActiveDPP = s->TotalDCCActiveDPP + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8825
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8826
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8827
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8828
locals->WritebackDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8831
mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8832
mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8833
mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8834
mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8835
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8836
mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8837
mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8838
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8840
locals->WritebackDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8842
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[j] == k
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8844
locals->WritebackDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8846
locals->WritebackDelay[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8856
mode_lib->ms.cache_display_cfg.timing.HTotal[k]) / locals->Dispclk);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8862
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8864
if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[k] == j)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8865
locals->WritebackDelay[k] = locals->WritebackDelay[j];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8875
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8876
CalculateUrgentBurstFactor(mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8877
locals->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8878
locals->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8879
locals->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8880
locals->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8881
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8884
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8885
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8886
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8887
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8888
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8889
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8890
locals->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8891
locals->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8894
&locals->UrgBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8895
&locals->UrgBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8896
&locals->UrgBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8897
&locals->NoUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8899
locals->cursor_bw[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8900
((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * mode_lib->ms.cache_display_cfg.plane.VRatio[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8906
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8907
s->MaxVStartupLines[k] = CalculateMaxVStartup(k,
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8911
locals->WritebackDelay[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8914
dml_print("DML::%s: k=%u MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8915
dml_print("DML::%s: k=%u WritebackDelay = %f\n", __func__, k, locals->WritebackDelay[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8919
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8920
s->MaxVStartupAllPlanes = (dml_uint_t)(dml_max(s->MaxVStartupAllPlanes, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8923
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8924
s->ImmediateFlipRequirementFinal = s->ImmediateFlipRequirementFinal || (mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8936
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8937
CalculatePrefetchMode(mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k], &s->MinPrefetchMode[k], &s->MaxPrefetchMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8938
s->NextPrefetchMode[k] = s->MinPrefetchMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8950
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8951
locals->PrefetchMode[k] = s->NextPrefetchMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8953
locals->PrefetchMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8954
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8956
mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8963
myPipe->Dppclk = locals->Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8965
myPipe->PixelClock = mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8967
myPipe->DPPPerSurface = mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8968
myPipe->ScalerEnabled = mode_lib->ms.cache_display_cfg.plane.ScalerEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8969
myPipe->SourceScan = mode_lib->ms.cache_display_cfg.plane.SourceScan[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8970
myPipe->BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8971
myPipe->BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8972
myPipe->BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8973
myPipe->BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8974
myPipe->InterlaceEnable = mode_lib->ms.cache_display_cfg.timing.Interlace[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8975
myPipe->NumberOfCursors = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8976
myPipe->VBlank = mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8977
myPipe->HTotal = mode_lib->ms.cache_display_cfg.timing.HTotal[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8978
myPipe->HActive = mode_lib->ms.cache_display_cfg.timing.HActive[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8979
myPipe->DCCEnable = mode_lib->ms.cache_display_cfg.surface.DCCEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8980
myPipe->ODMMode = mode_lib->ms.cache_display_cfg.hw.ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8981
myPipe->SourcePixelFormat = mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8982
myPipe->BytePerPixelY = locals->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8983
myPipe->BytePerPixelC = locals->BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8987
dml_print("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8988
dml_print("DML::%s: AllowForPStateChangeOrStutterInVBlank = %u\n", __func__, mode_lib->ms.policy.AllowForPStateChangeOrStutterInVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8989
dml_print("DML::%s: PrefetchMode[k] = %u (Min=%u Max=%u)\n", __func__, locals->PrefetchMode[k], s->MinPrefetchMode[k], s->MaxPrefetchMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
8995
CalculatePrefetchSchedule_params->DSCDelay = locals->DSCDelay[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9001
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (dml_uint_t)(locals->SwathWidthY[k] / mode_lib->ms.cache_display_cfg.plane.HRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9002
CalculatePrefetchSchedule_params->OutputFormat = mode_lib->ms.cache_display_cfg.output.OutputFormat[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9004
CalculatePrefetchSchedule_params->VStartup = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9005
CalculatePrefetchSchedule_params->MaxVStartup = s->MaxVStartupLines[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9011
CalculatePrefetchSchedule_params->DynamicMetadataEnable = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9013
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataLinesBeforeActiveRequired[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9014
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = mode_lib->ms.cache_display_cfg.plane.DynamicMetadataTransmittedBytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9018
CalculatePrefetchSchedule_params->PDEAndMetaPTEBytesFrame = locals->PDEAndMetaPTEBytesFrame[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9019
CalculatePrefetchSchedule_params->MetaRowByte = locals->MetaRowByte[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9020
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = locals->PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9021
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = locals->PrefetchSourceLinesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9022
CalculatePrefetchSchedule_params->VInitPreFillY = locals->VInitPreFillY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9023
CalculatePrefetchSchedule_params->MaxNumSwathY = locals->MaxNumSwathY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9024
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = locals->PrefetchSourceLinesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9025
CalculatePrefetchSchedule_params->VInitPreFillC = locals->VInitPreFillC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9026
CalculatePrefetchSchedule_params->MaxNumSwathC = locals->MaxNumSwathC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9027
CalculatePrefetchSchedule_params->swath_width_luma_ub = locals->swath_width_luma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9028
CalculatePrefetchSchedule_params->swath_width_chroma_ub = locals->swath_width_chroma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9029
CalculatePrefetchSchedule_params->SwathHeightY = locals->SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9030
CalculatePrefetchSchedule_params->SwathHeightC = locals->SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9032
CalculatePrefetchSchedule_params->DSTXAfterScaler = &locals->DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9033
CalculatePrefetchSchedule_params->DSTYAfterScaler = &locals->DSTYAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9034
CalculatePrefetchSchedule_params->DestinationLinesForPrefetch = &locals->DestinationLinesForPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9035
CalculatePrefetchSchedule_params->DestinationLinesToRequestVMInVBlank = &locals->DestinationLinesToRequestVMInVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9036
CalculatePrefetchSchedule_params->DestinationLinesToRequestRowInVBlank = &locals->DestinationLinesToRequestRowInVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9037
CalculatePrefetchSchedule_params->VRatioPrefetchY = &locals->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9038
CalculatePrefetchSchedule_params->VRatioPrefetchC = &locals->VRatioPrefetchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9039
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWLuma = &locals->RequiredPrefetchPixDataBWLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9040
CalculatePrefetchSchedule_params->RequiredPrefetchPixDataBWChroma = &locals->RequiredPrefetchPixDataBWChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9041
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &locals->NotEnoughTimeForDynamicMetadata[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9042
CalculatePrefetchSchedule_params->Tno_bw = &locals->Tno_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9043
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &locals->prefetch_vmrow_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9044
CalculatePrefetchSchedule_params->Tdmdl_vm = &locals->Tdmdl_vm[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9045
CalculatePrefetchSchedule_params->Tdmdl = &locals->Tdmdl[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9046
CalculatePrefetchSchedule_params->TSetup = &locals->TSetup[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9047
CalculatePrefetchSchedule_params->VUpdateOffsetPix = &locals->VUpdateOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9048
CalculatePrefetchSchedule_params->VUpdateWidthPix = &locals->VUpdateWidthPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9049
CalculatePrefetchSchedule_params->VReadyOffsetPix = &locals->VReadyOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9051
locals->NoTimeToPrefetch[k] =
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9056
dml_print("DML::%s: k=%0u NoTimeToPrefetch=%0d\n", __func__, k, locals->NoTimeToPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9058
locals->VStartup[k] = (dml_uint_t)(dml_min(s->VStartupLines, s->MaxVStartupLines[k]));
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9059
locals->VStartupMin[k] = locals->VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9062
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9064
mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9065
locals->swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9066
locals->swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9067
locals->SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9068
locals->SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9069
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9072
mode_lib->ms.cache_display_cfg.plane.CursorWidth[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9073
mode_lib->ms.cache_display_cfg.plane.CursorBPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9074
locals->VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9075
locals->VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9076
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9077
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9078
locals->DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9079
locals->DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9081
&locals->UrgBurstFactorCursorPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9082
&locals->UrgBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9083
&locals->UrgBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9084
&locals->NoUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9086
locals->cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * mode_lib->ms.cache_display_cfg.plane.CursorBPP[k] / 8.0 / (mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * locals->VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9089
dml_print("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9090
dml_print("DML::%s: k=%0u UrgBurstFactorLuma=%f\n", __func__, k, locals->UrgBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9091
dml_print("DML::%s: k=%0u UrgBurstFactorChroma=%f\n", __func__, k, locals->UrgBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9092
dml_print("DML::%s: k=%0u UrgBurstFactorLumaPre=%f\n", __func__, k, locals->UrgBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9093
dml_print("DML::%s: k=%0u UrgBurstFactorChromaPre=%f\n", __func__, k, locals->UrgBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9095
dml_print("DML::%s: k=%0u VRatioPrefetchY=%f\n", __func__, k, locals->VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9096
dml_print("DML::%s: k=%0u VRatioY=%f\n", __func__, k, mode_lib->ms.cache_display_cfg.plane.VRatio[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9098
dml_print("DML::%s: k=%0u prefetch_vmrow_bw=%f\n", __func__, k, locals->prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9099
dml_print("DML::%s: k=%0u ReadBandwidthSurfaceLuma=%f\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9100
dml_print("DML::%s: k=%0u ReadBandwidthSurfaceChroma=%f\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9101
dml_print("DML::%s: k=%0u cursor_bw=%f\n", __func__, k, locals->cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9102
dml_print("DML::%s: k=%0u meta_row_bw=%f\n", __func__, k, locals->meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9103
dml_print("DML::%s: k=%0u dpte_row_bw=%f\n", __func__, k, locals->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9104
dml_print("DML::%s: k=%0u RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, locals->RequiredPrefetchPixDataBWLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9105
dml_print("DML::%s: k=%0u RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, locals->RequiredPrefetchPixDataBWChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9106
dml_print("DML::%s: k=%0u cursor_bw_pre=%f\n", __func__, k, locals->cursor_bw_pre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9107
dml_print("DML::%s: k=%0u MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, s->MaxTotalRDBandwidthNoUrgentBurst);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9109
if (locals->DestinationLinesForPrefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9112
if (locals->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9113
locals->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9114
((s->VStartupLines < s->MaxVStartupLines[k] || mode_lib->ms.policy.EnhancedPrefetchScheduleAccelerationFinal == 0) &&
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9115
(locals->VRatioPrefetchY[k] > __DML_MAX_VRATIO_PRE__ || locals->VRatioPrefetchC[k] > __DML_MAX_VRATIO_PRE__)))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9165
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9166
s->dummy_unit_vector[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9203
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9204
if (locals->NoTimeToPrefetch[k] == true || locals->NotEnoughTimeForDynamicMetadata[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9205
dml_print("DML::%s: k=%u, NoTimeToPrefetch = %0d\n", __func__, k, locals->NoTimeToPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9206
dml_print("DML::%s: k=%u, NotEnoughTimeForDynamicMetadata=%u\n", __func__, k, locals->NotEnoughTimeForDynamicMetadata[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9231
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9232
if (mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9233
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9234
if (locals->use_one_row_for_frame_flip[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9235
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * (2 * locals->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9237
locals->TotImmediateFlipBytes = locals->TotImmediateFlipBytes + mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k] * locals->PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9240
dml_print("DML::%s: k = %u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9241
dml_print("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib->ms.cache_display_cfg.hw.DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9242
dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %u\n", __func__, locals->PDEAndMetaPTEBytesFrame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9243
dml_print("DML::%s: MetaRowByte = %u\n", __func__, locals->MetaRowByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9244
dml_print("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, locals->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9249
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9259
locals->PDEAndMetaPTEBytesFrame[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9260
locals->MetaRowByte[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9261
locals->PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9264
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9265
mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9266
mode_lib->ms.cache_display_cfg.plane.VRatio[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9267
mode_lib->ms.cache_display_cfg.plane.VRatioChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9268
locals->Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9269
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9270
locals->dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9271
locals->meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9272
locals->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9273
locals->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9274
locals->use_one_row_for_frame_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9277
&locals->DestinationLinesToRequestVMInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9278
&locals->DestinationLinesToRequestRowInImmediateFlip[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9279
&locals->final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9280
&locals->ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9339
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9340
if (mode_lib->ms.policy.ImmediateFlipRequirement[k] != dml_immediate_flip_not_required && locals->ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9343
dml_print("DML::%s: Pipe %0d not supporting iflip\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9362
for (k = 0; k < mode_lib->ms.num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9363
dml_print("DML::%s: ImmediateFlipRequirement[%u] = %u\n", __func__, k, mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_required);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9376
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9377
s->NextPrefetchMode[k] = s->NextPrefetchMode[k] + 1;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9379
if (s->NextPrefetchMode[k] <= s->MaxPrefetchMode[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9483
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9484
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9485
locals->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9486
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackDRAMClockChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9487
locals->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0, locals->VStartupMin[k] * mode_lib->ms.cache_display_cfg.timing.HTotal[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9488
mode_lib->ms.cache_display_cfg.timing.PixelClock[k] - locals->Watermark.WritebackFCLKChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9490
locals->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9491
locals->WritebackAllowFCLKChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9613
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9614
if (locals->PrefetchMode[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9615
locals->MinTTUVBlank[k] = dml_max4(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9620
} else if (locals->PrefetchMode[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9621
locals->MinTTUVBlank[k] = dml_max3(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9625
} else if (locals->PrefetchMode[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9626
locals->MinTTUVBlank[k] = dml_max(
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9630
locals->MinTTUVBlank[k] = locals->Watermark.UrgentWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9632
if (!mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9633
locals->MinTTUVBlank[k] = locals->TCalc + locals->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9637
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9639
dml_print("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9642
mode_lib->ms.cache_display_cfg.surface.DCCEnable[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9644
mode_lib->ms.cache_display_cfg.surface.SourcePixelFormat[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9645
mode_lib->ms.cache_display_cfg.surface.SurfaceWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9646
mode_lib->ms.cache_display_cfg.surface.SurfaceWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9647
mode_lib->ms.cache_display_cfg.surface.SurfaceHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9648
mode_lib->ms.cache_display_cfg.surface.SurfaceHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9650
locals->BlockHeight256BytesY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9651
locals->BlockHeight256BytesC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9652
mode_lib->ms.cache_display_cfg.surface.SurfaceTiling[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9653
locals->BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9654
locals->BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9655
locals->BytePerPixelDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9656
locals->BytePerPixelDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9657
mode_lib->ms.cache_display_cfg.plane.SourceScan[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9659
&locals->DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9660
&locals->DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9661
&locals->DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9662
&locals->DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9663
&locals->DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9664
&locals->DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9668
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9669
s->Tvstartup_margin = (s->MaxVStartupLines[k] - locals->VStartupMin[k]) * mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9671
dml_print("DML::%s: k=%u, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, locals->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9674
locals->MinTTUVBlank[k] = locals->MinTTUVBlank[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9677
dml_print("DML::%s: k=%u, Tvstartup_margin = %f\n", __func__, k, s->Tvstartup_margin);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9678
dml_print("DML::%s: k=%u, MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9679
dml_print("DML::%s: k=%u, MinTTUVBlank = %f\n", __func__, k, locals->MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9682
locals->Tdmdl[k] = locals->Tdmdl[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9683
if (mode_lib->ms.cache_display_cfg.plane.DynamicMetadataEnable[k] && mode_lib->ms.ip.dynamic_metadata_vm_enabled) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9684
locals->Tdmdl_vm[k] = locals->Tdmdl_vm[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9687
isInterlaceTiming = (mode_lib->ms.cache_display_cfg.timing.Interlace[k] && !mode_lib->ms.ip.ptoi_supported);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9690
locals->VStartup[k] = (isInterlaceTiming ? (2 * s->MaxVStartupLines[k]) : s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9692
s->dlg_vblank_start = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9693
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9694
s->LSetup = dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9695
s->blank_lines_remaining = (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k]) - locals->VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9702
locals->MIN_DST_Y_NEXT_START[k] = s->dlg_vblank_start + s->blank_lines_remaining + s->LSetup;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9705
s->old_MIN_DST_Y_NEXT_START = ((isInterlaceTiming ? dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9706
mode_lib->ms.cache_display_cfg.timing.VTotal[k]) - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k])
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9707
+ dml_max(1.0, dml_ceil((dml_float_t) locals->WritebackDelay[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0))
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9708
+ dml_floor(4.0 * locals->TSetup[k] / ((dml_float_t) mode_lib->ms.cache_display_cfg.timing.HTotal[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9710
if (((locals->VUpdateOffsetPix[k] + locals->VUpdateWidthPix[k] + locals->VReadyOffsetPix[k]) / (double) mode_lib->ms.cache_display_cfg.timing.HTotal[k]) <=
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9712
dml_floor((mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9713
(int) (mode_lib->ms.cache_display_cfg.timing.VTotal[k] - mode_lib->ms.cache_display_cfg.timing.VActive[k] - mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k] - locals->VStartup[k]))) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9714
locals->VREADY_AT_OR_AFTER_VSYNC[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9716
locals->VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9719
dml_print("DML::%s: k=%u, VStartup = %u (max)\n", __func__, k, locals->VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9720
dml_print("DML::%s: k=%u, VStartupMin = %u (max)\n", __func__, k, locals->VStartupMin[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9721
dml_print("DML::%s: k=%u, VUpdateOffsetPix = %u\n", __func__, k, locals->VUpdateOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9722
dml_print("DML::%s: k=%u, VUpdateWidthPix = %u\n", __func__, k, locals->VUpdateWidthPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9723
dml_print("DML::%s: k=%u, VReadyOffsetPix = %u\n", __func__, k, locals->VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9724
dml_print("DML::%s: k=%u, HTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.HTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9725
dml_print("DML::%s: k=%u, VTotal = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VTotal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9726
dml_print("DML::%s: k=%u, VActive = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VActive[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9727
dml_print("DML::%s: k=%u, VFrontPorch = %u\n", __func__, k, mode_lib->ms.cache_display_cfg.timing.VFrontPorch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9728
dml_print("DML::%s: k=%u, TSetup = %f\n", __func__, k, locals->TSetup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9729
dml_print("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f\n", __func__, k, locals->MIN_DST_Y_NEXT_START[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9730
dml_print("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f (old)\n", __func__, k, s->old_MIN_DST_Y_NEXT_START);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9731
dml_print("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, locals->VREADY_AT_OR_AFTER_VSYNC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9738
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9739
if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true && mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_32) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9740
s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9741
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9742
} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9743
s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9744
(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9750
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9751
locals->TotalDataReadBandwidth = locals->TotalDataReadBandwidth + locals->ReadBandwidthSurfaceLuma[k] + locals->ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9754
dml_print("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, locals->TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9755
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, locals->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9756
dml_print("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, locals->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9761
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9762
if (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[k] != dml_use_mall_pstate_change_phantom_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c
9764
+ locals->ReadBandwidthSurfaceLuma[k] + locals->ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
732
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
733
if (display_cfg->plane.ViewportWidth[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
786
for (dml_uint_t k = 0; k < __DML_NUM_PLANES__; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/display_mode_util.c
787
pipe_plane[k] = __DML_PIPE_NO_PLANE__;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
381
int i, j, k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
440
for (k = 0; k < dc->res_pool->pipe_count; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
441
if (context->res_ctx.pipe_ctx[k].stream &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
442
context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
443
context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
444
static_base_state->stream_v1.base.pipe_mask |= (1 << k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
445
static_base_state->stream_v1.base.plane_pipe_masks[j] |= (1 << k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
477
for (k = 0; k < dc->res_pool->pipe_count; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
478
if (context->res_ctx.pipe_ctx[k].stream &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
479
context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
480
context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
484
static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c
485
static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10002
line_time = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10005
TimePerVMGroupVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_group_per_lower_vm_stage_pref;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10007
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10010
TimePerVMGroupFlip[k] = dst_y_per_vm_flip[k] * line_time / num_group_per_lower_vm_stage_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10012
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10015
TimePerVMRequestVBlank[k] = dst_y_per_vm_vblank[k] * line_time / num_req_per_lower_vm_stage_pref;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10017
TimePerVMRequestVBlank[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10019
TimePerVMRequestFlip[k] = dst_y_per_vm_flip[k] * line_time / num_req_per_lower_vm_stage_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10021
TimePerVMRequestFlip[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10023
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_vblank = %f\n", __func__, k, dst_y_per_vm_vblank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10024
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_vm_flip = %f\n", __func__, k, dst_y_per_vm_flip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10025
DML_LOG_VERBOSE("DML::%s: k=%u, line_time = %f\n", __func__, k, line_time);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10026
DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_pref = %d\n", __func__, k, num_group_per_lower_vm_stage_pref);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10027
DML_LOG_VERBOSE("DML::%s: k=%u, num_group_per_lower_vm_stage_flip = %d\n", __func__, k, num_group_per_lower_vm_stage_flip);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10028
DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_pref = %d\n", __func__, k, num_req_per_lower_vm_stage_pref);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10029
DML_LOG_VERBOSE("DML::%s: k=%u, num_req_per_lower_vm_stage_flip = %d\n", __func__, k, num_req_per_lower_vm_stage_flip);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10032
TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10033
TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10034
TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10035
TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10039
TimePerVMGroupVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10040
TimePerVMGroupFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10041
TimePerVMRequestVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10042
TimePerVMRequestFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10046
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupVBlank = %f\n", __func__, k, TimePerVMGroupVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10047
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMGroupFlip = %f\n", __func__, k, TimePerVMGroupFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10048
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestVBlank = %f\n", __func__, k, TimePerVMRequestVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10049
DML_LOG_VERBOSE("DML::%s: k=%u, TimePerVMRequestFlip = %f\n", __func__, k, TimePerVMRequestFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10068
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10069
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10070
if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10071
if ((dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockWidth256BytesY[k] > p->SwathHeightY[k]) || (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockHeight256BytesY[k] > p->SwathHeightY[k]) || p->DCCYMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10076
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] / math_min2(p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0, l->MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10078
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10079
DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateLuma = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10080
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionLuma = %f\n", __func__, k, l->MaximumEffectiveCompressionLuma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10082
l->TotalZeroSizeRequestReadBandwidth = l->TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10083
l->TotalZeroSizeCompressedReadBandwidth = l->TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane0 / l->MaximumEffectiveCompressionLuma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10085
if (p->ReadBandwidthSurfaceChroma[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10086
if ((dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockWidth256BytesC[k] > p->SwathHeightC[k]) || (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle) && p->BlockHeight256BytesC[k] > p->SwathHeightC[k]) || p->DCCCMaxUncompressedBlock[k] < 256) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10091
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] / math_min2(p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1, l->MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10093
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceChroma = %f\n", __func__, k, p->ReadBandwidthSurfaceChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10094
DML_LOG_VERBOSE("DML::%s: k=%u, NetDCCRateChroma = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].surface.dcc.informative.dcc_rate_plane1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10095
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumEffectiveCompressionChroma = %f\n", __func__, k, l->MaximumEffectiveCompressionChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10097
l->TotalZeroSizeRequestReadBandwidth = l->TotalZeroSizeRequestReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10098
l->TotalZeroSizeCompressedReadBandwidth = l->TotalZeroSizeCompressedReadBandwidth + p->ReadBandwidthSurfaceChroma[k] * p->display_cfg->plane_descriptors[k].surface.dcc.informative.fraction_of_zero_size_request_plane1 / l->MaximumEffectiveCompressionChroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10101
l->TotalCompressedReadBandwidth = l->TotalCompressedReadBandwidth + p->ReadBandwidthSurfaceLuma[k] + p->ReadBandwidthSurfaceChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10103
l->TotalRowReadBandwidth = l->TotalRowReadBandwidth + p->DPPPerSurface[k] * (p->meta_row_bw[k] + p->dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10165
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10166
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10167
l->LinesInDETY = ((double)p->DETBufferSizeY[k] + (p->UnboundedRequestEnabled == true ? l->EffectiveCompressedBufferSize : 0) * p->ReadBandwidthSurfaceLuma[k] / p->TotalDataReadBandwidth) / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10168
l->LinesInDETYRoundedDownToSwath = math_floor2(l->LinesInDETY, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10169
l->DETBufferingTimeY = l->LinesInDETYRoundedDownToSwath * ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10171
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u (%u kbytes)\n", __func__, k, p->DETBufferSizeY[k], p->DETBufferSizeY[k] / 1024);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10172
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10173
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10174
DML_LOG_VERBOSE("DML::%s: k=%u, ReadBandwidthSurfaceLuma = %f\n", __func__, k, p->ReadBandwidthSurfaceLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10175
DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, p->TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10176
DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETY = %f\n", __func__, k, l->LinesInDETY);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10177
DML_LOG_VERBOSE("DML::%s: k=%u, LinesInDETYRoundedDownToSwath = %f\n", __func__, k, l->LinesInDETYRoundedDownToSwath);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10178
DML_LOG_VERBOSE("DML::%s: k=%u, VRatio = %f\n", __func__, k, p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10179
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferingTimeY = %f\n", __func__, k, l->DETBufferingTimeY);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10183
bool isInterlaceTiming = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !p->ProgressiveToInterlaceUnitInOPP;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10187
l->FrameTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10188
l->VActiveTimeCriticalSurface = (isInterlaceTiming ? math_floor2((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active / 2.0, 1.0) : p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_active) * (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10189
l->BytePerPixelYCriticalSurface = p->BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10190
l->SwathWidthYCriticalSurface = p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10191
l->SwathHeightYCriticalSurface = p->SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10192
l->BlockWidth256BytesYCriticalSurface = p->BlockWidth256BytesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10193
l->DETBufferSizeYCriticalSurface = p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10194
l->MinTTUVBlankCriticalSurface = p->MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10195
l->SinglePlaneCriticalSurface = (p->ReadBandwidthSurfaceChroma[k] == 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10196
l->SinglePipeCriticalSurface = (p->DPPPerSurface[k] == 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10199
DML_LOG_VERBOSE("DML::%s: k=%u, FoundCriticalSurface = %u\n", __func__, k, FoundCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10200
DML_LOG_VERBOSE("DML::%s: k=%u, StutterPeriod = %f\n", __func__, k, *p->StutterPeriod);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10201
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlankCriticalSurface = %f\n", __func__, k, l->MinTTUVBlankCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10202
DML_LOG_VERBOSE("DML::%s: k=%u, FrameTimeCriticalSurface= %f\n", __func__, k, l->FrameTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10203
DML_LOG_VERBOSE("DML::%s: k=%u, VActiveTimeCriticalSurface = %f\n", __func__, k, l->VActiveTimeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10204
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelYCriticalSurface = %u\n", __func__, k, l->BytePerPixelYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10205
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthYCriticalSurface = %f\n", __func__, k, l->SwathWidthYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10206
DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightYCriticalSurface = %f\n", __func__, k, l->SwathHeightYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10207
DML_LOG_VERBOSE("DML::%s: k=%u, BlockWidth256BytesYCriticalSurface = %u\n", __func__, k, l->BlockWidth256BytesYCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10208
DML_LOG_VERBOSE("DML::%s: k=%u, SinglePlaneCriticalSurface = %u\n", __func__, k, l->SinglePlaneCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10209
DML_LOG_VERBOSE("DML::%s: k=%u, SinglePipeCriticalSurface = %u\n", __func__, k, l->SinglePipeCriticalSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10251
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10252
if (!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10253
if (!l->stream_visited[p->display_cfg->plane_descriptors[k].stream_index]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10255
if (p->display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10259
SinglePixelClock = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10260
SingleHTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10261
SingleVTotal = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10262
} else if (SinglePixelClock != ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10263
SingleHTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10264
SingleVTotal != p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.v_total) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10268
l->stream_visited[p->display_cfg->plane_descriptors[k].stream_index] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10364
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10393
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10394
unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10405
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_4to1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10408
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_3to1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10411
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_2to1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10415
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10417
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10419
mode_lib->mp.ODMMode[k] = dml2_odm_mode_bypass;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10424
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10425
mode_lib->mp.NoOfDPP[k] = cfg_support_info->plane_support_info[k].dpps_used;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10426
mode_lib->mp.Dppclk[k] = programming->plane_programming[k].min_clocks.dcn4x.dppclk_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10427
DML_ASSERT(mode_lib->mp.Dppclk[k] > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10430
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10431
unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10432
mode_lib->mp.DSCCLK[k] = programming->stream_programming[stream_index].min_clocks.dcn4x.dscclk_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10433
DML_LOG_VERBOSE("DML::%s: k=%d stream_index=%d, mode_lib->mp.DSCCLK = %f\n", __func__, k, stream_index, mode_lib->mp.DSCCLK[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10456
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10457
DML_LOG_VERBOSE("DML::%s: Dppclk[%0d] = %f\n", __func__, k, mode_lib->mp.Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10465
for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10466
DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10467
DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib->mp.NoOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10470
for (k = 0; k < s->num_active_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10471
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10491
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10493
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10494
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10495
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10496
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10499
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10500
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10501
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10502
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10503
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10504
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10507
&mode_lib->mp.PSCL_THROUGHPUT[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10508
&mode_lib->mp.PSCL_THROUGHPUT_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10509
&mode_lib->mp.DPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1051
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10512
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10514
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10515
display_cfg->plane_descriptors[k].surface.tiling,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10516
display_cfg->plane_descriptors[k].surface.plane0.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10517
display_cfg->plane_descriptors[k].surface.plane1.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1052
DETBufferSizeInKByte[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10520
&mode_lib->mp.BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10521
&mode_lib->mp.BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10522
&mode_lib->mp.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10523
&mode_lib->mp.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10524
&mode_lib->mp.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10525
&mode_lib->mp.Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10526
&mode_lib->mp.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10527
&mode_lib->mp.Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10528
&mode_lib->mp.MacroTileHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10529
&mode_lib->mp.MacroTileHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1053
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10530
&mode_lib->mp.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10531
&mode_lib->mp.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10532
&mode_lib->mp.surf_linear128_l[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10533
&mode_lib->mp.surf_linear128_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10563
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10564
mode_lib->mp.cursor_bw[k] = display_cfg->plane_descriptors[k].cursor.num_cursors * display_cfg->plane_descriptors[k].cursor.cursor_width * display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10565
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10566
mode_lib->mp.vactive_sw_bw_l[k] = mode_lib->mp.SwathWidthSingleDPPY[k] * mode_lib->mp.BytePerPixelY[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10567
mode_lib->mp.vactive_sw_bw_c[k] = mode_lib->mp.SwathWidthSingleDPPC[k] * mode_lib->mp.BytePerPixelC[k] / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10568
DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_l[%i] = %fBps\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10569
DML_LOG_VERBOSE("DML::%s: vactive_sw_bw_c[%i] = %fBps\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1063
if (2.0 * ((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0 <= l->minDET)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10630
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10631
mode_lib->mp.DSCDelay[k] = DSCDelayRequirement(cfg_support_info->stream_support_info[display_cfg->plane_descriptors[k].stream_index].dsc_enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10632
mode_lib->mp.ODMMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10634
s->OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10635
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10636
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10637
cfg_support_info->stream_support_info[display_cfg->plane_descriptors[k].stream_index].num_dsc_slices,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10638
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10639
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10640
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10641
s->PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10646
for (k = 0; k < s->num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10647
mode_lib->mp.SurfaceSizeInTheMALL[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10669
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10670
s->SurfaceParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10671
s->SurfaceParameters[k].DPPPerSurface = mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10672
s->SurfaceParameters[k].RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10673
s->SurfaceParameters[k].ViewportHeight = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10674
s->SurfaceParameters[k].ViewportHeightC = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10675
s->SurfaceParameters[k].BlockWidth256BytesY = mode_lib->mp.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10676
s->SurfaceParameters[k].BlockHeight256BytesY = mode_lib->mp.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10677
s->SurfaceParameters[k].BlockWidth256BytesC = mode_lib->mp.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10678
s->SurfaceParameters[k].BlockHeight256BytesC = mode_lib->mp.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10679
s->SurfaceParameters[k].BlockWidthY = mode_lib->mp.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1068
DML_LOG_VERBOSE("DML::%s: k=%u minDET = %u\n", __func__, k, l->minDET);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10680
s->SurfaceParameters[k].BlockHeightY = mode_lib->mp.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10681
s->SurfaceParameters[k].BlockWidthC = mode_lib->mp.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10682
s->SurfaceParameters[k].BlockHeightC = mode_lib->mp.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10683
s->SurfaceParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10684
s->SurfaceParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10685
s->SurfaceParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10686
s->SurfaceParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10687
s->SurfaceParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10688
s->SurfaceParameters[k].BytePerPixelY = mode_lib->mp.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10689
s->SurfaceParameters[k].BytePerPixelC = mode_lib->mp.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1069
DML_LOG_VERBOSE("DML::%s: k=%u max_minDET = %u\n", __func__, k, l->max_minDET);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10690
s->SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ip.ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10691
s->SurfaceParameters[k].VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10692
s->SurfaceParameters[k].VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10693
s->SurfaceParameters[k].VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10694
s->SurfaceParameters[k].VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10695
s->SurfaceParameters[k].PitchY = display_cfg->plane_descriptors[k].surface.plane0.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10696
s->SurfaceParameters[k].PitchC = display_cfg->plane_descriptors[k].surface.plane1.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10697
s->SurfaceParameters[k].ViewportStationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10698
s->SurfaceParameters[k].ViewportXStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10699
s->SurfaceParameters[k].ViewportYStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1070
DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u\n", __func__, k, l->minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10700
s->SurfaceParameters[k].ViewportXStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10701
s->SurfaceParameters[k].ViewportYStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10702
s->SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg->plane_descriptors[k].overrides.hw.force_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10703
s->SurfaceParameters[k].SwathHeightY = mode_lib->mp.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10704
s->SurfaceParameters[k].SwathHeightC = mode_lib->mp.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10705
s->SurfaceParameters[k].DCCMetaPitchY = display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10706
s->SurfaceParameters[k].DCCMetaPitchC = display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1071
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, full_swath_bytes_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1072
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, full_swath_bytes_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1075
l->minDET_pipe = (unsigned int)(math_max2(128, math_ceil2(((double)full_swath_bytes_l[k] + (double)full_swath_bytes_c[k]) / 1024.0, ConfigReturnBufferSegmentSizeInkByte)));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1076
DML_LOG_VERBOSE("DML::%s: k=%u minDET_pipe = %u (assume each plane take half DET)\n", __func__, k, l->minDET_pipe);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10780
for (k = 0; k < s->num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10781
mode_lib->mp.mall_prefetch_sdp_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10782
mode_lib->mp.mall_prefetch_dram_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10783
mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10784
mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10785
mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10786
mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10789
for (k = 0; k < s->num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1079
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10790
calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10796
calculate_mcache_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10798
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10799
calculate_mcache_setting_params->surf_vert = dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1080
DETBufferSizeInKByte[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10800
calculate_mcache_setting_params->vp_stationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10801
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10802
calculate_mcache_setting_params->imall_enable = mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10804
calculate_mcache_setting_params->vp_start_x_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10805
calculate_mcache_setting_params->vp_start_y_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10806
calculate_mcache_setting_params->full_vp_width_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10807
calculate_mcache_setting_params->full_vp_height_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10808
calculate_mcache_setting_params->blk_width_l = mode_lib->mp.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10809
calculate_mcache_setting_params->blk_height_l = mode_lib->mp.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1081
} else if (display_cfg->plane_descriptors[k].overrides.det_size_override_kb > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10810
calculate_mcache_setting_params->vmpg_width_l = s->vmpg_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10811
calculate_mcache_setting_params->vmpg_height_l = s->vmpg_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10812
calculate_mcache_setting_params->full_swath_bytes_l = s->full_swath_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10813
calculate_mcache_setting_params->bytes_per_pixel_l = mode_lib->mp.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10815
calculate_mcache_setting_params->vp_start_x_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10816
calculate_mcache_setting_params->vp_start_y_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10817
calculate_mcache_setting_params->full_vp_width_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10818
calculate_mcache_setting_params->full_vp_height_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10819
calculate_mcache_setting_params->blk_width_c = mode_lib->mp.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1082
DETBufferSizeInKByte[k] = display_cfg->plane_descriptors[k].overrides.det_size_override_kb;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10820
calculate_mcache_setting_params->blk_height_c = mode_lib->mp.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10821
calculate_mcache_setting_params->vmpg_width_c = s->vmpg_width_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10822
calculate_mcache_setting_params->vmpg_height_c = s->vmpg_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10823
calculate_mcache_setting_params->full_swath_bytes_c = s->full_swath_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10824
calculate_mcache_setting_params->bytes_per_pixel_c = mode_lib->mp.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10827
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_l = &mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p0[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10828
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_l = &mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p0[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10829
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_c = &mode_lib->mp.dcc_dram_bw_nom_overhead_factor_p1[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1083
l->DETBufferSizePoolInKByte = l->DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * display_cfg->plane_descriptors[k].overrides.det_size_override_kb;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10830
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_c = &mode_lib->mp.dcc_dram_bw_pref_overhead_factor_p1[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10832
calculate_mcache_setting_params->num_mcaches_l = &mode_lib->mp.num_mcaches_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10833
calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->mp.mcache_row_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10834
calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->mp.mcache_row_bytes_per_channel_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10835
calculate_mcache_setting_params->mcache_offsets_l = mode_lib->mp.mcache_offsets_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10836
calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->mp.mcache_shift_granularity_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10838
calculate_mcache_setting_params->num_mcaches_c = &mode_lib->mp.num_mcaches_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10839
calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->mp.mcache_row_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1084
} else if ((ForceSingleDPP ? 1 : DPPPerSurface[k]) * l->minDET_pipe <= l->DETBufferSizePoolInKByte) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10840
calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->mp.mcache_row_bytes_per_channel_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10841
calculate_mcache_setting_params->mcache_offsets_c = mode_lib->mp.mcache_offsets_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10842
calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->mp.mcache_shift_granularity_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10844
calculate_mcache_setting_params->mall_comb_mcache_l = &mode_lib->mp.mall_comb_mcache_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10845
calculate_mcache_setting_params->mall_comb_mcache_c = &mode_lib->mp.mall_comb_mcache_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10846
calculate_mcache_setting_params->lc_comb_mcache = &mode_lib->mp.lc_comb_mcache[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1085
DETBufferSizeInKByte[k] = l->minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1086
l->DETBufferSizePoolInKByte = l->DETBufferSizePoolInKByte - (ForceSingleDPP ? 1 : DPPPerSurface[k]) * l->minDET_pipe;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10888
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10889
s->TotalActiveDPP = s->TotalActiveDPP + mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1089
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10890
if (display_cfg->plane_descriptors[k].surface.dcc.enable)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10891
s->TotalDCCActiveDPP = s->TotalDCCActiveDPP + mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10894
for (k = 0; k <= s->num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10896
calculate_tdlut_setting_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10897
calculate_tdlut_setting_params->tdlut_width_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_width_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10898
calculate_tdlut_setting_params->tdlut_addressing_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_addressing_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1090
DML_LOG_VERBOSE("DML::%s: k=%u DETSizeOverride = %u\n", __func__, k, display_cfg->plane_descriptors[k].overrides.det_size_override_kb);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10901
calculate_tdlut_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10904
calculate_tdlut_setting_params->tdlut_pte_bytes_per_frame = &s->tdlut_pte_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10905
calculate_tdlut_setting_params->tdlut_bytes_per_frame = &s->tdlut_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10906
calculate_tdlut_setting_params->tdlut_groups_per_2row_ub = &s->tdlut_groups_per_2row_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10907
calculate_tdlut_setting_params->tdlut_opt_time = &s->tdlut_opt_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10908
calculate_tdlut_setting_params->tdlut_drain_time = &s->tdlut_drain_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10909
calculate_tdlut_setting_params->tdlut_bytes_to_deliver = &s->tdlut_bytes_to_deliver[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1091
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10910
calculate_tdlut_setting_params->tdlut_bytes_per_group = &s->tdlut_bytes_per_group[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10952
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10953
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10954
mode_lib->mp.WritebackDelay[k] =
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10957
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10958
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10959
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10960
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10961
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10962
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10963
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10964
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->mp.Dispclk;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
10966
mode_lib->mp.WritebackDelay[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1103
for (unsigned int k = 0; k < display_cfg->num_streams; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1104
l->TotalPixelRate += display_cfg->stream_descriptors[k].timing.pixel_clock_khz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11047
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11049
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11050
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11052
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11054
s->lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11055
mode_lib->mp.NoOfDPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11056
display_cfg->plane_descriptors[k].composition.viewport.plane0.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11057
display_cfg->plane_descriptors[k].composition.viewport.plane0.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11058
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11059
display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11061
s->lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11062
mode_lib->mp.NoOfDPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11063
display_cfg->plane_descriptors[k].composition.viewport.plane1.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11064
display_cfg->plane_descriptors[k].composition.viewport.plane1.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11065
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11066
display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11068
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11070
display_cfg->plane_descriptors[k].cursor.cursor_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11071
display_cfg->plane_descriptors[k].cursor.cursor_bpp,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11074
&s->cursor_lines_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11075
&s->cursor_bytes_per_line[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11076
&s->cursor_bytes_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11077
&s->cursor_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1108
for (unsigned int k = 0; k < display_cfg->num_streams; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11081
display_cfg->plane_descriptors[k].cursor.cursor_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11082
s->cursor_bytes_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11083
s->cursor_lines_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11084
s->line_times[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11088
&mode_lib->mp.UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1109
l->DETBudgetPerStream[k] = (unsigned int)((double) display_cfg->stream_descriptors[k].timing.pixel_clock_khz * MaxTotalDETInKByte / l->TotalPixelRate);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11091
mode_lib->mp.UrgentBurstFactorCursorPre[k] = mode_lib->mp.UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11094
&display_cfg->plane_descriptors[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11095
mode_lib->mp.swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11096
mode_lib->mp.swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11097
mode_lib->mp.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11098
mode_lib->mp.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11099
s->line_times[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1110
l->RemainingDETBudgetPerStream[k] = l->DETBudgetPerStream[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11101
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11102
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11103
mode_lib->mp.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11104
mode_lib->mp.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11105
mode_lib->mp.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11106
mode_lib->mp.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11109
&mode_lib->mp.UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11110
&mode_lib->mp.UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11111
&mode_lib->mp.NotEnoughUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11113
mode_lib->mp.NotEnoughUrgentLatencyHiding[k] = mode_lib->mp.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11116
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11117
s->MaxVStartupLines[k] = CalculateMaxVStartup(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11120
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11121
mode_lib->mp.WritebackDelay[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11124
DML_LOG_VERBOSE("DML::%s: k=%u MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11125
DML_LOG_VERBOSE("DML::%s: k=%u WritebackDelay = %f\n", __func__, k, mode_lib->mp.WritebackDelay[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11130
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11131
s->immediate_flip_required = s->immediate_flip_required || display_cfg->plane_descriptors[k].immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1114
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1115
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1116
l->TotalBandwidthPerStream[display_cfg->plane_descriptors[k].stream_index] += (unsigned int)(ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11172
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11175
DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11176
mode_lib->mp.TWait[k] = CalculateTWait(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11177
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11180
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11183
myPipe->Dppclk = mode_lib->mp.Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11185
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11187
myPipe->DPPPerSurface = mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11188
myPipe->ScalerEnabled = display_cfg->plane_descriptors[k].composition.scaler_info.enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11189
myPipe->VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1119
if (l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] >= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11190
myPipe->VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11191
myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11192
myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11193
myPipe->RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11194
myPipe->mirrored = display_cfg->plane_descriptors[k].composition.mirrored;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11195
myPipe->BlockWidth256BytesY = mode_lib->mp.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11196
myPipe->BlockHeight256BytesY = mode_lib->mp.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11197
myPipe->BlockWidth256BytesC = mode_lib->mp.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11198
myPipe->BlockHeight256BytesC = mode_lib->mp.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11199
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1120
l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11200
myPipe->NumberOfCursors = display_cfg->plane_descriptors[k].cursor.num_cursors;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11201
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11202
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11203
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11204
myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11205
myPipe->ODMMode = mode_lib->mp.ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11206
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11207
myPipe->BytePerPixelY = mode_lib->mp.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11208
myPipe->BytePerPixelC = mode_lib->mp.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11212
DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11217
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->mp.DSCDelay[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11223
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (unsigned int)(mode_lib->mp.SwathWidthY[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11224
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11226
CalculatePrefetchSchedule_params->VStartup = s->MaxVStartupLines[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11228
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11230
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = display_cfg->plane_descriptors[k].dynamic_meta_data.lines_before_active_required;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11231
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = display_cfg->plane_descriptors[k].dynamic_meta_data.transmitted_bytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11235
CalculatePrefetchSchedule_params->vm_bytes = mode_lib->mp.vm_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11236
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->mp.PixelPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11237
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->mp.PrefetchSourceLinesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11238
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->mp.VInitPreFillY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11239
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->mp.MaxNumSwathY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11240
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->mp.PrefetchSourceLinesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11241
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->mp.VInitPreFillC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11242
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->mp.MaxNumSwathC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11243
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->mp.swath_width_luma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11244
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->mp.swath_width_chroma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11245
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->mp.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11246
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->mp.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11247
CalculatePrefetchSchedule_params->TWait = mode_lib->mp.TWait[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11250
CalculatePrefetchSchedule_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11251
CalculatePrefetchSchedule_params->tdlut_pte_bytes_per_frame = s->tdlut_pte_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11252
CalculatePrefetchSchedule_params->tdlut_bytes_per_frame = s->tdlut_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11253
CalculatePrefetchSchedule_params->tdlut_opt_time = s->tdlut_opt_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11254
CalculatePrefetchSchedule_params->tdlut_drain_time = s->tdlut_drain_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11255
CalculatePrefetchSchedule_params->num_cursors = (display_cfg->plane_descriptors[k].cursor.cursor_width > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11256
CalculatePrefetchSchedule_params->cursor_bytes_per_chunk = s->cursor_bytes_per_chunk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11257
CalculatePrefetchSchedule_params->cursor_bytes_per_line = s->cursor_bytes_per_line[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11258
CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11260
CalculatePrefetchSchedule_params->meta_row_bytes = mode_lib->mp.meta_row_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11261
CalculatePrefetchSchedule_params->mall_prefetch_sdp_overhead_factor = mode_lib->mp.mall_prefetch_sdp_overhead_factor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11262
CalculatePrefetchSchedule_params->impacted_dst_y_pre = s->impacted_dst_y_pre[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11263
CalculatePrefetchSchedule_params->vactive_sw_bw_l = mode_lib->mp.vactive_sw_bw_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11264
CalculatePrefetchSchedule_params->vactive_sw_bw_c = mode_lib->mp.vactive_sw_bw_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11267
CalculatePrefetchSchedule_params->DSTXAfterScaler = &mode_lib->mp.DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11268
CalculatePrefetchSchedule_params->DSTYAfterScaler = &mode_lib->mp.DSTYAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11269
CalculatePrefetchSchedule_params->dst_y_prefetch = &mode_lib->mp.dst_y_prefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11270
CalculatePrefetchSchedule_params->dst_y_per_vm_vblank = &mode_lib->mp.dst_y_per_vm_vblank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11271
CalculatePrefetchSchedule_params->dst_y_per_row_vblank = &mode_lib->mp.dst_y_per_row_vblank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11272
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->mp.VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11273
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->mp.VRatioPrefetchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11274
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWLuma = &mode_lib->mp.RequiredPrefetchPixelDataBWLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11275
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWChroma = &mode_lib->mp.RequiredPrefetchPixelDataBWChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11276
CalculatePrefetchSchedule_params->RequiredPrefetchBWMax = &s->dummy_single_array[0][k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11277
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->mp.NotEnoughTimeForDynamicMetadata[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11278
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->mp.Tno_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11279
CalculatePrefetchSchedule_params->Tno_bw_flip = &mode_lib->mp.Tno_bw_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11280
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->mp.prefetch_vmrow_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11281
CalculatePrefetchSchedule_params->Tdmdl_vm = &mode_lib->mp.Tdmdl_vm[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11282
CalculatePrefetchSchedule_params->Tdmdl = &mode_lib->mp.Tdmdl[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11283
CalculatePrefetchSchedule_params->TSetup = &mode_lib->mp.TSetup[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11284
CalculatePrefetchSchedule_params->Tvm_trips = &s->Tvm_trips[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11285
CalculatePrefetchSchedule_params->Tr0_trips = &s->Tr0_trips[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11286
CalculatePrefetchSchedule_params->Tvm_trips_flip = &s->Tvm_trips_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11287
CalculatePrefetchSchedule_params->Tr0_trips_flip = &s->Tr0_trips_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11288
CalculatePrefetchSchedule_params->Tvm_trips_flip_rounded = &s->Tvm_trips_flip_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11289
CalculatePrefetchSchedule_params->Tr0_trips_flip_rounded = &s->Tr0_trips_flip_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11290
CalculatePrefetchSchedule_params->VUpdateOffsetPix = &mode_lib->mp.VUpdateOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11291
CalculatePrefetchSchedule_params->VUpdateWidthPix = &mode_lib->mp.VUpdateWidthPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11292
CalculatePrefetchSchedule_params->VReadyOffsetPix = &mode_lib->mp.VReadyOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11293
CalculatePrefetchSchedule_params->prefetch_cursor_bw = &mode_lib->mp.prefetch_cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11294
CalculatePrefetchSchedule_params->prefetch_sw_bytes = &s->prefetch_sw_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11295
CalculatePrefetchSchedule_params->Tpre_rounded = &s->Tpre_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11296
CalculatePrefetchSchedule_params->Tpre_oto = &s->Tpre_oto[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11299
mode_lib->mp.NoTimeToPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11301
if (s->impacted_dst_y_pre[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11302
mode_lib->mp.impacted_prefetch_margin_us[k] = (mode_lib->mp.dst_y_prefetch[k] - s->impacted_dst_y_pre[k]) * s->line_times[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11304
mode_lib->mp.impacted_prefetch_margin_us[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11307
DML_LOG_VERBOSE("DML::%s: k=%0u NoTimeToPrefetch=%0d\n", __func__, k, mode_lib->mp.NoTimeToPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11309
mode_lib->mp.VStartupMin[k] = s->MaxVStartupLines[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11313
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11314
if (mode_lib->mp.NoTimeToPrefetch[k] == true ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11315
mode_lib->mp.NotEnoughTimeForDynamicMetadata[k] ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11316
mode_lib->mp.DSTYAfterScaler[k] > 8) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11317
DML_LOG_VERBOSE("DML::%s: k=%u, NoTimeToPrefetch = %0d\n", __func__, k, mode_lib->mp.NoTimeToPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11318
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughTimeForDynamicMetadata=%u\n", __func__, k, mode_lib->mp.NotEnoughTimeForDynamicMetadata[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11319
DML_LOG_VERBOSE("DML::%s: k=%u, DSTYAfterScaler=%u (should be <= 0)\n", __func__, k, mode_lib->mp.DSTYAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11322
if (mode_lib->mp.dst_y_prefetch[k] < 2)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11325
if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11326
mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11328
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchY=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11329
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPrefetchC=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1133
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11333
if (mode_lib->mp.NotEnoughUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11334
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHiding = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1134
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1135
l->IdealDETBudget = (unsigned int)(((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l->TotalBandwidthPerStream[display_cfg->plane_descriptors[k].stream_index])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11350
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11351
double line_time_us = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11352
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11354
&display_cfg->plane_descriptors[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11355
mode_lib->mp.swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11356
mode_lib->mp.swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11357
mode_lib->mp.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11358
mode_lib->mp.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1136
* l->DETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11361
mode_lib->mp.VRatioPrefetchY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11362
mode_lib->mp.VRatioPrefetchC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11363
mode_lib->mp.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11364
mode_lib->mp.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11365
mode_lib->mp.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11366
mode_lib->mp.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11368
&mode_lib->mp.UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11369
&mode_lib->mp.UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11370
&mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11373
DML_LOG_VERBOSE("DML::%s: k=%0u DPPPerSurface=%u\n", __func__, k, mode_lib->mp.NoOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11374
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLuma=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11375
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChroma=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11376
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorLumaPre=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorLumaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11377
DML_LOG_VERBOSE("DML::%s: k=%0u UrgentBurstFactorChromaPre=%f\n", __func__, k, mode_lib->mp.UrgentBurstFactorChromaPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11379
DML_LOG_VERBOSE("DML::%s: k=%0u VRatioPrefetchY=%f\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1138
if (l->IdealDETBudget > DETBufferSizeInKByte[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11380
DML_LOG_VERBOSE("DML::%s: k=%0u VRatioY=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11382
DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_vmrow_bw=%f\n", __func__, k, mode_lib->mp.prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11383
DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_l=%f\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11384
DML_LOG_VERBOSE("DML::%s: k=%0u vactive_sw_bw_c=%f\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11385
DML_LOG_VERBOSE("DML::%s: k=%0u cursor_bw=%f\n", __func__, k, mode_lib->mp.cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11386
DML_LOG_VERBOSE("DML::%s: k=%0u dpte_row_bw=%f\n", __func__, k, mode_lib->mp.dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11387
DML_LOG_VERBOSE("DML::%s: k=%0u meta_row_bw=%f\n", __func__, k, mode_lib->mp.meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11388
DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWLuma=%f\n", __func__, k, mode_lib->mp.RequiredPrefetchPixelDataBWLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11389
DML_LOG_VERBOSE("DML::%s: k=%0u RequiredPrefetchPixelDataBWChroma=%f\n", __func__, k, mode_lib->mp.RequiredPrefetchPixelDataBWChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1139
l->DeltaDETBudget = l->IdealDETBudget - DETBufferSizeInKByte[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11390
DML_LOG_VERBOSE("DML::%s: k=%0u prefetch_cursor_bw=%f\n", __func__, k, mode_lib->mp.prefetch_cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11394
for (k = 0; k <= s->num_active_planes - 1; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11395
mode_lib->mp.final_flip_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1140
if (l->DeltaDETBudget > l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1141
l->DeltaDETBudget = l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1144
DETBufferSizeInKByte[k] += (unsigned int)((double)l->DeltaDETBudget / (ForceSingleDPP ? 1 : DPPPerSurface[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1145
l->RemainingDETBudgetPerStream[display_cfg->plane_descriptors[k].stream_index] -= l->DeltaDETBudget;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11456
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11457
if (mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11458
DML_LOG_VERBOSE("DML::%s: k=%u, NotEnoughUrgentLatencyHidingPre = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11473
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11474
if (display_cfg->plane_descriptors[k].immediate_flip) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11475
s->per_pipe_flip_bytes[k] = get_pipe_flip_bytes(s->HostVMInefficiencyFactor,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11476
mode_lib->mp.vm_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11477
mode_lib->mp.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11478
mode_lib->mp.meta_row_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11480
s->per_pipe_flip_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11482
mode_lib->mp.TotImmediateFlipBytes += s->per_pipe_flip_bytes[k] * mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11484
DML_LOG_VERBOSE("DML::%s: k = %u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11485
DML_LOG_VERBOSE("DML::%s: DPPPerSurface = %u\n", __func__, mode_lib->mp.NoOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11486
DML_LOG_VERBOSE("DML::%s: vm_bytes = %u\n", __func__, mode_lib->mp.vm_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11487
DML_LOG_VERBOSE("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, mode_lib->mp.PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11488
DML_LOG_VERBOSE("DML::%s: meta_row_bytes = %u\n", __func__, mode_lib->mp.meta_row_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1149
DETBufferSizeInKByte[k] = (DETBufferSizeInKByte[k] / ConfigReturnBufferSegmentSizeInkByte) * ConfigReturnBufferSegmentSizeInkByte;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11492
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11495
display_cfg->plane_descriptors[k].immediate_flip,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11498
s->Tvm_trips_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11499
s->Tr0_trips_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11500
s->Tvm_trips_flip_rounded[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11501
s->Tr0_trips_flip_rounded[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11503
mode_lib->mp.vm_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11504
mode_lib->mp.PixelPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11507
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11508
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11509
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1151
l->ResidualDETAfterRounding -= DETBufferSizeInKByte[k] * (ForceSingleDPP ? 1 : DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11510
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11511
mode_lib->mp.Tno_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11512
mode_lib->mp.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11513
mode_lib->mp.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11514
mode_lib->mp.use_one_row_for_frame_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11517
s->per_pipe_flip_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11518
mode_lib->mp.meta_row_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11519
mode_lib->mp.meta_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11520
mode_lib->mp.meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11521
mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11524
&mode_lib->mp.dst_y_per_vm_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11525
&mode_lib->mp.dst_y_per_row_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11526
&mode_lib->mp.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11527
&mode_lib->mp.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11584
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11585
if (display_cfg->plane_descriptors[k].immediate_flip && mode_lib->mp.ImmediateFlipSupportedForPipe[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11588
DML_LOG_VERBOSE("DML::%s: Pipe %0d not supporting iflip!\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1159
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1160
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11602
for (k = 0; k < s->num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11603
DML_LOG_VERBOSE("DML::%s: immediate_flip_required[%u] = %u\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11608
DML_LOG_VERBOSE("DML::%s: Done one iteration: k=%d, MaxVStartupLines=%u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1161
l->TotalBandwidth = l->TotalBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11611
for (k = 0; k < s->num_active_planes; ++k)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11612
DML_LOG_VERBOSE("DML::%s: k=%d MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11620
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11622
DML_LOG_VERBOSE("DML::%s: Calculate DCC configuration for surface k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11625
display_cfg->plane_descriptors[k].surface.dcc.enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11627
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11628
display_cfg->plane_descriptors[k].surface.plane0.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11629
display_cfg->plane_descriptors[k].surface.plane1.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11630
display_cfg->plane_descriptors[k].surface.plane0.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11631
display_cfg->plane_descriptors[k].surface.plane1.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11633
mode_lib->mp.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11634
mode_lib->mp.Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11635
display_cfg->plane_descriptors[k].surface.tiling,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11636
mode_lib->mp.BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11637
mode_lib->mp.BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11638
mode_lib->mp.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11639
mode_lib->mp.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11640
display_cfg->plane_descriptors[k].composition.rotation_angle,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11643
&mode_lib->mp.RequestLuma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11644
&mode_lib->mp.RequestChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11645
&mode_lib->mp.DCCYMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11646
&mode_lib->mp.DCCCMaxUncompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11647
&mode_lib->mp.DCCYMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11648
&mode_lib->mp.DCCCMaxCompressedBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11649
&mode_lib->mp.DCCYIndependentBlock[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1165
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11650
&mode_lib->mp.DCCCIndependentBlock[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1166
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1171
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11717
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11718
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11719
mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11720
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackDRAMClockChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11721
mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = math_max2(0, mode_lib->mp.VStartupMin[k] * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11722
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) - mode_lib->mp.Watermark.WritebackFCLKChangeWatermark);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11724
mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11725
mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1173
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1174
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1175
} else if (display_cfg->plane_descriptors[k].overrides.det_size_override_kb > 0 || (((double)(ForceSingleDPP ? 1 : DPPPerSurface[k]) * (double)DETBufferSizeInKByte[k] / (double)MaxTotalDETInKByte) >= ((ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) / l->TotalBandwidth))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1176
DETPieceAssignedToThisSurfaceAlready[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1177
l->BandwidthOfSurfacesNotAssignedDETPiece = l->BandwidthOfSurfacesNotAssignedDETPiece - ReadBandwidthLuma[k] - ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1179
DETPieceAssignedToThisSurfaceAlready[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1181
DML_LOG_VERBOSE("DML::%s: k=%u DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, k, DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1182
DML_LOG_VERBOSE("DML::%s: k=%u BandwidthOfSurfacesNotAssignedDETPiece = %f\n", __func__, k, l->BandwidthOfSurfacesNotAssignedDETPiece);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11836
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11839
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TWait[k] + mode_lib->mp.ExtraLatency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11840
if (!display_cfg->plane_descriptors[k].dynamic_meta_data.enable)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11841
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.TCalc + mode_lib->mp.MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11844
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f (before vstartup margin)\n", __func__, k, mode_lib->mp.MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11846
s->Tvstartup_margin = (s->MaxVStartupLines[k] - mode_lib->mp.VStartupMin[k]) * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11847
mode_lib->mp.MinTTUVBlank[k] = mode_lib->mp.MinTTUVBlank[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11850
DML_LOG_VERBOSE("DML::%s: k=%u, Tvstartup_margin = %f\n", __func__, k, s->Tvstartup_margin);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11851
DML_LOG_VERBOSE("DML::%s: k=%u, MaxVStartupLines = %u\n", __func__, k, s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11852
DML_LOG_VERBOSE("DML::%s: k=%u, MinTTUVBlank = %f\n", __func__, k, mode_lib->mp.MinTTUVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11855
mode_lib->mp.Tdmdl[k] = mode_lib->mp.Tdmdl[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11856
if (display_cfg->plane_descriptors[k].dynamic_meta_data.enable && mode_lib->ip.dynamic_metadata_vm_enabled) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11857
mode_lib->mp.Tdmdl_vm[k] = mode_lib->mp.Tdmdl_vm[k] + s->Tvstartup_margin;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11860
isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11863
mode_lib->mp.VStartup[k] = (isInterlaceTiming ? (2 * s->MaxVStartupLines[k]) : s->MaxVStartupLines[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11865
s->dlg_vblank_start = ((isInterlaceTiming ? math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11866
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total) - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11867
s->LSetup = math_floor2(4.0 * mode_lib->mp.TSetup[k] / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)), 1.0) / 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11868
s->blank_lines_remaining = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active) - mode_lib->mp.VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11875
mode_lib->mp.MIN_DST_Y_NEXT_START[k] = s->dlg_vblank_start + s->blank_lines_remaining + s->LSetup;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11878
if (((mode_lib->mp.VUpdateOffsetPix[k] + mode_lib->mp.VUpdateWidthPix[k] + mode_lib->mp.VReadyOffsetPix[k]) / (double) display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) <=
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11880
math_floor2((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]) / 2.0, 1.0) :
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11881
(int)(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch - mode_lib->mp.VStartup[k]))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11882
mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11884
mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11887
DML_LOG_VERBOSE("DML::%s: k=%u, VStartup = %u (max)\n", __func__, k, mode_lib->mp.VStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11888
DML_LOG_VERBOSE("DML::%s: k=%u, VStartupMin = %u (max)\n", __func__, k, mode_lib->mp.VStartupMin[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11889
DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateOffsetPix = %u\n", __func__, k, mode_lib->mp.VUpdateOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1189
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11890
DML_LOG_VERBOSE("DML::%s: k=%u, VUpdateWidthPix = %u\n", __func__, k, mode_lib->mp.VUpdateWidthPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11891
DML_LOG_VERBOSE("DML::%s: k=%u, VReadyOffsetPix = %u\n", __func__, k, mode_lib->mp.VReadyOffsetPix[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11892
DML_LOG_VERBOSE("DML::%s: k=%u, HTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11893
DML_LOG_VERBOSE("DML::%s: k=%u, VTotal = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11894
DML_LOG_VERBOSE("DML::%s: k=%u, VActive = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11895
DML_LOG_VERBOSE("DML::%s: k=%u, VFrontPorch = %lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_front_porch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11896
DML_LOG_VERBOSE("DML::%s: k=%u, TSetup = %f\n", __func__, k, mode_lib->mp.TSetup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11897
DML_LOG_VERBOSE("DML::%s: k=%u, MIN_DST_Y_NEXT_START = %f\n", __func__, k, mode_lib->mp.MIN_DST_Y_NEXT_START[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11898
DML_LOG_VERBOSE("DML::%s: k=%u, VREADY_AT_OR_AFTER_VSYNC = %u\n", __func__, k, mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1190
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[k] = %f\n", __func__, j, k, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11904
for (k = 0; k < display_cfg->num_streams; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11906
if (display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11907
s->WRBandwidth = display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11908
* display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_width /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11909
(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1191
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[k] = %f\n", __func__, j, k, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11910
/ ((double)display_cfg->stream_descriptors[k].timing.pixel_clock_khz / 1000))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11911
* (display_cfg->stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11917
for (k = 0; k < s->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11918
mode_lib->mp.TotalDataReadBandwidth = mode_lib->mp.TotalDataReadBandwidth + mode_lib->mp.vactive_sw_bw_l[k] + mode_lib->mp.vactive_sw_bw_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1192
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthLuma[Next] = %f\n", __func__, j, k, ReadBandwidthLuma[l->NextSurfaceToAssignDETPiece]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11920
DML_LOG_VERBOSE("DML::%s: k=%u, TotalDataReadBandwidth = %f\n", __func__, k, mode_lib->mp.TotalDataReadBandwidth);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11921
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib->mp.vactive_sw_bw_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
11922
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib->mp.vactive_sw_bw_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1193
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, ReadBandwidthChroma[Next] = %f\n", __func__, j, k, ReadBandwidthChroma[l->NextSurfaceToAssignDETPiece]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1194
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextSurfaceToAssignDETPiece = %u\n", __func__, j, k, l->NextSurfaceToAssignDETPiece);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1195
if (!DETPieceAssignedToThisSurfaceAlready[k] && (!NextPotentialSurfaceToAssignDETPieceFound ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1196
ReadBandwidthLuma[k] + ReadBandwidthChroma[k] < ReadBandwidthLuma[l->NextSurfaceToAssignDETPiece] + ReadBandwidthChroma[l->NextSurfaceToAssignDETPiece])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1197
l->NextSurfaceToAssignDETPiece = k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1200
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, DETPieceAssignedToThisSurfaceAlready = %u\n", __func__, j, k, DETPieceAssignedToThisSurfaceAlready[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1201
DML_LOG_VERBOSE("DML::%s: j=%u k=%u, NextPotentialSurfaceToAssignDETPieceFound = %u\n", __func__, j, k, NextPotentialSurfaceToAssignDETPieceFound);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1234
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1235
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u (TotalReadBandWidth=%f)\n", __func__, k, DETBufferSizeInKByte[k], ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
12975
unsigned int k, n;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13032
for (k = 0; k < out->display_config.num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13034
out->informative.mode_support_info.FCLKChangeSupport[k] = mode_lib->ms.support.FCLKChangeSupport[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13035
out->informative.mode_support_info.MPCCombineEnable[k] = mode_lib->ms.support.MPCCombineEnable[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13036
out->informative.mode_support_info.ODMMode[k] = mode_lib->ms.support.ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13037
out->informative.mode_support_info.DPPPerSurface[k] = mode_lib->ms.support.DPPPerSurface[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13038
out->informative.mode_support_info.DSCEnabled[k] = mode_lib->ms.support.DSCEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13039
out->informative.mode_support_info.FECEnabled[k] = mode_lib->ms.support.FECEnabled[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13040
out->informative.mode_support_info.NumberOfDSCSlices[k] = mode_lib->ms.support.NumberOfDSCSlices[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13041
out->informative.mode_support_info.OutputBpp[k] = mode_lib->ms.support.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13043
if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_unknown)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13044
out->informative.mode_support_info.OutputType[k] = dml2_output_type_unknown;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13045
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13046
out->informative.mode_support_info.OutputType[k] = dml2_output_type_dp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13047
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_edp)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13048
out->informative.mode_support_info.OutputType[k] = dml2_output_type_edp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13049
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_dp2p0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13050
out->informative.mode_support_info.OutputType[k] = dml2_output_type_dp2p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13051
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmi)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13052
out->informative.mode_support_info.OutputType[k] = dml2_output_type_hdmi;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13053
else if (mode_lib->ms.support.OutputType[k] == dml2_core_internal_output_type_hdmifrl)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13054
out->informative.mode_support_info.OutputType[k] = dml2_output_type_hdmifrl;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13056
if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_unknown)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13057
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_unknown;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13058
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13059
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13060
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr2)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13061
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13062
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_hbr3)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13063
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_hbr3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13064
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr10)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13065
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr10;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13066
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr13p5)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13067
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr13p5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13068
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_dp_rate_uhbr20)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13069
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_dp_rate_uhbr20;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13070
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_3x3)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13071
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_3x3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13072
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x3)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13073
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13074
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_6x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13075
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_6x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13076
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_8x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13077
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_8x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13078
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_10x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13079
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_10x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13080
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_12x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13081
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_12x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13082
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_16x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13083
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_16x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13084
else if (mode_lib->ms.support.OutputRate[k] == dml2_core_internal_output_rate_hdmi_rate_20x4)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13085
out->informative.mode_support_info.OutputRate[k] = dml2_output_rate_hdmi_rate_20x4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13087
out->informative.mode_support_info.AlignedYPitch[k] = mode_lib->ms.support.AlignedYPitch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13088
out->informative.mode_support_info.AlignedCPitch[k] = mode_lib->ms.support.AlignedCPitch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13107
for (k = 0; k < out->display_config.num_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13108
out->informative.mall.total_surface_size_in_mall_bytes += mode_lib->mp.SurfaceSizeInTheMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13109
out->informative.dpp.total_num_dpps_required += mode_lib->mp.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13191
for (k = 0; k < out->display_config.num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13196
out->informative.misc.PrefetchMode[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13199
out->informative.misc.PrefetchMode[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13201
out->informative.misc.PrefetchMode[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13203
out->informative.misc.PrefetchMode[k] = 3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13205
out->informative.misc.min_ttu_vblank_us[k] = mode_lib->mp.MinTTUVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13206
out->informative.mall.subviewport_lines_needed_in_mall[k] = mode_lib->mp.SubViewportLinesNeededInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13207
out->informative.crb.det_size_in_kbytes[k] = mode_lib->mp.DETBufferSizeInKByte[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13208
out->informative.crb.DETBufferSizeY[k] = mode_lib->mp.DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13209
out->informative.misc.ImmediateFlipSupportedForPipe[k] = mode_lib->mp.ImmediateFlipSupportedForPipe[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13210
out->informative.misc.UsesMALLForStaticScreen[k] = mode_lib->mp.is_using_mall_for_ss[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13211
out->informative.plane_info[k].dpte_row_height_plane0 = mode_lib->mp.dpte_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13212
out->informative.plane_info[k].dpte_row_height_plane1 = mode_lib->mp.dpte_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13213
out->informative.plane_info[k].meta_row_height_plane0 = mode_lib->mp.meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13214
out->informative.plane_info[k].meta_row_height_plane1 = mode_lib->mp.meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13215
out->informative.dcc_control[k].max_uncompressed_block_plane0 = mode_lib->mp.DCCYMaxUncompressedBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13216
out->informative.dcc_control[k].max_compressed_block_plane0 = mode_lib->mp.DCCYMaxCompressedBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13217
out->informative.dcc_control[k].independent_block_plane0 = mode_lib->mp.DCCYIndependentBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13218
out->informative.dcc_control[k].max_uncompressed_block_plane1 = mode_lib->mp.DCCCMaxUncompressedBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13219
out->informative.dcc_control[k].max_compressed_block_plane1 = mode_lib->mp.DCCCMaxCompressedBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13220
out->informative.dcc_control[k].independent_block_plane1 = mode_lib->mp.DCCCIndependentBlock[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13221
out->informative.misc.dst_x_after_scaler[k] = mode_lib->mp.DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13222
out->informative.misc.dst_y_after_scaler[k] = mode_lib->mp.DSTYAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13223
out->informative.misc.prefetch_source_lines_plane0[k] = mode_lib->mp.PrefetchSourceLinesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13224
out->informative.misc.prefetch_source_lines_plane1[k] = mode_lib->mp.PrefetchSourceLinesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13225
out->informative.misc.vready_at_or_after_vsync[k] = mode_lib->mp.VREADY_AT_OR_AFTER_VSYNC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13226
out->informative.misc.min_dst_y_next_start[k] = mode_lib->mp.MIN_DST_Y_NEXT_START[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13227
out->informative.plane_info[k].swath_width_plane0 = mode_lib->mp.SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13228
out->informative.plane_info[k].swath_height_plane0 = mode_lib->mp.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13229
out->informative.plane_info[k].swath_height_plane1 = mode_lib->mp.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13230
out->informative.misc.CursorDstXOffset[k] = mode_lib->mp.CursorDstXOffset[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13231
out->informative.misc.CursorDstYOffset[k] = mode_lib->mp.CursorDstYOffset[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13232
out->informative.misc.CursorChunkHDLAdjust[k] = mode_lib->mp.CursorChunkHDLAdjust[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13233
out->informative.misc.dpte_group_bytes[k] = mode_lib->mp.dpte_group_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13234
out->informative.misc.vm_group_bytes[k] = mode_lib->mp.vm_group_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13235
out->informative.misc.DisplayPipeRequestDeliveryTimeLuma[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13236
out->informative.misc.DisplayPipeRequestDeliveryTimeChroma[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13237
out->informative.misc.DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeLumaPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13238
out->informative.misc.DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeRequestDeliveryTimeChromaPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13239
out->informative.misc.TimePerVMGroupVBlank[k] = mode_lib->mp.TimePerVMGroupVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13240
out->informative.misc.TimePerVMGroupFlip[k] = mode_lib->mp.TimePerVMGroupFlip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13241
out->informative.misc.TimePerVMRequestVBlank[k] = mode_lib->mp.TimePerVMRequestVBlank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13242
out->informative.misc.TimePerVMRequestFlip[k] = mode_lib->mp.TimePerVMRequestFlip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13243
out->informative.misc.Tdmdl_vm[k] = mode_lib->mp.Tdmdl_vm[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13244
out->informative.misc.Tdmdl[k] = mode_lib->mp.Tdmdl[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13245
out->informative.misc.VStartup[k] = mode_lib->mp.VStartup[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13246
out->informative.misc.VUpdateOffsetPix[k] = mode_lib->mp.VUpdateOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13247
out->informative.misc.VUpdateWidthPix[k] = mode_lib->mp.VUpdateWidthPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13248
out->informative.misc.VReadyOffsetPix[k] = mode_lib->mp.VReadyOffsetPix[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13250
out->informative.misc.DST_Y_PER_PTE_ROW_NOM_L[k] = mode_lib->mp.DST_Y_PER_PTE_ROW_NOM_L[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13251
out->informative.misc.DST_Y_PER_PTE_ROW_NOM_C[k] = mode_lib->mp.DST_Y_PER_PTE_ROW_NOM_C[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13252
out->informative.misc.time_per_pte_group_nom_luma[k] = mode_lib->mp.time_per_pte_group_nom_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13253
out->informative.misc.time_per_pte_group_nom_chroma[k] = mode_lib->mp.time_per_pte_group_nom_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13254
out->informative.misc.time_per_pte_group_vblank_luma[k] = mode_lib->mp.time_per_pte_group_vblank_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13255
out->informative.misc.time_per_pte_group_vblank_chroma[k] = mode_lib->mp.time_per_pte_group_vblank_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13256
out->informative.misc.time_per_pte_group_flip_luma[k] = mode_lib->mp.time_per_pte_group_flip_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13257
out->informative.misc.time_per_pte_group_flip_chroma[k] = mode_lib->mp.time_per_pte_group_flip_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13258
out->informative.misc.VRatioPrefetchY[k] = mode_lib->mp.VRatioPrefetchY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13259
out->informative.misc.VRatioPrefetchC[k] = mode_lib->mp.VRatioPrefetchC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13260
out->informative.misc.DestinationLinesForPrefetch[k] = mode_lib->mp.dst_y_prefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13261
out->informative.misc.DestinationLinesToRequestVMInVBlank[k] = mode_lib->mp.dst_y_per_vm_vblank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13262
out->informative.misc.DestinationLinesToRequestRowInVBlank[k] = mode_lib->mp.dst_y_per_row_vblank[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13263
out->informative.misc.DestinationLinesToRequestVMInImmediateFlip[k] = mode_lib->mp.dst_y_per_vm_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13264
out->informative.misc.DestinationLinesToRequestRowInImmediateFlip[k] = mode_lib->mp.dst_y_per_row_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13265
out->informative.misc.DisplayPipeLineDeliveryTimeLuma[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13266
out->informative.misc.DisplayPipeLineDeliveryTimeChroma[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13267
out->informative.misc.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLumaPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13268
out->informative.misc.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChromaPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13271
out->informative.misc.WritebackAllowDRAMClockChangeEndPosition[k] = mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13272
out->informative.misc.WritebackAllowFCLKChangeEndPosition[k] = mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13273
out->informative.misc.DSCCLK_calculated[k] = mode_lib->mp.DSCCLK[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13274
out->informative.misc.BIGK_FRAGMENT_SIZE[k] = mode_lib->mp.BIGK_FRAGMENT_SIZE[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13275
out->informative.misc.PTE_BUFFER_MODE[k] = mode_lib->mp.PTE_BUFFER_MODE[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13276
out->informative.misc.DSCDelay[k] = mode_lib->mp.DSCDelay[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13277
out->informative.misc.MaxActiveDRAMClockChangeLatencySupported[k] = mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13279
if (mode_lib->mp.impacted_prefetch_margin_us[k] < out->informative.misc.LowestPrefetchMargin)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13280
out->informative.misc.LowestPrefetchMargin = mode_lib->mp.impacted_prefetch_margin_us[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13286
for (k = 0; k < out->display_config.num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13287
out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane0 = dml_get_plane_num_mcaches_plane0(mode_lib, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13288
out->informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane0 = dml_get_plane_mcache_row_bytes_plane0(mode_lib, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13290
for (n = 0; n < out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane0; n++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13291
out->informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane0[n] = dml_get_plane_array_mcache_offsets_plane0(mode_lib, k, n);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13292
out->informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane0[n] = k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13295
out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane1 = dml_get_plane_num_mcaches_plane1(mode_lib, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13296
out->informative.non_optimized_mcache_allocation[k].informative.meta_row_bytes_plane1 = dml_get_plane_mcache_row_bytes_plane1(mode_lib, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13298
for (n = 0; n < out->informative.non_optimized_mcache_allocation[k].num_mcaches_plane1; n++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13299
out->informative.non_optimized_mcache_allocation[k].mcache_x_offsets_plane1[n] = dml_get_plane_array_mcache_offsets_plane1(mode_lib, k, n);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
13300
out->informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane1[n] = k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
159
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
160
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
161
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
162
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
164
out_bpp[k] = bpc * 3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
167
out_bpp[k] = bpc * 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
170
out_bpp[k] = bpc * 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
174
out_bpp[k] = bpc * 1.5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
177
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
178
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
180
out_bpp[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
182
DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
183
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
184
DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1957
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1958
is_using_mall_for_ss[k] = (display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1959
if (is_using_mall_for_ss[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1960
TotalSurfaceSizeInMALL = TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1962
DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, is_using_mall_for_ss[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1963
DML_LOG_VERBOSE("DML::%s: k=%u, TotalSurfaceSizeInMALL = %u\n", __func__, k, TotalSurfaceSizeInMALL);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1971
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1972
if (TotalSurfaceSizeInMALL + SurfaceSizeInMALL[k] <= MALLAllocatedForDCN * 1024 * 1024 &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1973
!is_using_mall_for_ss[k] && display_cfg->plane_descriptors[k].overrides.refresh_from_mall != dml2_refresh_from_mall_mode_override_force_disable && one_row_per_frame_fits_in_buffer[k] &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1974
(!CanAddAnotherSurfaceToMALL || SurfaceSizeInMALL[k] < SurfaceSizeInMALL[SurfaceToAddToMALL])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1976
SurfaceToAddToMALL = k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
1977
DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForStaticScreen = %u (dis, en, optimize)\n", __func__, k, display_cfg->plane_descriptors[k].overrides.refresh_from_mall);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
209
for (unsigned int k = 0; k < num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
210
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
221
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
222
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2634
for (unsigned int k = 0; k < num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2635
mall_prefetch_sdp_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2636
mall_prefetch_dram_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2639
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall) // always no data return
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2640
mall_prefetch_sdp_overhead_factor[k] = 1.25;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2641
else if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2642
mall_prefetch_sdp_overhead_factor[k] = 0.25;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2645
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2646
mall_prefetch_dram_overhead_factor[k] = 2.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2649
DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_sdp_overhead_factor = %f\n", __func__, k, mall_prefetch_sdp_overhead_factor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2650
DML_LOG_VERBOSE("DML::%s: k=%u, mall_prefetch_dram_overhead_factor = %f\n", __func__, k, mall_prefetch_dram_overhead_factor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2817
unsigned int n, m, k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2830
for (k = 0; k < num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2832
DML_LOG_VERBOSE("DML::%s: plane %0d\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2833
DML_LOG_VERBOSE("DML::%s: ReadBandwidthLuma=%f\n", __func__, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2834
DML_LOG_VERBOSE("DML::%s: ReadBandwidthChroma=%f\n", __func__, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2835
DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p0=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p0[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2836
DML_LOG_VERBOSE("DML::%s: dcc_dram_bw_nom_overhead_factor_p1=%f\n", __func__, dcc_dram_bw_nom_overhead_factor_p1[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2837
DML_LOG_VERBOSE("DML::%s: mall_prefetch_dram_overhead_factor=%f\n", __func__, mall_prefetch_dram_overhead_factor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2838
DML_LOG_VERBOSE("DML::%s: mall_prefetch_sdp_overhead_factor=%f\n", __func__, mall_prefetch_sdp_overhead_factor[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2841
sdp_overhead_factor = mall_prefetch_sdp_overhead_factor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2842
dram_overhead_factor_p0 = dcc_dram_bw_nom_overhead_factor_p0[k] * mall_prefetch_dram_overhead_factor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2843
dram_overhead_factor_p1 = dcc_dram_bw_nom_overhead_factor_p1[k] * mall_prefetch_dram_overhead_factor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2847
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2848
avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2849
avg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2851
avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_sdp] += sdp_overhead_factor * (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]) + cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2852
avg_bandwidth_required[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram] += dram_overhead_factor_p0 * ReadBandwidthLuma[k] + dram_overhead_factor_p1 * ReadBandwidthChroma[k] + cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2870
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2872
p->vm_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2873
p->dpte_group_bytes[k] = 512;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2875
p->vm_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2876
p->dpte_group_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2879
if (dml_is_420(p->myPipe[k].SourcePixelFormat) || p->myPipe[k].SourcePixelFormat == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2880
if ((p->myPipe[k].SourcePixelFormat == dml2_420_10 || p->myPipe[k].SourcePixelFormat == dml2_420_12) && !dml_is_vertical_rotation(p->myPipe[k].RotationAngle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2881
s->PTEBufferSizeInRequestsForLuma[k] = (p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma) / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2882
s->PTEBufferSizeInRequestsForChroma[k] = s->PTEBufferSizeInRequestsForLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2884
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2885
s->PTEBufferSizeInRequestsForChroma[k] = p->PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2888
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2889
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2890
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2891
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2892
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2893
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2894
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2895
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2896
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2897
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2898
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeightC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2899
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStartC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2900
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStartC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2903
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2904
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2905
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2906
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2907
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2908
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2909
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2912
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2913
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2914
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_chroma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2915
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2916
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2917
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowC_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2918
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_chroma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2919
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_chroma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2920
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2921
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2922
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2923
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2924
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2925
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2927
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2928
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2929
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2930
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2931
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2932
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2936
p->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2937
p->myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2938
p->myPipe[k].VTapsChroma,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2939
p->myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2940
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2941
p->myPipe[k].SwathHeightC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2942
p->myPipe[k].RotationAngle,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2943
p->myPipe[k].mirrored,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2944
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2945
p->SwathWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2946
p->myPipe[k].ViewportHeightC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2947
p->myPipe[k].ViewportXStartC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2948
p->myPipe[k].ViewportYStartC,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2951
&p->VInitPreFillC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2952
&p->MaxNumSwathC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2954
s->PTEBufferSizeInRequestsForLuma[k] = p->PTEBufferSizeInRequestsLuma + p->PTEBufferSizeInRequestsChroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2955
s->PTEBufferSizeInRequestsForChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2956
s->PixelPTEBytesPerRowC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2957
s->PixelPTEBytesPerRowStorageC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2959
p->MaxNumSwathC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2960
p->PrefetchSourceLinesC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2961
s->dpte_row_height_chroma_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2962
s->dpte_row_width_chroma_ub_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2963
s->PixelPTEBytesPerRowC_one_row_per_frame[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2966
scratch->calculate_vm_and_row_bytes_params.ViewportStationary = p->myPipe[k].ViewportStationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2967
scratch->calculate_vm_and_row_bytes_params.DCCEnable = p->myPipe[k].DCCEnable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2968
scratch->calculate_vm_and_row_bytes_params.NumberOfDPPs = p->myPipe[k].DPPPerSurface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2969
scratch->calculate_vm_and_row_bytes_params.BlockHeight256Bytes = p->myPipe[k].BlockHeight256BytesY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2970
scratch->calculate_vm_and_row_bytes_params.BlockWidth256Bytes = p->myPipe[k].BlockWidth256BytesY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2971
scratch->calculate_vm_and_row_bytes_params.SourcePixelFormat = p->myPipe[k].SourcePixelFormat;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2972
scratch->calculate_vm_and_row_bytes_params.SurfaceTiling = p->myPipe[k].SurfaceTiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2973
scratch->calculate_vm_and_row_bytes_params.BytePerPixel = p->myPipe[k].BytePerPixelY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2974
scratch->calculate_vm_and_row_bytes_params.RotationAngle = p->myPipe[k].RotationAngle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2975
scratch->calculate_vm_and_row_bytes_params.SwathWidth = p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2976
scratch->calculate_vm_and_row_bytes_params.ViewportHeight = p->myPipe[k].ViewportHeight;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2977
scratch->calculate_vm_and_row_bytes_params.ViewportXStart = p->myPipe[k].ViewportXStart;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2978
scratch->calculate_vm_and_row_bytes_params.ViewportYStart = p->myPipe[k].ViewportYStart;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2981
scratch->calculate_vm_and_row_bytes_params.GPUVMMinPageSizeKBytes = p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2982
scratch->calculate_vm_and_row_bytes_params.PTEBufferSizeInRequests = s->PTEBufferSizeInRequestsForLuma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2983
scratch->calculate_vm_and_row_bytes_params.Pitch = p->myPipe[k].PitchY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2984
scratch->calculate_vm_and_row_bytes_params.MacroTileWidth = p->myPipe[k].BlockWidthY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2985
scratch->calculate_vm_and_row_bytes_params.MacroTileHeight = p->myPipe[k].BlockHeightY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2986
scratch->calculate_vm_and_row_bytes_params.is_phantom = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2987
scratch->calculate_vm_and_row_bytes_params.DCCMetaPitch = p->myPipe[k].DCCMetaPitchY;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2990
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow = &s->PixelPTEBytesPerRowY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2991
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRowStorage = &s->PixelPTEBytesPerRowStorageY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2992
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub = &p->dpte_row_width_luma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2993
scratch->calculate_vm_and_row_bytes_params.dpte_row_height = &p->dpte_row_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2994
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_linear = &p->dpte_row_height_linear_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2995
scratch->calculate_vm_and_row_bytes_params.PixelPTEBytesPerRow_one_row_per_frame = &s->PixelPTEBytesPerRowY_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2996
scratch->calculate_vm_and_row_bytes_params.dpte_row_width_ub_one_row_per_frame = &s->dpte_row_width_luma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2997
scratch->calculate_vm_and_row_bytes_params.dpte_row_height_one_row_per_frame = &s->dpte_row_height_luma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2998
scratch->calculate_vm_and_row_bytes_params.vmpg_width = &p->vmpg_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
2999
scratch->calculate_vm_and_row_bytes_params.vmpg_height = &p->vmpg_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3000
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqWidth = &p->PixelPTEReqWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3001
scratch->calculate_vm_and_row_bytes_params.PixelPTEReqHeight = &p->PixelPTEReqHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3002
scratch->calculate_vm_and_row_bytes_params.PTERequestSize = &p->PTERequestSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3003
scratch->calculate_vm_and_row_bytes_params.dpde0_bytes_per_frame_ub = &p->dpde0_bytes_per_frame_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3005
scratch->calculate_vm_and_row_bytes_params.meta_row_bytes = &s->meta_row_bytes_per_row_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3006
scratch->calculate_vm_and_row_bytes_params.MetaRequestWidth = &p->meta_req_width_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3007
scratch->calculate_vm_and_row_bytes_params.MetaRequestHeight = &p->meta_req_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3008
scratch->calculate_vm_and_row_bytes_params.meta_row_width = &p->meta_row_width_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3009
scratch->calculate_vm_and_row_bytes_params.meta_row_height = &p->meta_row_height_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3010
scratch->calculate_vm_and_row_bytes_params.meta_pte_bytes_per_frame_ub = &p->meta_pte_bytes_per_frame_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3014
p->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3015
p->myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3016
p->myPipe[k].VTaps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3017
p->myPipe[k].InterlaceEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3018
p->myPipe[k].ProgressiveToInterlaceUnitInOPP,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3019
p->myPipe[k].SwathHeightY,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3020
p->myPipe[k].RotationAngle,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3021
p->myPipe[k].mirrored,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3022
p->myPipe[k].ViewportStationary,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3023
p->SwathWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3024
p->myPipe[k].ViewportHeight,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3025
p->myPipe[k].ViewportXStart,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3026
p->myPipe[k].ViewportYStart,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3029
&p->VInitPreFillY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3030
&p->MaxNumSwathY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3033
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_l = %u (before hvm level)\n", __func__, k, s->vm_bytes_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3034
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes_c = %u (before hvm level)\n", __func__, k, s->vm_bytes_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3035
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_l = %u\n", __func__, k, s->meta_row_bytes_per_row_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3036
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes_per_row_ub_c = %u\n", __func__, k, s->meta_row_bytes_per_row_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3038
p->vm_bytes[k] = (s->vm_bytes_l + s->vm_bytes_c) * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3039
p->meta_row_bytes[k] = s->meta_row_bytes_per_row_ub_l[k] + s->meta_row_bytes_per_row_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3040
p->meta_row_bytes_per_row_ub_l[k] = s->meta_row_bytes_per_row_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3041
p->meta_row_bytes_per_row_ub_c[k] = s->meta_row_bytes_per_row_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3044
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_bytes = %u\n", __func__, k, p->meta_row_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3045
DML_LOG_VERBOSE("DML::%s: k=%u, vm_bytes = %u (after hvm level)\n", __func__, k, p->vm_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3047
if (s->PixelPTEBytesPerRowStorageY[k] <= 64 * s->PTEBufferSizeInRequestsForLuma[k] && s->PixelPTEBytesPerRowStorageC[k] <= 64 * s->PTEBufferSizeInRequestsForChroma[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3048
p->PTEBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3050
p->PTEBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3053
s->one_row_per_frame_fits_in_buffer[k] = (s->PixelPTEBytesPerRowY_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForLuma[k] &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3054
s->PixelPTEBytesPerRowC_one_row_per_frame[k] <= 64 * 2 * s->PTEBufferSizeInRequestsForChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3056
if (p->PTEBufferSizeNotExceeded[k] == 0 || s->one_row_per_frame_fits_in_buffer[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3057
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (before hvm level)\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3058
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (before hvm level)\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3059
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageY = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3060
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowStorageC = %u\n", __func__, k, s->PixelPTEBytesPerRowStorageC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3061
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForLuma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3062
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeInRequestsForChroma = %u\n", __func__, k, s->PTEBufferSizeInRequestsForChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3063
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded (not one_row_per_frame) = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3065
DML_LOG_VERBOSE("DML::%s: k=%u, HostVMDynamicLevels = %u\n", __func__, k, s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3066
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowY_one_row_per_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3067
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC_one_row_per_frame = %u\n", __func__, k, s->PixelPTEBytesPerRowC_one_row_per_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3068
DML_LOG_VERBOSE("DML::%s: k=%u, one_row_per_frame_fits_in_buffer = %u\n", __func__, k, s->one_row_per_frame_fits_in_buffer[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3082
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3084
if (p->display_cfg->plane_descriptors[k].overrides.hw.force_pte_buffer_mode.enable == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3085
p->PTE_BUFFER_MODE[k] = p->display_cfg->plane_descriptors[k].overrides.hw.force_pte_buffer_mode.value;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3087
p->PTE_BUFFER_MODE[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->is_using_mall_for_ss[k] || (p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3088
dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) || (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes > 64);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3089
p->BIGK_FRAGMENT_SIZE[k] = (unsigned int)(math_log((float)p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes * 1024, 2) - 12);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3091
p->PTE_BUFFER_MODE[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3092
p->BIGK_FRAGMENT_SIZE[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3096
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3097
p->DCCMetaBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3099
DML_LOG_VERBOSE("DML::%s: k=%u, SurfaceSizeInMALL = %u\n", __func__, k, p->SurfaceSizeInMALL[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3100
DML_LOG_VERBOSE("DML::%s: k=%u, is_using_mall_for_ss = %u\n", __func__, k, p->is_using_mall_for_ss[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3102
p->use_one_row_for_frame[k] = p->myPipe[k].FORCE_ONE_ROW_FOR_FRAME || p->is_using_mall_for_ss[k] || (p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3103
(dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) || (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes > 64 && dml_is_vertical_rotation(p->myPipe[k].RotationAngle));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3105
p->use_one_row_for_frame_flip[k] = p->use_one_row_for_frame[k] && !(p->display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3107
if (p->use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3108
p->dpte_row_height_luma[k] = s->dpte_row_height_luma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3109
p->dpte_row_width_luma_ub[k] = s->dpte_row_width_luma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3110
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3111
p->dpte_row_height_chroma[k] = s->dpte_row_height_chroma_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3112
p->dpte_row_width_chroma_ub[k] = s->dpte_row_width_chroma_ub_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3113
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC_one_row_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3114
p->PTEBufferSizeNotExceeded[k] = s->one_row_per_frame_fits_in_buffer[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3117
if (p->meta_row_bytes[k] <= p->DCCMetaBufferSizeBytes) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3118
p->DCCMetaBufferSizeNotExceeded[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3120
p->DCCMetaBufferSizeNotExceeded[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3123
DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bytes = %d\n", __func__, k, p->meta_row_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3124
DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeBytes = %d\n", __func__, k, p->DCCMetaBufferSizeBytes);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3125
DML_LOG_VERBOSE("DML::%s: k=%d, DCCMetaBufferSizeNotExceeded = %d\n", __func__, k, p->DCCMetaBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3129
s->PixelPTEBytesPerRowY[k] = s->PixelPTEBytesPerRowY[k] * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3130
s->PixelPTEBytesPerRowC[k] = s->PixelPTEBytesPerRowC[k] * (1 + 8 * s->HostVMDynamicLevels);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3131
p->PixelPTEBytesPerRow[k] = s->PixelPTEBytesPerRowY[k] + s->PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3132
p->dpte_row_bytes_per_row_l[k] = s->PixelPTEBytesPerRowY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3133
p->dpte_row_bytes_per_row_c[k] = s->PixelPTEBytesPerRowC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3136
if (p->use_one_row_for_frame[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3137
p->PixelPTEBytesPerRow[k] = p->PixelPTEBytesPerRow[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3141
p->use_one_row_for_frame[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3142
p->myPipe[k].SourcePixelFormat,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3143
p->myPipe[k].VRatio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3144
p->myPipe[k].VRatioChroma,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3145
p->myPipe[k].DCCEnable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3146
p->myPipe[k].HTotal / p->myPipe[k].PixelClock,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3147
s->PixelPTEBytesPerRowY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3148
s->PixelPTEBytesPerRowC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3149
p->dpte_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3150
p->dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3153
p->meta_row_bytes_per_row_ub_l[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3154
p->meta_row_bytes_per_row_ub_c[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3155
p->meta_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3156
p->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3159
&p->dpte_row_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3160
&p->meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3162
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3163
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame_flip = %u\n", __func__, k, p->use_one_row_for_frame_flip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3164
DML_LOG_VERBOSE("DML::%s: k=%u, UseMALLForPStateChange = %u\n", __func__, k, p->display_cfg->plane_descriptors[k].overrides.legacy_svp_config);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3165
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_luma = %u\n", __func__, k, p->dpte_row_height_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3166
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3167
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowY = %u (after hvm level)\n", __func__, k, s->PixelPTEBytesPerRowY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3168
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_height_chroma = %u\n", __func__, k, p->dpte_row_height_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3169
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3170
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRowC = %u (after hvm level)\n", __func__, k, s->PixelPTEBytesPerRowC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3171
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEBytesPerRow = %u\n", __func__, k, p->PixelPTEBytesPerRow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3172
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, p->PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3173
DML_LOG_VERBOSE("DML::%s: k=%u, gpuvm_enable = %u\n", __func__, k, p->display_cfg->gpuvm_enable);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3174
DML_LOG_VERBOSE("DML::%s: k=%u, PTE_BUFFER_MODE = %u\n", __func__, k, p->PTE_BUFFER_MODE[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3175
DML_LOG_VERBOSE("DML::%s: k=%u, BIGK_FRAGMENT_SIZE = %u\n", __func__, k, p->BIGK_FRAGMENT_SIZE[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3518
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3519
double pixel_rate_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3521
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3522
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerSurface[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_rate_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3524
DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3526
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3529
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3530
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerSurface[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_rate_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3532
DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3536
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3537
DCFClkDeepSleepPerSurface[k] = math_max2(__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3538
__DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3540
DCFClkDeepSleepPerSurface[k] = __DML2_CALCS_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3542
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], pixel_rate_mhz / 16);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3545
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && tdlut_bytes_to_deliver[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3546
double tdlut_required_deepsleep_dcfclk = (double) tdlut_bytes_to_deliver[k] / 64.0 / prefetch_swath_time_us[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3548
DML_LOG_VERBOSE("DML::%s: k=%d, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3549
DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_bytes_to_deliver = %d\n", __func__, k, tdlut_bytes_to_deliver[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3550
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_swath_time_us = %f\n", __func__, k, prefetch_swath_time_us[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3551
DML_LOG_VERBOSE("DML::%s: k=%d, tdlut_required_deepsleep_dcfclk = %f\n", __func__, k, tdlut_required_deepsleep_dcfclk);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3554
if (tdlut_required_deepsleep_dcfclk > DCFClkDeepSleepPerSurface[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3555
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], tdlut_required_deepsleep_dcfclk);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3556
DCFClkDeepSleepPerSurface[k] = math_max2(DCFClkDeepSleepPerSurface[k], dispclk / 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3561
DML_LOG_VERBOSE("DML::%s: k=%u, PixelClock = %f\n", __func__, k, pixel_rate_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3562
DML_LOG_VERBOSE("DML::%s: k=%u, DCFClkDeepSleepPerSurface = %f\n", __func__, k, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3566
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3567
ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3579
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3580
*DCFClkDeepSleep = math_max2(*DCFClkDeepSleep, DCFClkDeepSleepPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3710
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3711
DML_LOG_VERBOSE("DML::%s: DPPPerSurface[%u] = %u\n", __func__, k, p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3741
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3742
p->full_swath_bytes_l[k] = (unsigned int)(p->swath_width_luma_ub[k] * p->BytePerPixDETY[k] * MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3743
p->full_swath_bytes_c[k] = (unsigned int)(p->swath_width_chroma_ub[k] * p->BytePerPixDETC[k] * MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3745
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface = %u\n", __func__, k, p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3746
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub = %u\n", __func__, k, p->swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3747
DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETY = %f\n", __func__, k, p->BytePerPixDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3748
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY = %u\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3749
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p->full_swath_bytes_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3750
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub = %u\n", __func__, k, p->swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3751
DML_LOG_VERBOSE("DML::%s: k=%u BytePerPixDETC = %f\n", __func__, k, p->BytePerPixDETC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3752
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC = %u\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3753
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p->full_swath_bytes_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3755
if (p->display_cfg->plane_descriptors[k].pixel_format == dml2_420_10) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3756
p->full_swath_bytes_l[k] = (unsigned int)(math_ceil2((double)p->full_swath_bytes_l[k], 256));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3757
p->full_swath_bytes_c[k] = (unsigned int)(math_ceil2((double)p->full_swath_bytes_c[k], 256));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3761
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3762
TotalActiveDPP = TotalActiveDPP + (p->ForceSingleDPP ? 1 : p->DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3763
if (p->DPPPerSurface[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3764
SurfaceDoingUnboundedRequest = k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3765
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format) || p->display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3766
|| p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3804
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3806
DETBufferSizeInKByteForSwathCalculation = (dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) ? 1024 : p->DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3808
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation = %u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3810
if (p->display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3811
p->SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3812
p->SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3813
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3814
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3816
if (p->surf_linear128_l[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3817
p->request_size_bytes_luma[k] = 128;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3819
p->request_size_bytes_luma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3821
if (p->surf_linear128_c[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3822
p->request_size_bytes_chroma[k] = 128;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3824
p->request_size_bytes_chroma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3826
} else if (p->full_swath_bytes_l[k] + p->full_swath_bytes_c[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3827
p->SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3828
p->SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3829
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3830
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3831
p->request_size_bytes_luma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3832
p->request_size_bytes_chroma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3834
} else if (p->full_swath_bytes_l[k] >= 1.5 * p->full_swath_bytes_c[k] && p->full_swath_bytes_l[k] / 2 + p->full_swath_bytes_c[k] <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3835
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3836
p->SwathHeightC[k] = MaximumSwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3837
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3838
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3839
p->request_size_bytes_luma[k] = ((p->BytePerPixY[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3840
p->request_size_bytes_chroma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3842
} else if (p->full_swath_bytes_l[k] < 1.5 * p->full_swath_bytes_c[k] && p->full_swath_bytes_l[k] + p->full_swath_bytes_c[k] / 2 <= DETBufferSizeInKByteForSwathCalculation * 1024 / 2) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3843
p->SwathHeightY[k] = MaximumSwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3844
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3845
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3846
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3847
p->request_size_bytes_luma[k] = 256;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3848
p->request_size_bytes_chroma[k] = ((p->BytePerPixC[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3851
p->SwathHeightY[k] = MaximumSwathHeightY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3852
p->SwathHeightC[k] = MaximumSwathHeightC[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3853
RoundedUpSwathSizeBytesY[k] = p->full_swath_bytes_l[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3854
RoundedUpSwathSizeBytesC[k] = p->full_swath_bytes_c[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3855
p->request_size_bytes_luma[k] = ((p->BytePerPixY[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3856
p->request_size_bytes_chroma[k] = ((p->BytePerPixC[k] == 2) == dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) ? 128 : 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3859
if (p->SwathHeightC[k] == 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3860
p->request_size_bytes_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3862
if ((p->full_swath_bytes_l[k] / 2 + p->full_swath_bytes_c[k] / 2 > DETBufferSizeInKByteForSwathCalculation * 1024 / 2) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3863
p->SwathWidth[k] > p->MaximumSwathWidthLuma[k] || (p->SwathHeightC[k] > 0 && p->SwathWidthChroma[k] > p->MaximumSwathWidthChroma[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3865
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l=%u\n", __func__, k, p->full_swath_bytes_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3866
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c=%u\n", __func__, k, p->full_swath_bytes_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3867
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByteForSwathCalculation=%u\n", __func__, k, DETBufferSizeInKByteForSwathCalculation);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3868
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidth=%u\n", __func__, k, p->SwathWidth[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3869
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, p->MaximumSwathWidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3870
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthChroma=%d\n", __func__, k, p->SwathWidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3871
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, p->MaximumSwathWidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3872
p->ViewportSizeSupportPerSurface[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3874
p->ViewportSizeSupportPerSurface[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3877
if (p->SwathHeightC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3879
DML_LOG_VERBOSE("DML::%s: k=%u, All DET will be used for plane0\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3881
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3882
p->DETBufferSizeC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3883
} else if (RoundedUpSwathSizeBytesY[k] <= 1.5 * RoundedUpSwathSizeBytesC[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3885
DML_LOG_VERBOSE("DML::%s: k=%u, Half DET will be used for plane0, and half for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3887
p->DETBufferSizeY[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3888
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3891
DML_LOG_VERBOSE("DML::%s: k=%u, 2/3 DET will be used for plane0, and 1/3 for plane1\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3893
p->DETBufferSizeY[k] = (unsigned int)(math_floor2(p->DETBufferSizeInKByte[k] * 1024 * 2 / 3, 1024));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3894
p->DETBufferSizeC[k] = p->DETBufferSizeInKByte[k] * 1024 - p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3898
DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3899
DML_LOG_VERBOSE("DML::%s: k=%u SwathHeightC = %u\n", __func__, k, p->SwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3900
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_l = %u\n", __func__, k, p->full_swath_bytes_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3901
DML_LOG_VERBOSE("DML::%s: k=%u full_swath_bytes_c = %u\n", __func__, k, p->full_swath_bytes_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3902
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesY = %u\n", __func__, k, RoundedUpSwathSizeBytesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3903
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3904
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeInKByte = %u\n", __func__, k, p->DETBufferSizeInKByte[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3905
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3906
DML_LOG_VERBOSE("DML::%s: k=%u DETBufferSizeC = %u\n", __func__, k, p->DETBufferSizeC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3907
DML_LOG_VERBOSE("DML::%s: k=%u ViewportSizeSupportPerSurface = %u\n", __func__, k, p->ViewportSizeSupportPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3930
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3932
&& p->display_cfg->plane_descriptors[k].surface.dcc.enable
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3934
+ *p->CompressedBufferSizeInkByte * MAXIMUMCOMPRESSION * 1024) > TTUFIFODEPTH * (RoundedUpSwathSizeBytesY[k] + RoundedUpSwathSizeBytesC[k])))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3937
DML_LOG_VERBOSE("DML::%s: k=%u UnboundedRequestEnabled = %u\n", __func__, k, *p->UnboundedRequestEnabled);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3938
DML_LOG_VERBOSE("DML::%s: k=%u MAXIMUMCOMPRESSION = %lu\n", __func__, k, MAXIMUMCOMPRESSION);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3939
DML_LOG_VERBOSE("DML::%s: k=%u TTUFIFODEPTH = %lu\n", __func__, k, TTUFIFODEPTH);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3940
DML_LOG_VERBOSE("DML::%s: k=%u CompressedBufferSizeInkByte = %u\n", __func__, k, *p->CompressedBufferSizeInkByte);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3941
DML_LOG_VERBOSE("DML::%s: k=%u RoundedUpSwathSizeBytesC = %u\n", __func__, k, RoundedUpSwathSizeBytesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
3942
DML_LOG_VERBOSE("DML::%s: k=%u hw_debug5 = %u\n", __func__, k, *p->hw_debug5);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
433
for (unsigned int k = 0; k < display_cfg->num_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
434
PixelClockBackEnd[k] = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
435
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && ptoi_supported == true) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4559
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4560
const struct dml2_composition_cfg *composition = &display_cfg->plane_descriptors[k].composition;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4561
const struct dml2_surface_cfg *surface = &display_cfg->plane_descriptors[k].surface;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4564
SurfaceSizeInMALL[k] = (unsigned int)(math_min2(math_ceil2((double)surface->plane0.width, ReadBlockWidthY[k]),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4565
math_floor2(composition->viewport.plane0.x_start + composition->viewport.plane0.width + ReadBlockWidthY[k] - 1, ReadBlockWidthY[k]) -
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4566
math_floor2((double)composition->viewport.plane0.x_start, ReadBlockWidthY[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4567
math_min2(math_ceil2((double)surface->plane0.height, ReadBlockHeightY[k]),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4568
math_floor2((double)composition->viewport.plane0.y_start + composition->viewport.plane0.height + ReadBlockHeightY[k] - 1, ReadBlockHeightY[k]) -
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4569
math_floor2((double)composition->viewport.plane0.y_start, ReadBlockHeightY[k])) * BytesPerPixelY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4571
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4572
SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4573
math_min2(math_ceil2((double)surface->plane1.width, ReadBlockWidthC[k]),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4574
math_floor2((double)composition->viewport.plane1.y_start + composition->viewport.plane1.width + ReadBlockWidthC[k] - 1, ReadBlockWidthC[k]) -
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4575
math_floor2((double)composition->viewport.plane1.y_start, ReadBlockWidthC[k])) *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4576
math_min2(math_ceil2((double)surface->plane1.height, ReadBlockHeightC[k]),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4577
math_floor2((double)composition->viewport.plane1.y_start + composition->viewport.plane1.height + ReadBlockHeightC[k] - 1, ReadBlockHeightC[k]) -
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4578
math_floor2(composition->viewport.plane1.y_start, ReadBlockHeightC[k])) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4581
SurfaceSizeInMALL[k] = (unsigned int)(math_ceil2(math_min2(surface->plane0.width, composition->viewport.plane0.width + ReadBlockWidthY[k] - 1), ReadBlockWidthY[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4582
math_ceil2(math_min2(surface->plane0.height, composition->viewport.plane0.height + ReadBlockHeightY[k] - 1), ReadBlockHeightY[k]) * BytesPerPixelY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4583
if (ReadBlockWidthC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4584
SurfaceSizeInMALL[k] = (unsigned int)(SurfaceSizeInMALL[k] +
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4585
math_ceil2(math_min2(surface->plane1.width, composition->viewport.plane1.width + ReadBlockWidthC[k] - 1), ReadBlockWidthC[k]) *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4586
math_ceil2(math_min2(surface->plane1.height, composition->viewport.plane1.height + ReadBlockHeightC[k] - 1), ReadBlockHeightC[k]) * BytesPerPixelC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4591
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4593
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4594
TotalSurfaceSizeInMALLForSubVP += SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4595
else if (display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4596
TotalSurfaceSizeInMALLForSS += SurfaceSizeInMALL[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4750
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4751
extra_bytes = extra_bytes + (NumberOfDPP[k] * PixelChunkSizeInKByte * 1024);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4753
if (display_cfg->plane_descriptors[k].surface.dcc.enable)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4756
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4757
extra_bytes = extra_bytes + tdlut_bytes_per_group[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4762
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4764
extra_bytes = extra_bytes + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4765
extra_bytes_prefetch = extra_bytes_prefetch + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactorPrefetch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4898
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4899
l->mall_svp_prefetch_factor = (state_type == dml2_core_internal_soc_state_svp_prefetch) ? (bw_type == dml2_core_internal_bw_dram ? mall_prefetch_dram_overhead_factor[k] : mall_prefetch_sdp_overhead_factor[k]) : 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4900
l->tmp_nom_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p0[k] : 1.0) * l->mall_svp_prefetch_factor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4901
l->tmp_nom_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_nom_overhead_factor_p1[k] : 1.0) * l->mall_svp_prefetch_factor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4902
l->tmp_pref_adj_factor_p0 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p0[k] : 1.0) * l->mall_svp_prefetch_factor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4903
l->tmp_pref_adj_factor_p1 = (bw_type == dml2_core_internal_bw_dram ? dcc_dram_bw_pref_overhead_factor_p1[k] : 1.0) * l->mall_svp_prefetch_factor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4905
l->adj_factor_p0 = UrgentBurstFactorLuma[k] * l->tmp_nom_adj_factor_p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4906
l->adj_factor_p1 = UrgentBurstFactorChroma[k] * l->tmp_nom_adj_factor_p1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4907
l->adj_factor_cur = UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4908
l->adj_factor_p0_pre = UrgentBurstFactorLumaPre[k] * l->tmp_pref_adj_factor_p0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4909
l->adj_factor_p1_pre = UrgentBurstFactorChromaPre[k] * l->tmp_pref_adj_factor_p1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4910
l->adj_factor_cur_pre = UrgentBurstFactorCursorPre[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4912
bool is_phantom = dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4923
l->per_plane_flip_bw[k] = 0; // qual_row_bw
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4924
else if (!display_cfg->plane_descriptors[k].immediate_flip)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4925
l->per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4928
if ((!display_cfg->plane_descriptors[k].immediate_flip && !display_cfg->hostvm_enable) || !inc_flip_bw)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4929
l->per_plane_flip_bw[k] = NumberOfDPP[k] * (dpte_row_bw[k] + meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4931
l->per_plane_flip_bw[k] = NumberOfDPP[k] * flip_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4935
l->vm_row_bw = NumberOfDPP[k] * prefetch_vmrow_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4936
l->flip_and_active_bw = l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4937
l->flip_and_prefetch_bw = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4938
l->flip_and_prefetch_bw_max = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthMax[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4939
l->active_and_excess_bw = (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4940
surface_required_bw[k] = math_max5(l->vm_row_bw, l->flip_and_active_bw, l->flip_and_prefetch_bw, l->active_and_excess_bw, l->flip_and_prefetch_bw_max);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4943
surface_peak_required_bw[k] = math_max2(surface_required_bw[k], surface_peak_required_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4946
DML_LOG_VERBOSE("DML::%s: k=%d, max1: vm_row_bw=%f\n", __func__, k, l->vm_row_bw);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4947
DML_LOG_VERBOSE("DML::%s: k=%d, max2: flip_and_active_bw=%f\n", __func__, k, l->flip_and_active_bw);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4948
DML_LOG_VERBOSE("DML::%s: k=%d, max3: flip_and_prefetch_bw=%f\n", __func__, k, l->flip_and_prefetch_bw);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4949
DML_LOG_VERBOSE("DML::%s: k=%d, max4: active_and_excess_bw=%f\n", __func__, k, l->active_and_excess_bw);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4950
DML_LOG_VERBOSE("DML::%s: k=%d, surface_required_bw=%f\n", __func__, k, surface_required_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4951
DML_LOG_VERBOSE("DML::%s: k=%d, surface_peak_required_bw=%f\n", __func__, k, surface_peak_required_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4954
surface_required_bw[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4957
l->required_bandwidth_mbps += surface_required_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4960
DML_LOG_VERBOSE("DML::%s: k=%d, NumberOfDPP=%d\n", __func__, k, NumberOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4961
DML_LOG_VERBOSE("DML::%s: k=%d, use_qual_row_bw=%d\n", __func__, k, use_qual_row_bw);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4962
DML_LOG_VERBOSE("DML::%s: k=%d, immediate_flip=%d\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4963
DML_LOG_VERBOSE("DML::%s: k=%d, mall_svp_prefetch_factor=%f\n", __func__, k, l->mall_svp_prefetch_factor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4964
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0=%f\n", __func__, k, l->adj_factor_p0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4965
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1=%f\n", __func__, k, l->adj_factor_p1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4966
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur=%f\n", __func__, k, l->adj_factor_cur);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4968
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p0_pre=%f\n", __func__, k, l->adj_factor_p0_pre);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4969
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_p1_pre=%f\n", __func__, k, l->adj_factor_p1_pre);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4970
DML_LOG_VERBOSE("DML::%s: k=%d, adj_factor_cur_pre=%f\n", __func__, k, l->adj_factor_cur_pre);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4972
DML_LOG_VERBOSE("DML::%s: k=%d, per_plane_flip_bw=%f\n", __func__, k, l->per_plane_flip_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4973
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_vmrow_bw=%f\n", __func__, k, prefetch_vmrow_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4974
DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthLuma=%f\n", __func__, k, ReadBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4975
DML_LOG_VERBOSE("DML::%s: k=%d, ReadBandwidthChroma=%f\n", __func__, k, ReadBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4976
DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_l=%f\n", __func__, k, excess_vactive_fill_bw_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4977
DML_LOG_VERBOSE("DML::%s: k=%d, excess_vactive_fill_bw_c=%f\n", __func__, k, excess_vactive_fill_bw_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4978
DML_LOG_VERBOSE("DML::%s: k=%d, cursor_bw=%f\n", __func__, k, cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4980
DML_LOG_VERBOSE("DML::%s: k=%d, meta_row_bw=%f\n", __func__, k, meta_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4981
DML_LOG_VERBOSE("DML::%s: k=%d, dpte_row_bw=%f\n", __func__, k, dpte_row_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4982
DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthLuma=%f\n", __func__, k, PrefetchBandwidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4983
DML_LOG_VERBOSE("DML::%s: k=%d, PrefetchBandwidthChroma=%f\n", __func__, k, PrefetchBandwidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4984
DML_LOG_VERBOSE("DML::%s: k=%d, prefetch_cursor_bw=%f\n", __func__, k, prefetch_cursor_bw[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4985
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4986
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), soc_state=%s, inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, dml2_core_internal_soc_state_type_str(state_type), inc_flip_bw, is_phantom, exclude_this_plane);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
4987
DML_LOG_VERBOSE("DML::%s: k=%d, required_bandwidth_mbps=%f (total), inc_flip_bw=%d, is_phantom=%d exclude_this_plane=%d\n", __func__, k, l->required_bandwidth_mbps, inc_flip_bw, is_phantom, exclude_this_plane);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5049
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5050
if (request_size_bytes_luma[k] > max_request_size_bytes)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5051
max_request_size_bytes = request_size_bytes_luma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5052
if (request_size_bytes_chroma[k] > max_request_size_bytes)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5053
max_request_size_bytes = request_size_bytes_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
5982
unsigned int i, k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6056
k = find_max_impact_plane(i, p->num_active_planes, s->accumulated_return_path_dcfclk_cycles); // plane k causes most impact to plane i
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6058
p->impacted_dst_y_pre[i] = s->accumulated_return_path_dcfclk_cycles[k]/p->estimated_dcfclk_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6059
p->impacted_dst_y_pre[i] += calculate_impacted_Tsw(k, p->num_active_planes, p->prefetch_sw_bytes, p->estimated_urg_bandwidth_required_mbps);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6063
DML_LOG_VERBOSE("DML::%s: i=%u impacted_Tpre=%f (k=%u)\n", __func__, i, p->impacted_dst_y_pre[i], k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6108
for (unsigned int k = 0; k < p->num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6109
l->unity_array[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6110
l->zero_array[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6725
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6726
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6762
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6763
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6764
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6765
double v_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6766
double v_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6767
s->TotalPixelBW = s->TotalPixelBW + p->DPPPerSurface[k]
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6768
* (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * v_ratio + p->SwathWidthC[k] * p->BytePerPixelDETC[k] * v_ratio_c) / (h_total / pixel_clock_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6774
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6775
double h_total = (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6776
double pixel_clock_mhz = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6777
double v_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6778
double v_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6779
double v_taps = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6780
double v_taps_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6781
double h_ratio = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6782
double h_ratio_c = p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6785
s->LBLatencyHidingSourceLinesY[k] = (unsigned int)(math_min2((double)p->MaxLineBufferLines, math_floor2((double)p->LineBufferSize / LBBitPerPixel / ((double)p->SwathWidthY[k] / math_max2(h_ratio, 1.0)), 1)) - (v_taps - 1));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6786
s->LBLatencyHidingSourceLinesC[k] = (unsigned int)(math_min2((double)p->MaxLineBufferLines, math_floor2((double)p->LineBufferSize / LBBitPerPixel / ((double)p->SwathWidthC[k] / math_max2(h_ratio_c, 1.0)), 1)) - (v_taps_c - 1));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6789
DML_LOG_VERBOSE("DML::%s: k=%u, MaxLineBufferLines = %u\n", __func__, k, p->MaxLineBufferLines);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6790
DML_LOG_VERBOSE("DML::%s: k=%u, LineBufferSize = %u\n", __func__, k, p->LineBufferSize);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6791
DML_LOG_VERBOSE("DML::%s: k=%u, LBBitPerPixel = %f\n", __func__, k, LBBitPerPixel);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6792
DML_LOG_VERBOSE("DML::%s: k=%u, HRatio = %f\n", __func__, k, h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6793
DML_LOG_VERBOSE("DML::%s: k=%u, VTaps = %f\n", __func__, k, v_taps);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6796
s->EffectiveLBLatencyHidingY = s->LBLatencyHidingSourceLinesY[k] / v_ratio * (h_total / pixel_clock_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6797
s->EffectiveLBLatencyHidingC = s->LBLatencyHidingSourceLinesC[k] / v_ratio_c * (h_total / pixel_clock_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6799
s->EffectiveDETBufferSizeY = p->DETBufferSizeY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6801
s->EffectiveDETBufferSizeY = s->EffectiveDETBufferSizeY + p->CompressedBufferSizeInkByte * 1024 * (p->SwathWidthY[k] * p->BytePerPixelDETY[k] * v_ratio) / (h_total / pixel_clock_mhz) / s->TotalPixelBW;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6804
s->LinesInDETY[k] = (double)s->EffectiveDETBufferSizeY / p->BytePerPixelDETY[k] / p->SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6805
s->LinesInDETYRoundedDownToSwath[k] = (unsigned int)(math_floor2(s->LinesInDETY[k], p->SwathHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6806
s->FullDETBufferingTimeY = s->LinesInDETYRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6808
s->ActiveClockChangeLatencyHidingY = s->EffectiveLBLatencyHidingY + s->FullDETBufferingTimeY - ((double)p->DSTXAfterScaler[k] / h_total + (double)p->DSTYAfterScaler[k]) * h_total / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6811
s->ActiveClockChangeLatencyHidingY = s->ActiveClockChangeLatencyHidingY - (1.0 - 1.0 / (double)p->NumberOfActiveSurfaces) * (double)p->SwathHeightY[k] * (double)h_total / pixel_clock_mhz / v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6814
if (p->BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6815
s->LinesInDETC[k] = p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6816
s->LinesInDETCRoundedDownToSwath[k] = (unsigned int)(math_floor2(s->LinesInDETC[k], p->SwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6817
s->FullDETBufferingTimeC = s->LinesInDETCRoundedDownToSwath[k] * (h_total / pixel_clock_mhz) / v_ratio_c;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6818
s->ActiveClockChangeLatencyHidingC = s->EffectiveLBLatencyHidingC + s->FullDETBufferingTimeC - ((double)p->DSTXAfterScaler[k] / (double)h_total + (double)p->DSTYAfterScaler[k]) * (double)h_total / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6820
s->ActiveClockChangeLatencyHidingC = s->ActiveClockChangeLatencyHidingC - (1.0 - 1.0 / (double)p->NumberOfActiveSurfaces) * (double)p->SwathHeightC[k] * (double)h_total / pixel_clock_mhz / v_ratio_c;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6827
s->ActiveDRAMClockChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->DRAMClockChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6828
s->ActiveFCLKChangeLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->FCLKChangeWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6829
s->USRRetrainingLatencyMargin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->USRRetrainingWatermark;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6830
s->g6_temp_read_latency_margin[k] = s->ActiveClockChangeLatencyHiding - p->Watermark->temp_read_or_ppt_watermark_us;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6833
p->VActiveLatencyHidingMargin[k] = s->ActiveDRAMClockChangeLatencyMargin[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6836
p->VActiveLatencyHidingUs[k] = s->ActiveClockChangeLatencyHiding;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6838
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6840
/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6841
* (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6842
/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height * (double)h_total / pixel_clock_mhz) * 4.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6843
if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6850
s->ActiveDRAMClockChangeLatencyMargin[k] = math_min2(s->ActiveDRAMClockChangeLatencyMargin[k], s->WritebackDRAMClockChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6851
s->ActiveFCLKChangeLatencyMargin[k] = math_min2(s->ActiveFCLKChangeLatencyMargin[k], s->WritebackFCLKChangeLatencyMargin);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6853
p->MaxActiveDRAMClockChangeLatencySupported[k] = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6855
uclk_pstate_change_strategy = p->display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6856
reserved_vblank_time_us = (double)p->display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns / 1000;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6858
p->FCLKChangeSupport[k] = dml2_pstate_change_unsupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6859
if (s->ActiveFCLKChangeLatencyMargin[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6860
p->FCLKChangeSupport[k] = dml2_pstate_change_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6862
p->FCLKChangeSupport[k] = dml2_pstate_change_vblank;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6864
if (p->FCLKChangeSupport[k] == dml2_pstate_change_unsupported)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6867
p->DRAMClockChangeSupport[k] = dml2_pstate_change_unsupported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6870
(s->ActiveDRAMClockChangeLatencyMargin[k] > 0 && reserved_vblank_time_us >= p->mmSOCParameters.DRAMClockChangeLatency))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6871
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank_and_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6872
else if (s->ActiveDRAMClockChangeLatencyMargin[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6873
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6875
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6876
} else if (uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_vactive && s->ActiveDRAMClockChangeLatencyMargin[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6877
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vactive;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6879
p->DRAMClockChangeSupport[k] = dml2_pstate_change_vblank;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6881
p->DRAMClockChangeSupport[k] = dml2_pstate_change_drr;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6883
p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_svp;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6885
p->DRAMClockChangeSupport[k] = dml2_pstate_change_mall_full_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6887
if (p->DRAMClockChangeSupport[k] == dml2_pstate_change_unsupported)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6891
s->src_y_pstate_l = (unsigned int)(math_ceil2(s->dst_y_pstate * v_ratio, p->SwathHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6892
s->src_y_ahead_l = (unsigned int)(math_floor2(p->DETBufferSizeY[k] / p->BytePerPixelDETY[k] / p->SwathWidthY[k], p->SwathHeightY[k]) + s->LBLatencyHidingSourceLinesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6893
s->sub_vp_lines_l = s->src_y_pstate_l + s->src_y_ahead_l + p->meta_row_height_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6896
DML_LOG_VERBOSE("DML::%s: k=%u, DETBufferSizeY = %u\n", __func__, k, p->DETBufferSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6897
DML_LOG_VERBOSE("DML::%s: k=%u, BytePerPixelDETY = %f\n", __func__, k, p->BytePerPixelDETY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6898
DML_LOG_VERBOSE("DML::%s: k=%u, SwathWidthY = %u\n", __func__, k, p->SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6899
DML_LOG_VERBOSE("DML::%s: k=%u, SwathHeightY = %u\n", __func__, k, p->SwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6900
DML_LOG_VERBOSE("DML::%s: k=%u, LBLatencyHidingSourceLinesY = %u\n", __func__, k, s->LBLatencyHidingSourceLinesY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6901
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_pstate = %u\n", __func__, k, s->dst_y_pstate);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6902
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_l = %u\n", __func__, k, s->src_y_pstate_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6903
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_l = %u\n", __func__, k, s->src_y_ahead_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6904
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_l = %u\n", __func__, k, p->meta_row_height_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6905
DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_l = %u\n", __func__, k, s->sub_vp_lines_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6907
p->SubViewportLinesNeededInMALL[k] = s->sub_vp_lines_l;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6909
if (p->BytePerPixelDETC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6910
s->src_y_pstate_c = (unsigned int)(math_ceil2(s->dst_y_pstate * v_ratio_c, p->SwathHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6911
s->src_y_ahead_c = (unsigned int)(math_floor2(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6912
s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6914
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6915
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, 2 * s->sub_vp_lines_c));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6917
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, s->sub_vp_lines_c));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6920
DML_LOG_VERBOSE("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, k, p->meta_row_height_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6921
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6922
DML_LOG_VERBOSE("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6923
DML_LOG_VERBOSE("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6929
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6930
if ((!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6931
(s->g6_temp_read_latency_margin[k] < 0)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6936
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6937
if ((!dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k])) && ((!FoundCriticalSurface)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6938
|| ((s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency) < *p->MaxActiveFCLKChangeLatencySupported))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
6940
*p->MaxActiveFCLKChangeLatencySupported = s->ActiveFCLKChangeLatencyMargin[k] + p->mmSOCParameters.FCLKChangeLatency;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7299
unsigned int k;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7315
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7316
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7321
calculate_tdlut_setting_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7322
calculate_tdlut_setting_params->tdlut_width_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_width_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7323
calculate_tdlut_setting_params->tdlut_addressing_mode = display_cfg->plane_descriptors[k].tdlut.tdlut_addressing_mode;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7326
calculate_tdlut_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7327
calculate_tdlut_setting_params->tdlut_mpc_width_flag = display_cfg->plane_descriptors[k].tdlut.tdlut_mpc_width_flag;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7328
calculate_tdlut_setting_params->is_gfx11 = dml_get_gfx_version(display_cfg->plane_descriptors[k].surface.tiling);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7331
calculate_tdlut_setting_params->tdlut_pte_bytes_per_frame = &s->tdlut_pte_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7332
calculate_tdlut_setting_params->tdlut_bytes_per_frame = &s->tdlut_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7333
calculate_tdlut_setting_params->tdlut_groups_per_2row_ub = &s->tdlut_groups_per_2row_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7334
calculate_tdlut_setting_params->tdlut_opt_time = &s->tdlut_opt_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7335
calculate_tdlut_setting_params->tdlut_drain_time = &s->tdlut_drain_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7336
calculate_tdlut_setting_params->tdlut_bytes_to_deliver = &s->tdlut_bytes_to_deliver[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7337
calculate_tdlut_setting_params->tdlut_bytes_per_group = &s->tdlut_bytes_per_group[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7380
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7381
s->impacted_dst_y_pre[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7388
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7389
s->line_times[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7390
s->pixel_format[k] = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7392
s->lb_source_lines_l[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7393
mode_lib->ms.NoOfDPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7394
display_cfg->plane_descriptors[k].composition.viewport.plane0.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7395
display_cfg->plane_descriptors[k].composition.viewport.plane0.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7396
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7397
display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7399
s->lb_source_lines_c[k] = get_num_lb_source_lines(mode_lib->ip.max_line_buffer_lines, mode_lib->ip.line_buffer_size_bits,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7400
mode_lib->ms.NoOfDPP[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7401
display_cfg->plane_descriptors[k].composition.viewport.plane1.width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7402
display_cfg->plane_descriptors[k].composition.viewport.plane1.height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7403
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7404
display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7408
mode_lib->ms.TWait[k] = CalculateTWait(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7409
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7412
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7415
myPipe->Dppclk = mode_lib->ms.RequiredDPPCLK[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7417
myPipe->PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7419
myPipe->DPPPerSurface = mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7420
myPipe->ScalerEnabled = display_cfg->plane_descriptors[k].composition.scaler_info.enabled;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7421
myPipe->VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7422
myPipe->VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7423
myPipe->VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7424
myPipe->VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7425
myPipe->RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7426
myPipe->mirrored = display_cfg->plane_descriptors[k].composition.mirrored;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7427
myPipe->BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7428
myPipe->BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7429
myPipe->BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7430
myPipe->BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7431
myPipe->InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7432
myPipe->NumberOfCursors = display_cfg->plane_descriptors[k].cursor.num_cursors;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7433
myPipe->VBlank = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7434
myPipe->HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7435
myPipe->HActive = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7436
myPipe->DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7437
myPipe->ODMMode = mode_lib->ms.ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7438
myPipe->SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7439
myPipe->BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7440
myPipe->BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7444
DML_LOG_VERBOSE("DML::%s: Calling CalculatePrefetchSchedule for k=%u\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7445
DML_LOG_VERBOSE("DML::%s: MaximumVStartup = %u\n", __func__, s->MaximumVStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7450
CalculatePrefetchSchedule_params->DSCDelay = mode_lib->ms.DSCDelay[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7456
CalculatePrefetchSchedule_params->DPP_RECOUT_WIDTH = (unsigned int)(mode_lib->ms.SwathWidthY[k] / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7457
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7459
CalculatePrefetchSchedule_params->VStartup = s->MaximumVStartup[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7461
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7463
CalculatePrefetchSchedule_params->DynamicMetadataLinesBeforeActiveRequired = display_cfg->plane_descriptors[k].dynamic_meta_data.lines_before_active_required;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7464
CalculatePrefetchSchedule_params->DynamicMetadataTransmittedBytes = display_cfg->plane_descriptors[k].dynamic_meta_data.transmitted_bytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7468
CalculatePrefetchSchedule_params->vm_bytes = mode_lib->ms.vm_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7469
CalculatePrefetchSchedule_params->PixelPTEBytesPerRow = mode_lib->ms.DPTEBytesPerRow[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7470
CalculatePrefetchSchedule_params->PrefetchSourceLinesY = mode_lib->ms.PrefetchLinesY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7471
CalculatePrefetchSchedule_params->VInitPreFillY = mode_lib->ms.PrefillY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7472
CalculatePrefetchSchedule_params->MaxNumSwathY = mode_lib->ms.MaxNumSwathY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7473
CalculatePrefetchSchedule_params->PrefetchSourceLinesC = mode_lib->ms.PrefetchLinesC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7474
CalculatePrefetchSchedule_params->VInitPreFillC = mode_lib->ms.PrefillC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7475
CalculatePrefetchSchedule_params->MaxNumSwathC = mode_lib->ms.MaxNumSwathC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7476
CalculatePrefetchSchedule_params->swath_width_luma_ub = mode_lib->ms.swath_width_luma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7477
CalculatePrefetchSchedule_params->swath_width_chroma_ub = mode_lib->ms.swath_width_chroma_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7478
CalculatePrefetchSchedule_params->SwathHeightY = mode_lib->ms.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7479
CalculatePrefetchSchedule_params->SwathHeightC = mode_lib->ms.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7480
CalculatePrefetchSchedule_params->TWait = mode_lib->ms.TWait[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7483
CalculatePrefetchSchedule_params->setup_for_tdlut = display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7484
CalculatePrefetchSchedule_params->tdlut_pte_bytes_per_frame = s->tdlut_pte_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7485
CalculatePrefetchSchedule_params->tdlut_bytes_per_frame = s->tdlut_bytes_per_frame[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7486
CalculatePrefetchSchedule_params->tdlut_opt_time = s->tdlut_opt_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7487
CalculatePrefetchSchedule_params->tdlut_drain_time = s->tdlut_drain_time[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7488
CalculatePrefetchSchedule_params->num_cursors = (display_cfg->plane_descriptors[k].cursor.cursor_width > 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7489
CalculatePrefetchSchedule_params->cursor_bytes_per_chunk = s->cursor_bytes_per_chunk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7490
CalculatePrefetchSchedule_params->cursor_bytes_per_line = s->cursor_bytes_per_line[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7491
CalculatePrefetchSchedule_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7493
CalculatePrefetchSchedule_params->meta_row_bytes = mode_lib->ms.meta_row_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7494
CalculatePrefetchSchedule_params->mall_prefetch_sdp_overhead_factor = mode_lib->ms.mall_prefetch_sdp_overhead_factor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7495
CalculatePrefetchSchedule_params->impacted_dst_y_pre = s->impacted_dst_y_pre[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7496
CalculatePrefetchSchedule_params->vactive_sw_bw_l = mode_lib->ms.vactive_sw_bw_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7497
CalculatePrefetchSchedule_params->vactive_sw_bw_c = mode_lib->ms.vactive_sw_bw_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7500
CalculatePrefetchSchedule_params->DSTXAfterScaler = &s->DSTXAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7501
CalculatePrefetchSchedule_params->DSTYAfterScaler = &s->DSTYAfterScaler[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7502
CalculatePrefetchSchedule_params->dst_y_prefetch = &mode_lib->ms.dst_y_prefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7503
CalculatePrefetchSchedule_params->dst_y_per_vm_vblank = &mode_lib->ms.LinesForVM[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7504
CalculatePrefetchSchedule_params->dst_y_per_row_vblank = &mode_lib->ms.LinesForDPTERow[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7505
CalculatePrefetchSchedule_params->VRatioPrefetchY = &mode_lib->ms.VRatioPreY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7506
CalculatePrefetchSchedule_params->VRatioPrefetchC = &mode_lib->ms.VRatioPreC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7507
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWLuma = &mode_lib->ms.RequiredPrefetchPixelDataBWLuma[k]; // prefetch_sw_bw_l
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7508
CalculatePrefetchSchedule_params->RequiredPrefetchPixelDataBWChroma = &mode_lib->ms.RequiredPrefetchPixelDataBWChroma[k]; // prefetch_sw_bw_c
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7509
CalculatePrefetchSchedule_params->RequiredPrefetchBWMax = &mode_lib->ms.RequiredPrefetchBWMax[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7510
CalculatePrefetchSchedule_params->NotEnoughTimeForDynamicMetadata = &mode_lib->ms.NoTimeForDynamicMetadata[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7511
CalculatePrefetchSchedule_params->Tno_bw = &mode_lib->ms.Tno_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7512
CalculatePrefetchSchedule_params->Tno_bw_flip = &mode_lib->ms.Tno_bw_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7513
CalculatePrefetchSchedule_params->prefetch_vmrow_bw = &mode_lib->ms.prefetch_vmrow_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7517
CalculatePrefetchSchedule_params->Tvm_trips = &s->Tvm_trips[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7518
CalculatePrefetchSchedule_params->Tr0_trips = &s->Tr0_trips[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7519
CalculatePrefetchSchedule_params->Tvm_trips_flip = &s->Tvm_trips_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7520
CalculatePrefetchSchedule_params->Tr0_trips_flip = &s->Tr0_trips_flip[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7521
CalculatePrefetchSchedule_params->Tvm_trips_flip_rounded = &s->Tvm_trips_flip_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7522
CalculatePrefetchSchedule_params->Tr0_trips_flip_rounded = &s->Tr0_trips_flip_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7526
CalculatePrefetchSchedule_params->prefetch_cursor_bw = &mode_lib->ms.prefetch_cursor_bw[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7527
CalculatePrefetchSchedule_params->prefetch_sw_bytes = &s->prefetch_sw_bytes[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7528
CalculatePrefetchSchedule_params->Tpre_rounded = &s->Tpre_rounded[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7529
CalculatePrefetchSchedule_params->Tpre_oto = &s->Tpre_oto[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7530
CalculatePrefetchSchedule_params->prefetch_swath_time_us = &s->prefetch_swath_time_us[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7532
mode_lib->ms.NoTimeForPrefetch[k] = CalculatePrefetchSchedule(&mode_lib->scratch, CalculatePrefetchSchedule_params);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7534
mode_lib->ms.support.PrefetchSupported &= !mode_lib->ms.NoTimeForPrefetch[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7535
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_vm_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params->dst_y_per_vm_vblank);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7536
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_per_row_vblank = %f\n", __func__, k, *CalculatePrefetchSchedule_params->dst_y_per_row_vblank);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7560
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7561
if (mode_lib->ms.dst_y_prefetch[k] < 2.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7562
|| mode_lib->ms.LinesForVM[k] >= 32.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7563
|| mode_lib->ms.LinesForDPTERow[k] >= 16.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7564
|| mode_lib->ms.NoTimeForPrefetch[k] == true
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7565
|| s->DSTYAfterScaler[k] > 8) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7567
DML_LOG_VERBOSE("DML::%s: k=%d, dst_y_prefetch=%f (should not be < 2)\n", __func__, k, mode_lib->ms.dst_y_prefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7568
DML_LOG_VERBOSE("DML::%s: k=%d, LinesForVM=%f (should not be >= 32)\n", __func__, k, mode_lib->ms.LinesForVM[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7569
DML_LOG_VERBOSE("DML::%s: k=%d, LinesForDPTERow=%f (should not be >= 16)\n", __func__, k, mode_lib->ms.LinesForDPTERow[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7570
DML_LOG_VERBOSE("DML::%s: k=%d, DSTYAfterScaler=%d (should be <= 8)\n", __func__, k, s->DSTYAfterScaler[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7571
DML_LOG_VERBOSE("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7576
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7577
if (mode_lib->ms.NoTimeForDynamicMetadata[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7583
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7584
if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7585
mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7587
DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreY = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7588
DML_LOG_VERBOSE("DML::%s: k=%d VRatioPreC = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7600
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7603
DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor (for prefetch)\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7604
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreY=%f\n", __func__, k, mode_lib->ms.VRatioPreY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7605
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioPreC=%f\n", __func__, k, mode_lib->ms.VRatioPreC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7608
&display_cfg->plane_descriptors[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7609
mode_lib->ms.swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7610
mode_lib->ms.swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7611
mode_lib->ms.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7612
mode_lib->ms.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7613
s->line_times[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7615
mode_lib->ms.VRatioPreY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7616
mode_lib->ms.VRatioPreC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7617
mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7618
mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7619
mode_lib->ms.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7620
mode_lib->ms.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7622
&mode_lib->ms.UrgentBurstFactorLumaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7623
&mode_lib->ms.UrgentBurstFactorChromaPre[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7624
&mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7629
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7630
mode_lib->ms.final_flip_bw[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7691
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7692
if (mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7694
DML_LOG_VERBOSE("DML::%s: k=%d, NotEnoughUrgentLatencyHidingPre=%d\n", __func__, k, mode_lib->ms.NotEnoughUrgentLatencyHidingPre[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7747
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7748
if (display_cfg->plane_descriptors[k].immediate_flip) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7749
s->per_pipe_flip_bytes[k] = get_pipe_flip_bytes(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7751
mode_lib->ms.vm_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7752
mode_lib->ms.DPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7753
mode_lib->ms.meta_row_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7755
s->per_pipe_flip_bytes[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7757
mode_lib->ms.TotImmediateFlipBytes += s->per_pipe_flip_bytes[k] * mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7761
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7764
display_cfg->plane_descriptors[k].immediate_flip,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7767
s->Tvm_trips_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7768
s->Tr0_trips_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7769
s->Tvm_trips_flip_rounded[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7770
s->Tr0_trips_flip_rounded[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7772
mode_lib->ms.vm_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7773
mode_lib->ms.DPTEBytesPerRow[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7776
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7777
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7778
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7779
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7780
mode_lib->ms.Tno_bw_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7781
mode_lib->ms.dpte_row_height[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7782
mode_lib->ms.dpte_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7783
mode_lib->ms.use_one_row_for_frame_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7786
s->per_pipe_flip_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7787
mode_lib->ms.meta_row_bytes[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7788
s->meta_row_height_luma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7789
s->meta_row_height_chroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7790
mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7793
&mode_lib->ms.dst_y_per_vm_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7794
&mode_lib->ms.dst_y_per_row_flip[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7795
&mode_lib->ms.final_flip_bw[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7796
&mode_lib->ms.ImmediateFlipSupportedForPipe[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7850
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7851
if (display_cfg->plane_descriptors[k].immediate_flip == true && mode_lib->ms.ImmediateFlipSupportedForPipe[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7941
unsigned int k, m, n;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7982
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
7983
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8007
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8008
if (display_cfg->plane_descriptors[k].composition.scaler_info.enabled == false
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8009
&& (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8010
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8011
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8012
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio != 1.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8013
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8015
} else if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps < 1.0 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps > 8.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8016
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps > 8.0
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8017
|| (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps % 2) == 1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8018
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio > mode_lib->ip.max_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8019
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio > mode_lib->ip.max_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8020
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8021
|| display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8022
|| (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8023
&& (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps < 1 || display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps > 8 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8024
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps > 8 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8025
(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps % 2 == 1) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8026
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio > mode_lib->ip.max_hscl_ratio ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8027
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio > mode_lib->ip.max_vscl_ratio ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8028
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8029
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio > display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8036
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8037
if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear && dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8042
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8044
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8045
display_cfg->plane_descriptors[k].surface.tiling,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8046
display_cfg->plane_descriptors[k].surface.plane0.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8047
display_cfg->plane_descriptors[k].surface.plane1.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8050
&mode_lib->ms.BytePerPixelY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8051
&mode_lib->ms.BytePerPixelC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8052
&mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8053
&mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8054
&mode_lib->ms.Read256BlockHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8055
&mode_lib->ms.Read256BlockHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8056
&mode_lib->ms.Read256BlockWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8057
&mode_lib->ms.Read256BlockWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8058
&mode_lib->ms.MacroTileHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8059
&mode_lib->ms.MacroTileHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8060
&mode_lib->ms.MacroTileWidthY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8061
&mode_lib->ms.MacroTileWidthC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8062
&mode_lib->ms.surf_linear128_l[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8063
&mode_lib->ms.surf_linear128_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8067
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8068
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8069
mode_lib->ms.SwathWidthYSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8070
mode_lib->ms.SwathWidthCSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8072
mode_lib->ms.SwathWidthYSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8073
mode_lib->ms.SwathWidthCSingleDPP[k] = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8077
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8078
mode_lib->ms.vactive_sw_bw_l[k] = mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8079
mode_lib->ms.vactive_sw_bw_c[k] = mode_lib->ms.SwathWidthCSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8081
mode_lib->ms.cursor_bw[k] = display_cfg->plane_descriptors[k].cursor.num_cursors * display_cfg->plane_descriptors[k].cursor.cursor_width *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8082
display_cfg->plane_descriptors[k].cursor.cursor_bpp / 8.0 / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8085
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthLuma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] * math_ceil2(mode_lib->ms.BytePerPixelInDETY[k], 1.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8086
DML_LOG_VERBOSE("DML::%s: k=%u, old_ReadBandwidthChroma = %f\n", __func__, k, mode_lib->ms.SwathWidthYSingleDPP[k] / 2 * math_ceil2(mode_lib->ms.BytePerPixelInDETC[k], 2.0) / (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio / 2.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8087
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_l = %f\n", __func__, k, mode_lib->ms.vactive_sw_bw_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8088
DML_LOG_VERBOSE("DML::%s: k=%u, vactive_sw_bw_c = %f\n", __func__, k, mode_lib->ms.vactive_sw_bw_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8093
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8094
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8095
mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8096
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8097
/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8098
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8099
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 8.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8100
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8101
mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8102
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8103
/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8104
* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8105
/ ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000)) * 4.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8107
mode_lib->ms.WriteBandwidth[k][0] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8113
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8114
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8115
(mode_lib->ms.WriteBandwidth[k][0] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib->soc.qos_parameters.writeback.base_latency_us))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8123
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8124
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8125
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > mode_lib->ip.writeback_max_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8126
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > mode_lib->ip.writeback_max_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8127
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio < mode_lib->ip.writeback_min_hscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8128
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio < mode_lib->ip.writeback_min_vscl_ratio
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8129
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > (unsigned int) mode_lib->ip.writeback_max_hscl_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8130
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps > (unsigned int) mode_lib->ip.writeback_max_vscl_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8131
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8132
|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8133
|| (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps % 2) == 1))) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8136
if (2.0 * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height * (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps - 1) * 57 > mode_lib->ip.writeback_line_buffer_buffer_size) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8142
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8144
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8145
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8146
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8147
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8150
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8151
display_cfg->plane_descriptors[k].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8152
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8153
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8154
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8155
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8157
&mode_lib->ms.PSCL_FACTOR[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8158
&mode_lib->ms.PSCL_FACTOR_CHROMA[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8159
&mode_lib->ms.MinDPPCLKUsingSingleDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8163
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8164
if (display_cfg->plane_descriptors[k].surface.tiling == dml2_sw_linear) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8166
} else if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // horz video
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8168
} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelC[k] > 0 && display_cfg->plane_descriptors[k].pixel_format != dml2_rgbe_alpha) { // vert video
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8170
} else if (display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { // rgbe + alpha
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8172
} else if (dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle) && mode_lib->ms.BytePerPixelY[k] == 8 && display_cfg->plane_descriptors[k].surface.dcc.enable == true) { // vert 64bpp
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8178
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8196
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8197
(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio, 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8198
if (mode_lib->ms.BytePerPixelC[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8201
mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8202
(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio, 1.0) - 2, 0.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8205
mode_lib->ms.MaximumSwathWidthLuma[k] = math_min2(s->MaximumSwathWidthSupportLuma, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8206
mode_lib->ms.MaximumSwathWidthChroma[k] = math_min2(s->MaximumSwathWidthSupportChroma, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8208
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthLuma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8209
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportLuma=%u\n", __func__, k, s->MaximumSwathWidthSupportLuma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8210
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferLuma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthInLineBufferLuma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8212
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthChroma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8213
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthSupportChroma=%u\n", __func__, k, s->MaximumSwathWidthSupportChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8214
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathWidthInLineBufferChroma=%f\n", __func__, k, mode_lib->ms.MaximumSwathWidthInLineBufferChroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8219
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8220
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8221
if (display_cfg->plane_descriptors[k].cursor.cursor_bpp == 64 && mode_lib->ip.cursor_64bpp_support == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8228
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8231
unsigned int alignment_l = mode_lib->ms.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8233
if (mode_lib->ms.surf_linear128_l[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8236
mode_lib->ms.support.AlignedYPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane0.pitch, display_cfg->plane_descriptors[k].surface.plane0.width), alignment_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8237
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8238
unsigned int alignment_c = mode_lib->ms.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8240
if (mode_lib->ms.surf_linear128_c[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8242
mode_lib->ms.support.AlignedCPitch[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.plane1.pitch, display_cfg->plane_descriptors[k].surface.plane1.width), alignment_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8244
mode_lib->ms.support.AlignedCPitch[k] = display_cfg->plane_descriptors[k].surface.plane1.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8247
if (mode_lib->ms.support.AlignedYPitch[k] > display_cfg->plane_descriptors[k].surface.plane0.pitch ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8248
mode_lib->ms.support.AlignedCPitch[k] > display_cfg->plane_descriptors[k].surface.plane1.pitch) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8251
DML_LOG_VERBOSE("DML::%s: k=%u AlignedYPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedYPitch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8252
DML_LOG_VERBOSE("DML::%s: k=%u PitchY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.pitch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8253
DML_LOG_VERBOSE("DML::%s: k=%u AlignedCPitch = %d\n", __func__, k, mode_lib->ms.support.AlignedCPitch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8254
DML_LOG_VERBOSE("DML::%s: k=%u PitchC = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane1.pitch);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8255
DML_LOG_VERBOSE("DML::%s: k=%u PitchSupport = %d\n", __func__, k, mode_lib->ms.support.PitchSupport);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8260
if (mode_lib->ip.dcn_mrq_present && display_cfg->plane_descriptors[k].surface.dcc.enable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8261
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8262
display_cfg->plane_descriptors[k].surface.plane0.width), 64.0 * mode_lib->ms.Read256BlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8264
if (mode_lib->ms.support.AlignedDCCMetaPitchY[k] > display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8267
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8268
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = (unsigned int)math_ceil2(math_max2(display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8269
display_cfg->plane_descriptors[k].surface.plane1.width), 64.0 * mode_lib->ms.Read256BlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8271
if (mode_lib->ms.support.AlignedDCCMetaPitchC[k] > display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8275
mode_lib->ms.support.AlignedDCCMetaPitchY[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8276
mode_lib->ms.support.AlignedDCCMetaPitchC[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8282
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8283
if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8284
display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8287
DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth = %ld\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8288
DML_LOG_VERBOSE("DML::%s: k=%u SurfaceWidthY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.width);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8289
DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight = %ld\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.height);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8290
DML_LOG_VERBOSE("DML::%s: k=%u SurfaceHeightY = %ld\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.height);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8291
DML_LOG_VERBOSE("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib->ms.support.ViewportExceedsSurface);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8294
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8295
if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8296
display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8363
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8365
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8366
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8368
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8369
mode_lib->ms.support.NumberOfDSCSlices[k] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8371
if (s->PixelClockBackEnd[k] > 4800) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8372
mode_lib->ms.support.NumberOfDSCSlices[k] = (unsigned int)(math_ceil2(s->PixelClockBackEnd[k] / 600, 4));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8373
} else if (s->PixelClockBackEnd[k] > 2400) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8374
mode_lib->ms.support.NumberOfDSCSlices[k] = 8;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8375
} else if (s->PixelClockBackEnd[k] > 1200) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8376
mode_lib->ms.support.NumberOfDSCSlices[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8377
} else if (s->PixelClockBackEnd[k] > 340) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8378
mode_lib->ms.support.NumberOfDSCSlices[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8380
mode_lib->ms.support.NumberOfDSCSlices[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8384
mode_lib->ms.support.NumberOfDSCSlices[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8389
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8390
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8391
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8392
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8397
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8398
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8408
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8409
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8410
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8411
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8416
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8417
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8431
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8432
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8433
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8434
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8435
s->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8436
s->OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8438
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8439
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_rate,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8440
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_layout,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8443
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8444
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8445
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8448
&mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8449
&mode_lib->ms.RequiresFEC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8450
&mode_lib->ms.OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8451
&mode_lib->ms.OutputType[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8452
&mode_lib->ms.OutputRate[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8453
&mode_lib->ms.RequiredSlots[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8455
if (s->OutputBpp[k] == 0.0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8456
s->OutputBpp[k] = mode_lib->ms.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8459
if (mode_lib->ms.RequiresDSC[k] == false) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8460
mode_lib->ms.ODMMode[k] = s->ODMModeNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8461
mode_lib->ms.RequiredDISPCLKPerSurface[k] = s->RequiredDISPCLKPerSurfaceNoDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8466
mode_lib->ms.ODMMode[k] = s->ODMModeDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8467
mode_lib->ms.RequiredDISPCLKPerSurface[k] = s->RequiredDISPCLKPerSurfaceDSC;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8473
DML_LOG_VERBOSE("DML::%s: k=%d RequiresDSC = %d\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8474
DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib->ms.ODMMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8479
if (mode_lib->ms.RequiresDSC[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8481
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices != 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8482
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8483
mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 2) == 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8484
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8485
mode_lib->ms.support.DSCSlicesODMModeSupported = (mode_lib->ms.support.NumberOfDSCSlices[k] == 12);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8486
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8487
mode_lib->ms.support.DSCSlicesODMModeSupported = ((mode_lib->ms.support.NumberOfDSCSlices[k] % 4) == 0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8490
DML_LOG_VERBOSE("DML::%s: k=%d Invalid dsc num_slices and ODM mode setting\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8491
DML_LOG_VERBOSE("DML::%s: k=%d num_slices = %d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.overrides.num_slices);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8492
DML_LOG_VERBOSE("DML::%s: k=%d ODMMode = %d\n", __func__, k, mode_lib->ms.ODMMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8497
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8498
mode_lib->ms.support.NumberOfDSCSlices[k] = 2 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 2.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8499
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8500
mode_lib->ms.support.NumberOfDSCSlices[k] = 12;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8501
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8502
mode_lib->ms.support.NumberOfDSCSlices[k] = 4 * (unsigned int)math_ceil2(mode_lib->ms.support.NumberOfDSCSlices[k] / 4.0, 1.0);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8506
mode_lib->ms.support.NumberOfDSCSlices[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8511
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8512
if (mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8516
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8517
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8518
mode_lib->ms.NoOfDPP[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8520
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8521
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8522
mode_lib->ms.NoOfDPP[k] = 4;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8523
} else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8524
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8525
mode_lib->ms.NoOfDPP[k] = 3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8526
} else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8527
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8528
mode_lib->ms.NoOfDPP[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8529
} else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 2) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8530
mode_lib->ms.MPCCombine[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8531
mode_lib->ms.NoOfDPP[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8533
} else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8534
mode_lib->ms.MPCCombine[k] = false;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8535
mode_lib->ms.NoOfDPP[k] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8536
if (!mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
854
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8540
if ((mode_lib->ms.MinDPPCLKUsingSingleDPP[k] > mode_lib->ms.max_dppclk_freq_mhz) || !mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8541
mode_lib->ms.MPCCombine[k] = true;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8542
mode_lib->ms.NoOfDPP[k] = 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8547
DML_LOG_VERBOSE("DML::%s: k=%d, NoOfDPP = %d\n", __func__, k, mode_lib->ms.NoOfDPP[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
855
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8556
for (k = 0; k < (unsigned int)mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8557
if (mode_lib->ms.NoOfDPP[k] == 1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
856
SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8563
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8564
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8566
CalculateWriteBackDISPCLK(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8567
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8568
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8569
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8570
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8571
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8572
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8573
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8574
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
858
SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8580
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8581
mode_lib->ms.RequiredDISPCLK = math_max2(mode_lib->ms.RequiredDISPCLK, mode_lib->ms.RequiredDISPCLKPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8585
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8586
mode_lib->ms.RequiredDPPCLK[k] = mode_lib->ms.MinDPPCLKUsingSingleDPP[k] / mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8587
mode_lib->ms.GlobalDPPCLK = math_max2(mode_lib->ms.GlobalDPPCLK, mode_lib->ms.RequiredDPPCLK[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8600
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8601
if (!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8602
if (!s->stream_visited[display_cfg->plane_descriptors[k].stream_index]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8603
s->stream_visited[display_cfg->plane_descriptors[k].stream_index] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8605
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8609
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
861
DML_LOG_VERBOSE("DML::%s: k=%u ViewportWidth=%lu\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8611
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
862
DML_LOG_VERBOSE("DML::%s: k=%u ViewportHeight=%lu\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.height);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
863
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8634
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8635
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_disabled == false &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8636
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8637
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) && mode_lib->ms.OutputBpp[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
865
MainSurfaceODMMode = ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8652
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8653
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8654
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8655
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8658
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8661
if (((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr2 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8662
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_hbr3) &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8663
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_edp) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8664
((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr10 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr13p5 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8665
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_link_rate == dml2_dp_rate_uhbr20) &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8666
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp2p0))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
868
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8681
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8682
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmi ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8683
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8692
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder != dml2_dp && (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_split_1to2 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8693
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8696
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to2 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count < 2) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8697
(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode == dml2_odm_mode_mso_1to4 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_dp_lane_count < 4))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8703
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8704
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8705
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8706
mode_lib->ms.RequiredDTBCLK[k] = RequiredDTBCLK(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8707
mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8708
s->PixelClockBackEnd[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8709
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8710
mode_lib->ms.OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8711
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8712
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8713
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8714
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_rate,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8715
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.audio_sample_layout);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8717
if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_ss_clocks_khz.dtbclk / 1000)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8726
mode_lib->ms.RequiredDTBCLK[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8731
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8732
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8733
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0 ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8734
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_edp ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8735
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8736
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8738
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_444) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8740
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8746
DML_LOG_VERBOSE("DML::%s: k=%u, RequiresDSC = %u\n", __func__, k, mode_lib->ms.RequiresDSC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8748
if (mode_lib->ms.RequiresDSC[k] == true) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8751
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8753
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8755
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8758
mode_lib->ms.required_dscclk_freq_mhz[k] = s->PixelClockBackEnd[k] / s->PixelClockBackEndFactor / (double)s->DSCFormatFactor;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8759
if (mode_lib->ms.required_dscclk_freq_mhz[k] > mode_lib->ms.max_dscclk_freq_mhz) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8764
DML_LOG_VERBOSE("DML::%s: k=%u, PixelClockBackEnd = %f\n", __func__, k, s->PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8765
DML_LOG_VERBOSE("DML::%s: k=%u, required_dscclk_freq_mhz = %f\n", __func__, k, mode_lib->ms.required_dscclk_freq_mhz[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8766
DML_LOG_VERBOSE("DML::%s: k=%u, DSCFormatFactor = %u\n", __func__, k, s->DSCFormatFactor);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8767
DML_LOG_VERBOSE("DML::%s: k=%u, DSCCLKRequiredMoreThanSupported = %u\n", __func__, k, mode_lib->ms.support.DSCCLKRequiredMoreThanSupported);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8779
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
878
SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio)));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8780
if (mode_lib->ms.RequiresDSC[k] == true && !s->stream_visited[display_cfg->plane_descriptors[k].stream_index]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8783
if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8785
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8787
else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
879
} else if (DPPPerSurface[k] == 2) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8790
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active > s->NumDSCUnitRequired * (unsigned int)mode_lib->ip.maximum_pixels_per_line_per_dsc_unit)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8794
if (mode_lib->ms.support.NumberOfDSCSlices[k] > 4 * s->NumDSCUnitRequired)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8797
s->stream_visited[display_cfg->plane_descriptors[k].stream_index] = 1;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
880
SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8806
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8807
mode_lib->ms.DSCDelay[k] = DSCDelayRequirement(mode_lib->ms.RequiresDSC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8808
mode_lib->ms.ODMMode[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8810
s->OutputBpp[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8811
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8812
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8813
mode_lib->ms.support.NumberOfDSCSlices[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8814
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8815
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8816
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000),
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8817
s->PixelClockBackEnd[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
882
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8849
for (k = 0; k < mode_lib->ms.num_active_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8850
mode_lib->ms.SurfaceSizeInMALL[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
886
DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
887
DML_LOG_VERBOSE("DML::%s: k=%u HRatio=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8875
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8876
if (display_cfg->plane_descriptors[k].surface.dcc.enable == true) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8877
mode_lib->ms.TotalNumberOfDCCActiveDPP = mode_lib->ms.TotalNumberOfDCCActiveDPP + mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
888
DML_LOG_VERBOSE("DML::%s: k=%u MainSurfaceODMMode=%u\n", __func__, k, MainSurfaceODMMode);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8881
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8882
s->SurfParameters[k].PixelClock = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8883
s->SurfParameters[k].DPPPerSurface = mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8884
s->SurfParameters[k].RotationAngle = display_cfg->plane_descriptors[k].composition.rotation_angle;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8885
s->SurfParameters[k].ViewportHeight = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8886
s->SurfParameters[k].ViewportHeightC = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8887
s->SurfParameters[k].BlockWidth256BytesY = mode_lib->ms.Read256BlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8888
s->SurfParameters[k].BlockHeight256BytesY = mode_lib->ms.Read256BlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8889
s->SurfParameters[k].BlockWidth256BytesC = mode_lib->ms.Read256BlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
889
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthSingleDPPY=%u\n", __func__, k, SwathWidthSingleDPPY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8890
s->SurfParameters[k].BlockHeight256BytesC = mode_lib->ms.Read256BlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8891
s->SurfParameters[k].BlockWidthY = mode_lib->ms.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8892
s->SurfParameters[k].BlockHeightY = mode_lib->ms.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8893
s->SurfParameters[k].BlockWidthC = mode_lib->ms.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8894
s->SurfParameters[k].BlockHeightC = mode_lib->ms.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8895
s->SurfParameters[k].InterlaceEnable = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8896
s->SurfParameters[k].HTotal = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8897
s->SurfParameters[k].DCCEnable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8898
s->SurfParameters[k].SourcePixelFormat = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8899
s->SurfParameters[k].SurfaceTiling = display_cfg->plane_descriptors[k].surface.tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
890
DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8900
s->SurfParameters[k].BytePerPixelY = mode_lib->ms.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8901
s->SurfParameters[k].BytePerPixelC = mode_lib->ms.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8902
s->SurfParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->ip.ptoi_supported;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8903
s->SurfParameters[k].VRatio = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8904
s->SurfParameters[k].VRatioChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8905
s->SurfParameters[k].VTaps = display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8906
s->SurfParameters[k].VTapsChroma = display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8907
s->SurfParameters[k].PitchY = display_cfg->plane_descriptors[k].surface.plane0.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8908
s->SurfParameters[k].PitchC = display_cfg->plane_descriptors[k].surface.plane1.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8909
s->SurfParameters[k].ViewportStationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8910
s->SurfParameters[k].ViewportXStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8911
s->SurfParameters[k].ViewportYStart = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8912
s->SurfParameters[k].ViewportXStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8913
s->SurfParameters[k].ViewportYStartC = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8914
s->SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = display_cfg->plane_descriptors[k].overrides.hw.force_one_row_for_frame;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8915
s->SurfParameters[k].SwathHeightY = mode_lib->ms.SwathHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8916
s->SurfParameters[k].SwathHeightC = mode_lib->ms.SwathHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8918
s->SurfParameters[k].DCCMetaPitchY = display_cfg->plane_descriptors[k].surface.dcc.plane0.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8919
s->SurfParameters[k].DCCMetaPitchC = display_cfg->plane_descriptors[k].surface.dcc.plane1.pitch;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
892
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
893
SwathWidthC[k] = SwathWidthY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
894
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
896
SwathWidthC[k] = SwathWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
897
SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8994
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8995
if (mode_lib->ms.PTEBufferSizeNotExceeded[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
8998
if (mode_lib->ms.DCCMetaBufferSizeNotExceeded[k] == false)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9002
DML_LOG_VERBOSE("DML::%s: k=%u, PTEBufferSizeNotExceeded = %u\n", __func__, k, mode_lib->ms.PTEBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9003
DML_LOG_VERBOSE("DML::%s: k=%u, DCCMetaBufferSizeNotExceeded = %u\n", __func__, k, mode_lib->ms.DCCMetaBufferSizeNotExceeded[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
901
SwathWidthY[k] = SwathWidthSingleDPPY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
902
SwathWidthC[k] = SwathWidthSingleDPPC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
905
req_width_horz_y = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
906
req_width_horz_c = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9079
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
908
if (surf_linear128_l[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9080
double line_time_us = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total / ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9083
if (display_cfg->plane_descriptors[k].cursor.num_cursors > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9085
display_cfg->plane_descriptors[k].cursor.cursor_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9086
display_cfg->plane_descriptors[k].cursor.cursor_bpp,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9089
&s->cursor_lines_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9090
&s->cursor_bytes_per_line[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9091
&s->cursor_bytes_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9092
&s->cursor_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9096
display_cfg->plane_descriptors[k].cursor.cursor_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9097
s->cursor_bytes_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9098
s->cursor_lines_per_chunk[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9103
&mode_lib->ms.UrgentBurstFactorCursor[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9107
mode_lib->ms.UrgentBurstFactorCursorPre[k] = mode_lib->ms.UrgentBurstFactorCursor[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
911
if (surf_linear128_c[k])
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9110
DML_LOG_VERBOSE("DML::%s: k=%d, Calling CalculateUrgentBurstFactor\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9111
DML_LOG_VERBOSE("DML::%s: k=%d, VRatio=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9112
DML_LOG_VERBOSE("DML::%s: k=%d, VRatioChroma=%f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9116
&display_cfg->plane_descriptors[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9117
mode_lib->ms.swath_width_luma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9118
mode_lib->ms.swath_width_chroma_ub[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9119
mode_lib->ms.SwathHeightY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9120
mode_lib->ms.SwathHeightC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9123
display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9124
display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9125
mode_lib->ms.BytePerPixelInDETY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9126
mode_lib->ms.BytePerPixelInDETC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9127
mode_lib->ms.DETBufferSizeY[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9128
mode_lib->ms.DETBufferSizeC[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9131
&mode_lib->ms.UrgentBurstFactorLuma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9132
&mode_lib->ms.UrgentBurstFactorChroma[k],
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9133
&mode_lib->ms.NotEnoughUrgentLatencyHiding[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9135
mode_lib->ms.NotEnoughUrgentLatencyHiding[k] = mode_lib->ms.NotEnoughUrgentLatencyHiding[k] || cursor_not_enough_urgent_latency_hiding;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
914
surface_width_ub_l = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane0.width, req_width_horz_y);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
915
surface_height_ub_l = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane0.height, Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9156
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9157
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9158
mode_lib->ms.WritebackDelayTime[k] = mode_lib->soc.qos_parameters.writeback.base_latency_us + CalculateWriteBackDelay(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9159
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
916
surface_width_ub_c = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane1.width, req_width_horz_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9160
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9161
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9162
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9163
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9164
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9165
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9166
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total) / mode_lib->ms.RequiredDISPCLK;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9168
mode_lib->ms.WritebackDelayTime[k] = 0.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
917
surface_height_ub_c = (unsigned int)math_ceil2((double)display_cfg->plane_descriptors[k].surface.plane1.height, Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9173
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9174
bool isInterlaceTiming = (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced && !mode_lib->ip.ptoi_supported);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9175
s->MaximumVStartup[k] = CalculateMaxVStartup(
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9178
&display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing,
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9179
mode_lib->ms.WritebackDelayTime[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9180
mode_lib->ms.MaxVStartupLines[k] = (isInterlaceTiming ? (2 * s->MaximumVStartup[k]) : s->MaximumVStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9184
DML_LOG_VERBOSE("DML::%s: k=%u, MaximumVStartup = %u\n", __func__, k, s->MaximumVStartup[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9189
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
919
DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_l=%u\n", __func__, k, surface_width_ub_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9190
s->ImmediateFlipRequired = s->ImmediateFlipRequired || display_cfg->plane_descriptors[k].immediate_flip;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9194
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9197
((display_cfg->hostvm_enable == true || display_cfg->plane_descriptors[k].immediate_flip == true) &&
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9198
(display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame || dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
920
DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_l=%u\n", __func__, k, surface_height_ub_l);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9202
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9204
((display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_enable || display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) && (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))) ||
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9205
((display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_force_disable || display_cfg->plane_descriptors[k].overrides.refresh_from_mall == dml2_refresh_from_mall_mode_override_auto) && (display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
921
DML_LOG_VERBOSE("DML::%s: k=%u surface_width_ub_c=%u\n", __func__, k, surface_width_ub_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9212
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9213
if (display_cfg->plane_descriptors[k].overrides.uclk_pstate_change_strategy == dml2_uclk_pstate_change_strategy_force_mall_full_frame)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9215
if (display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_main_pipe) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9219
unsigned long long refresh_rate = (unsigned long long) ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz * 1000 /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
922
DML_LOG_VERBOSE("DML::%s: k=%u surface_height_ub_c=%u\n", __func__, k, surface_height_ub_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9220
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9221
(double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.v_total);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9226
if (dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
923
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
924
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
925
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthY=%u\n", __func__, k, Read256BytesBlockWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
926
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightY=%u\n", __func__, k, Read256BytesBlockHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9266
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9269
outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_luma[k]
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
927
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockWidthC=%u\n", __func__, k, Read256BytesBlockWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
928
DML_LOG_VERBOSE("DML::%s: k=%u Read256BytesBlockHeightC=%u\n", __func__, k, Read256BytesBlockHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9283
DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_luma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9284
DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (luma)\n", __func__, k, outstanding_latency_us);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9288
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x && mode_lib->ms.BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9289
outstanding_latency_us = (mode_lib->soc.max_outstanding_reqs * mode_lib->ms.support.request_size_bytes_chroma[k]
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
929
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_y=%u\n", __func__, k, req_width_horz_y);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
930
DML_LOG_VERBOSE("DML::%s: k=%u req_width_horz_c=%u\n", __func__, k, req_width_horz_c);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9300
DML_LOG_VERBOSE("DML::%s: k=%d, request_size_bytes_chroma = %d\n", __func__, k, mode_lib->ms.support.request_size_bytes_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9301
DML_LOG_VERBOSE("DML::%s: k=%d, outstanding_latency_us = %f (chroma)\n", __func__, k, outstanding_latency_us);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9308
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9309
mode_lib->ms.mall_prefetch_sdp_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
931
DML_LOG_VERBOSE("DML::%s: k=%u ViewportStationary=%u\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.stationary);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9310
mode_lib->ms.mall_prefetch_dram_overhead_factor[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9311
mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9312
mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p0[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9313
mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9314
mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p1[k] = 1.0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9317
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9318
calculate_mcache_setting_params->dcc_enable = display_cfg->plane_descriptors[k].surface.dcc.enable;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
932
DML_LOG_VERBOSE("DML::%s: k=%u DPPPerSurface=%u\n", __func__, k, DPPPerSurface[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9324
calculate_mcache_setting_params->gpuvm_page_size_kbytes = display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9326
calculate_mcache_setting_params->source_format = display_cfg->plane_descriptors[k].pixel_format;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9327
calculate_mcache_setting_params->surf_vert = dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9328
calculate_mcache_setting_params->vp_stationary = display_cfg->plane_descriptors[k].composition.viewport.stationary;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9329
calculate_mcache_setting_params->tiling_mode = display_cfg->plane_descriptors[k].surface.tiling;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9330
calculate_mcache_setting_params->imall_enable = mode_lib->ip.imall_supported && display_cfg->plane_descriptors[k].overrides.legacy_svp_config == dml2_svp_mode_override_imall;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9332
calculate_mcache_setting_params->vp_start_x_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9333
calculate_mcache_setting_params->vp_start_y_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9334
calculate_mcache_setting_params->full_vp_width_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9335
calculate_mcache_setting_params->full_vp_height_l = display_cfg->plane_descriptors[k].composition.viewport.plane0.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9336
calculate_mcache_setting_params->blk_width_l = mode_lib->ms.MacroTileWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9337
calculate_mcache_setting_params->blk_height_l = mode_lib->ms.MacroTileHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9338
calculate_mcache_setting_params->vmpg_width_l = s->vmpg_width_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9339
calculate_mcache_setting_params->vmpg_height_l = s->vmpg_height_y[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
934
req_per_swath_ub_l[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9340
calculate_mcache_setting_params->full_swath_bytes_l = s->full_swath_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9341
calculate_mcache_setting_params->bytes_per_pixel_l = mode_lib->ms.BytePerPixelY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9343
calculate_mcache_setting_params->vp_start_x_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.x_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9344
calculate_mcache_setting_params->vp_start_y_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9345
calculate_mcache_setting_params->full_vp_width_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9346
calculate_mcache_setting_params->full_vp_height_c = display_cfg->plane_descriptors[k].composition.viewport.plane1.height;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9347
calculate_mcache_setting_params->blk_width_c = mode_lib->ms.MacroTileWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9348
calculate_mcache_setting_params->blk_height_c = mode_lib->ms.MacroTileHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9349
calculate_mcache_setting_params->vmpg_width_c = s->vmpg_width_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
935
req_per_swath_ub_c[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9350
calculate_mcache_setting_params->vmpg_height_c = s->vmpg_height_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9351
calculate_mcache_setting_params->full_swath_bytes_c = s->full_swath_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9352
calculate_mcache_setting_params->bytes_per_pixel_c = mode_lib->ms.BytePerPixelC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9355
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_l = &mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9356
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_l = &mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p0[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9357
calculate_mcache_setting_params->dcc_dram_bw_nom_overhead_factor_c = &mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9358
calculate_mcache_setting_params->dcc_dram_bw_pref_overhead_factor_c = &mode_lib->ms.dcc_dram_bw_pref_overhead_factor_p1[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
936
if (!dml_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9360
calculate_mcache_setting_params->num_mcaches_l = &mode_lib->ms.num_mcaches_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9361
calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->ms.mcache_row_bytes_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9362
calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->ms.mcache_row_bytes_per_channel_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9363
calculate_mcache_setting_params->mcache_offsets_l = mode_lib->ms.mcache_offsets_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9364
calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->ms.mcache_shift_granularity_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9366
calculate_mcache_setting_params->num_mcaches_c = &mode_lib->ms.num_mcaches_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9367
calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->ms.mcache_row_bytes_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9368
calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->ms.mcache_row_bytes_per_channel_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9369
calculate_mcache_setting_params->mcache_offsets_c = mode_lib->ms.mcache_offsets_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
937
MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9370
calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->ms.mcache_shift_granularity_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9372
calculate_mcache_setting_params->mall_comb_mcache_l = &mode_lib->ms.mall_comb_mcache_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9373
calculate_mcache_setting_params->mall_comb_mcache_c = &mode_lib->ms.mall_comb_mcache_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9374
calculate_mcache_setting_params->lc_comb_mcache = &mode_lib->ms.lc_comb_mcache[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
938
MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
939
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
940
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start + SwathWidthY[k] + req_width_horz_y - 1, req_width_horz_y) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.x_start, req_width_horz_y)));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
942
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_width_ub_l, math_ceil2((double)SwathWidthY[k] - 1, req_width_horz_y) + req_width_horz_y));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
944
req_per_swath_ub_l[k] = swath_width_luma_ub[k] / req_width_horz_y;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9444
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9445
if (mode_lib->ms.NotEnoughUrgentLatencyHiding[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9447
DML_LOG_VERBOSE("DML::%s: k=%u NotEnoughUrgentLatencyHiding set\n", __func__, k);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
946
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
947
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
948
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + req_width_horz_c - 1, req_width_horz_c) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start, req_width_horz_c)));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
950
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_width_ub_c, math_ceil2((double)SwathWidthC[k] - 1, req_width_horz_c) + req_width_horz_c));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
952
req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / req_width_horz_c;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
954
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9561
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9562
mode_lib->ms.support.MPCCombineEnable[k] = mode_lib->ms.MPCCombine[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9563
mode_lib->ms.support.DPPPerSurface[k] = mode_lib->ms.NoOfDPP[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9566
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9567
mode_lib->ms.support.ODMMode[k] = mode_lib->ms.ODMMode[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9568
mode_lib->ms.support.DSCEnabled[k] = mode_lib->ms.RequiresDSC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9569
mode_lib->ms.support.FECEnabled[k] = mode_lib->ms.RequiresFEC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
957
MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9570
mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9571
mode_lib->ms.support.OutputType[k] = mode_lib->ms.OutputType[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9572
mode_lib->ms.support.OutputRate[k] = mode_lib->ms.OutputRate[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9575
DML_LOG_VERBOSE("DML::%s: k=%d, ODMMode = %u\n", __func__, k, mode_lib->ms.support.ODMMode[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9576
DML_LOG_VERBOSE("DML::%s: k=%d, DSCEnabled = %u\n", __func__, k, mode_lib->ms.support.DSCEnabled[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
958
MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
960
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9602
for (unsigned int k = 0; k < in_out_params->in_display_cfg->num_planes; k++)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9603
DML_LOG_VERBOSE("DML::%s: plane_%d: reserved_vblank_time_ns = %lu\n", __func__, k, in_out_params->in_display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
961
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start + SwathWidthY[k] + Read256BytesBlockHeightY[k] - 1, Read256BytesBlockHeightY[k]) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane0.y_start, Read256BytesBlockHeightY[k])));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
963
swath_width_luma_ub[k] = (unsigned int)(math_min2(surface_height_ub_l, math_ceil2((double)SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9635
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9636
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9639
DML_LOG_VERBOSE("DML::%s: k=%u : HRatio = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9640
DML_LOG_VERBOSE("DML::%s: k=%u : VRatio = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9641
DML_LOG_VERBOSE("DML::%s: k=%u : HRatioChroma = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9642
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioChroma = %f\n", __func__, k, display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9643
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchY = %f\n", __func__, k, VRatioPrefetchY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9644
DML_LOG_VERBOSE("DML::%s: k=%u : VRatioPrefetchC = %f\n", __func__, k, VRatioPrefetchC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9645
DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_luma_ub = %u\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9646
DML_LOG_VERBOSE("DML::%s: k=%u : swath_width_chroma_ub = %u\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9647
DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT = %f\n", __func__, k, PSCL_THROUGHPUT[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9648
DML_LOG_VERBOSE("DML::%s: k=%u : PSCL_THROUGHPUT_CHROMA = %f\n", __func__, k, PSCL_THROUGHPUT_CHROMA[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9649
DML_LOG_VERBOSE("DML::%s: k=%u : DPPPerSurface = %u\n", __func__, k, cfg_support_info->plane_support_info[k].dpps_used);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
965
req_per_swath_ub_l[k] = swath_width_luma_ub[k] / Read256BytesBlockHeightY[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9650
DML_LOG_VERBOSE("DML::%s: k=%u : pixel_clock_mhz = %f\n", __func__, k, pixel_clock_mhz);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9651
DML_LOG_VERBOSE("DML::%s: k=%u : Dppclk = %f\n", __func__, k, Dppclk[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9653
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9654
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9656
DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9659
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
966
if (BytePerPixC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9660
DisplayPipeLineDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9662
if (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9663
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9665
DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9669
if (VRatioPrefetchY[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
967
if (display_cfg->plane_descriptors[k].composition.viewport.stationary && DPPPerSurface[k] == 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9670
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9672
DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9675
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9676
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9678
if (VRatioPrefetchC[k] <= 1) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9679
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * cfg_support_info->plane_support_info[k].dpps_used / display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio / pixel_clock_mhz;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
968
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start + SwathWidthC[k] + Read256BytesBlockHeightC[k] - 1, Read256BytesBlockHeightC[k]) - math_floor2(display_cfg->plane_descriptors[k].composition.viewport.plane1.y_start, Read256BytesBlockHeightC[k])));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9681
DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / Dppclk[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9685
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9686
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9687
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9688
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9692
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9694
DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9695
DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub_l[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9696
if (BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9697
DisplayPipeRequestDeliveryTimeChroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9698
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
970
swath_width_chroma_ub[k] = (unsigned int)(math_min2(surface_height_ub_c, math_ceil2((double)SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9700
DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9701
DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9704
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9705
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9706
DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_l = %d\n", __func__, k, req_per_swath_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9707
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9708
DML_LOG_VERBOSE("DML::%s: k=%u : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9709
DML_LOG_VERBOSE("DML::%s: k=%u : req_per_swath_ub_c = %d\n", __func__, k, req_per_swath_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
972
req_per_swath_ub_c[k] = swath_width_chroma_ub[k] / Read256BytesBlockHeightC[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9734
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9735
p->DST_Y_PER_PTE_ROW_NOM_L[k] = p->dpte_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9736
if (p->BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9737
p->DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9739
p->DST_Y_PER_PTE_ROW_NOM_C[k] = p->dpte_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
974
swath_width_chroma_ub[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9741
p->DST_Y_PER_META_ROW_NOM_L[k] = p->meta_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9742
if (p->BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9743
p->DST_Y_PER_META_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9745
p->DST_Y_PER_META_ROW_NOM_C[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9749
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9750
if (p->display_cfg->plane_descriptors[k].surface.dcc.enable == true && p->mrq_present) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9751
meta_chunk_width = p->MetaChunkSize * 1024 * 256 / p->BytePerPixelY[k] / p->meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9752
min_meta_chunk_width = p->MinMetaChunkSizeBytes * 256 / p->BytePerPixelY[k] / p->meta_row_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9753
meta_chunk_per_row_int = p->meta_row_width[k] / meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9754
meta_row_remainder = p->meta_row_width[k] % meta_chunk_width;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9755
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9756
meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9758
meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_height[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9765
p->TimePerMetaChunkNominal[k] = p->meta_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio *
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9766
p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9767
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9768
p->TimePerMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9769
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9770
p->TimePerMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total /
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9771
(p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9772
if (p->BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9773
p->TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9774
p->TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9775
p->TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9777
meta_chunk_width_chroma = p->MetaChunkSize * 1024 * 256 / p->BytePerPixelC[k] / p->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9778
min_meta_chunk_width_chroma = p->MinMetaChunkSizeBytes * 256 / p->BytePerPixelC[k] / p->meta_row_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9779
meta_chunk_per_row_int_chroma = (unsigned int)((double)p->meta_row_width_chroma[k] / meta_chunk_width_chroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
978
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_luma_ub=%u\n", __func__, k, swath_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9780
meta_row_remainder_chroma = p->meta_row_width_chroma[k] % meta_chunk_width_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9781
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9782
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p->meta_req_width_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9784
meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - p->meta_req_height_chroma[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
979
DML_LOG_VERBOSE("DML::%s: k=%u swath_width_chroma_ub=%u\n", __func__, k, swath_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9791
p->TimePerChromaMetaChunkNominal[k] = p->meta_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9792
p->TimePerChromaMetaChunkVBlank[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9793
p->TimePerChromaMetaChunkFlip[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000) / meta_chunks_per_row_ub_chroma;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9796
p->TimePerMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9797
p->TimePerMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9798
p->TimePerMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9799
p->TimePerChromaMetaChunkNominal[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
980
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightY=%u\n", __func__, k, MaximumSwathHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9800
p->TimePerChromaMetaChunkVBlank[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9801
p->TimePerChromaMetaChunkFlip[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9805
DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_L = %f\n", __func__, k, p->DST_Y_PER_META_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9806
DML_LOG_VERBOSE("DML::%s: k=%d, DST_Y_PER_META_ROW_NOM_C = %f\n", __func__, k, p->DST_Y_PER_META_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9807
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkNominal = %f\n", __func__, k, p->TimePerMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9808
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkVBlank = %f\n", __func__, k, p->TimePerMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9809
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerMetaChunkFlip = %f\n", __func__, k, p->TimePerMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
981
DML_LOG_VERBOSE("DML::%s: k=%u MaximumSwathHeightC=%u\n", __func__, k, MaximumSwathHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9810
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkNominal = %f\n", __func__, k, p->TimePerChromaMetaChunkNominal[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9811
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkVBlank = %f\n", __func__, k, p->TimePerChromaMetaChunkVBlank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9812
DML_LOG_VERBOSE("DML::%s: k=%d, TimePerChromaMetaChunkFlip = %f\n", __func__, k, p->TimePerChromaMetaChunkFlip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9816
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9817
p->DST_Y_PER_PTE_ROW_NOM_L[k] = p->dpte_row_height[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9818
if (p->BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9819
p->DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
982
DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_l=%u\n", __func__, k, req_per_swath_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9821
p->DST_Y_PER_PTE_ROW_NOM_C[k] = p->dpte_row_height_chroma[k] / p->display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9825
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9826
pixel_clock_mhz = ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9828
if (p->display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9829
p->time_per_tdlut_group[k] = 2 * p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / p->tdlut_groups_per_2row_ub[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
983
DML_LOG_VERBOSE("DML::%s: k=%u req_per_swath_ub_c=%u\n", __func__, k, req_per_swath_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9831
p->time_per_tdlut_group[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9833
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_tdlut_group = %f\n", __func__, k, p->time_per_tdlut_group[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9836
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9837
dpte_group_width_luma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeY[k] * p->PixelPTEReqWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9839
dpte_group_width_luma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeY[k] * p->PixelPTEReqHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9841
if (p->use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9842
dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma / 2.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9844
dpte_groups_per_row_luma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_luma_ub[k] / (double)dpte_group_width_luma, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9849
DML_LOG_VERBOSE("DML::%s: k=%u, use_one_row_for_frame = %u\n", __func__, k, p->use_one_row_for_frame[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9850
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_bytes = %u\n", __func__, k, p->dpte_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9851
DML_LOG_VERBOSE("DML::%s: k=%u, PTERequestSizeY = %u\n", __func__, k, p->PTERequestSizeY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9852
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqWidthY = %u\n", __func__, k, p->PixelPTEReqWidthY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9853
DML_LOG_VERBOSE("DML::%s: k=%u, PixelPTEReqHeightY = %u\n", __func__, k, p->PixelPTEReqHeightY[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9854
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_luma_ub = %u\n", __func__, k, p->dpte_row_width_luma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9855
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_luma = %u\n", __func__, k, dpte_group_width_luma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9856
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_luma_ub = %u\n", __func__, k, dpte_groups_per_row_luma_ub);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9858
p->time_per_pte_group_nom_luma[k] = p->DST_Y_PER_PTE_ROW_NOM_L[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9859
p->time_per_pte_group_vblank_luma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9860
p->time_per_pte_group_flip_luma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_luma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9861
if (p->BytePerPixelC[k] == 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9862
p->time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9863
p->time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9864
p->time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9866
if (!dml_is_vertical_rotation(p->display_cfg->plane_descriptors[k].composition.rotation_angle)) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9867
dpte_group_width_chroma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeC[k] * p->PixelPTEReqWidthC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9869
dpte_group_width_chroma = (unsigned int)((double)p->dpte_group_bytes[k] / (double)p->PTERequestSizeC[k] * p->PixelPTEReqHeightC[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9872
if (p->use_one_row_for_frame[k]) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9873
dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma / 2.0, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9875
dpte_groups_per_row_chroma_ub = (unsigned int)(math_ceil2((double)p->dpte_row_width_chroma_ub[k] / (double)dpte_group_width_chroma, 1.0));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9880
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_row_width_chroma_ub = %u\n", __func__, k, p->dpte_row_width_chroma_ub[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9881
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_group_width_chroma = %u\n", __func__, k, dpte_group_width_chroma);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9882
DML_LOG_VERBOSE("DML::%s: k=%u, dpte_groups_per_row_chroma_ub = %u\n", __func__, k, dpte_groups_per_row_chroma_ub);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9884
p->time_per_pte_group_nom_chroma[k] = p->DST_Y_PER_PTE_ROW_NOM_C[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9885
p->time_per_pte_group_vblank_chroma[k] = p->dst_y_per_row_vblank[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9886
p->time_per_pte_group_flip_chroma[k] = p->dst_y_per_row_flip[k] * p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].timing.h_total / pixel_clock_mhz / dpte_groups_per_row_chroma_ub;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9889
p->time_per_pte_group_nom_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9890
p->time_per_pte_group_vblank_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9891
p->time_per_pte_group_flip_luma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9892
p->time_per_pte_group_nom_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9893
p->time_per_pte_group_vblank_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9894
p->time_per_pte_group_flip_chroma[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9897
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_vblank = %f\n", __func__, k, p->dst_y_per_row_vblank[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9898
DML_LOG_VERBOSE("DML::%s: k=%u, dst_y_per_row_flip = %f\n", __func__, k, p->dst_y_per_row_flip[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9900
DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_L = %f\n", __func__, k, p->DST_Y_PER_PTE_ROW_NOM_L[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9901
DML_LOG_VERBOSE("DML::%s: k=%u, DST_Y_PER_PTE_ROW_NOM_C = %f\n", __func__, k, p->DST_Y_PER_PTE_ROW_NOM_C[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9902
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_luma = %f\n", __func__, k, p->time_per_pte_group_nom_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9903
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_luma = %f\n", __func__, k, p->time_per_pte_group_vblank_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9904
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_luma = %f\n", __func__, k, p->time_per_pte_group_flip_luma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9905
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_nom_chroma = %f\n", __func__, k, p->time_per_pte_group_nom_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9906
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_vblank_chroma = %f\n", __func__, k, p->time_per_pte_group_vblank_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9907
DML_LOG_VERBOSE("DML::%s: k=%u, time_per_pte_group_flip_chroma = %f\n", __func__, k, p->time_per_pte_group_flip_chroma[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9945
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9946
double pixel_clock_mhz = ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9947
bool dcc_mrq_enable = display_cfg->plane_descriptors[k].surface.dcc.enable && mrq_present;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9949
DML_LOG_VERBOSE("DML::%s: k=%u, dcc_mrq_enable = %u\n", __func__, k, dcc_mrq_enable);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9950
DML_LOG_VERBOSE("DML::%s: k=%u, vm_group_bytes = %u\n", __func__, k, vm_group_bytes[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9951
DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_l = %u\n", __func__, k, dpde0_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9952
DML_LOG_VERBOSE("DML::%s: k=%u, dpde0_bytes_per_frame_ub_c = %u\n", __func__, k, dpde0_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9953
DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_l = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_l[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9954
DML_LOG_VERBOSE("DML::%s: k=%d, meta_pte_bytes_per_frame_ub_c = %d\n", __func__, k, meta_pte_bytes_per_frame_ub_c[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9959
num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9961
if (BytePerPixelC[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9962
num_group_per_lower_vm_stage += (unsigned int) math_ceil2((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9966
if (BytePerPixelC[k] > 0) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9967
num_group_per_lower_vm_stage += (unsigned int)(2.0 /*for each mpde0 group*/ + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) +
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9968
math_ceil2((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9970
num_group_per_lower_vm_stage += (unsigned int)(1.0 + math_ceil2((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1));
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9977
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && display_cfg->gpuvm_enable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9978
num_group_per_lower_vm_stage_pref += (unsigned int) math_ceil2(tdlut_pte_bytes_per_frame[k] / vm_group_bytes[k], 1);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9984
num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9985
if (BytePerPixelC[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9986
num_req_per_lower_vm_stage += dpde0_bytes_per_frame_ub_c[k];
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9990
num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_l[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9991
if (BytePerPixelC[k] > 0)
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9992
num_req_per_lower_vm_stage += meta_pte_bytes_per_frame_ub_c[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9998
if (display_cfg->plane_descriptors[k].tdlut.setup_for_tdlut && display_cfg->gpuvm_enable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
9999
num_req_per_lower_vm_stage_pref += tdlut_pte_bytes_per_frame[k] / 64;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
337
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
338
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
339
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
340
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
342
out_bpp[k] = bpc * 3;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
345
out_bpp[k] = bpc * 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
348
out_bpp[k] = bpc * 2;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
352
out_bpp[k] = bpc * 1.5;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
355
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
356
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
358
out_bpp[k] = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
361
DML_LOG_VERBOSE("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
362
DML_LOG_VERBOSE("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
363
DML_LOG_VERBOSE("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
389
for (unsigned int k = 0; k < num_planes; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
390
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
403
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
404
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1292
int i = 0, j = 0, k = 0;
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1317
for (k = 0; k < MAX_PIPES; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1320
if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1321
current_pipe_context = &context->res_ctx.pipe_ctx[k];
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
449
uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
498
for (k = 0; k < 16; k++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
499
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
500
hw_points += (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
504
for (k = 0; k < (region_end - region_start); k++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
505
increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
506
start_index = (region_start + k + MAX_LOW_POINT) *
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
566
k = 0;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
568
if (seg_distr[k] != -1) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
569
regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
571
regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
573
k++;
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
576
if (seg_distr[k] != -1)
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
577
regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
315
uint32_t i, j, k;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
349
for (k = 0; k < dc->res_pool->pipe_count; k++) {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
350
if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
351
context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
353
pipe_counted[k] = 1;
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
358
for (k = 0; k < dc->res_pool->pipe_count; k++) {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
359
if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
360
context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
361
pipe_segments[k] = plane_segments / pipe_plane_count;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2698
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2743
k = 0;
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2749
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2755
&adev->pm.dpm.ps[i], k,
sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c
2757
k++;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1945
u32 k = dte_data->k;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
1954
for (i = 0; i < k; i++) {
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2591
if (dte_data->k <= 0)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
2600
table_size = dte_data->k;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3380
u32 k, a, ah, al;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3386
k = (100 * fh) / fl;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
3387
t1 = (t * (k - 100));
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5892
u8 i, j, k;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5903
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5904
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5906
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5914
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5915
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5917
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5919
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5928
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5929
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5930
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5938
for(k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5939
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
5941
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7319
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7367
k = 0;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7373
if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7379
&adev->pm.dpm.ps[i], k,
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c
7381
k++;
sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.h
898
u32 k;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5445
uint32_t i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5455
for (k = 0; k < watermarks->num_wm_sets; k++) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5456
if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 &&
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5457
dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 &&
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5458
dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 &&
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5459
dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) {
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5461
table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
5467
table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2594
uint8_t i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2608
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2609
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2611
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2620
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2621
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2623
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2626
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2635
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2636
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2637
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2648
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2649
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2651
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
723
int i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
751
for (k = 0; k < SMU7_DTE_SINKS; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
752
dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
753
dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1858
int i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1895
for (k = 0; k < SMU71_DTE_SINKS; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1896
dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
1897
dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2513
uint8_t i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2527
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2528
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2530
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2539
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2540
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2542
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2545
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2555
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2556
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2557
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2568
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2569
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
2571
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
438
int i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
463
for (k = 0; k < SMU74_DTE_SINKS; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
464
table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
465
table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1835
int i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1859
for (k = 0; k < SMU72_DTE_SINKS; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1860
dpm_table->BAPMTI_R[i][j][k] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
1862
dpm_table->BAPMTI_RC[i][j][k] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2977
uint8_t i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2992
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2993
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
2995
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3004
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3005
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3007
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3010
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3019
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3020
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3021
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3031
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3032
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
3034
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1449
int i, j, k;
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1474
for (k = 0; k < SMU75_DTE_SINKS; k++) {
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1475
table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
sys/dev/pci/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
1476
table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
726
int inst, j, k, idx;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
734
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
736
inst = GET_INST(VCN, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
759
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
760
inst = GET_INST(GC, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
781
int ret = 0, xcc_id, inst, i, j, k, idx;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
887
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
889
inst = GET_INST(VCN, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
904
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
905
inst = GET_INST(GC, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2635
int ret, inst, i, j, k, idx;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2676
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2678
inst = GET_INST(VCN, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2705
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2706
inst = GET_INST(GC, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2749
int ret = 0, xcc_id, inst, i, j, k, idx;
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2902
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2904
inst = GET_INST(VCN, k);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2921
for_each_inst(k, inst_mask) {
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
2922
inst = GET_INST(GC, k);
sys/dev/pci/drm/dma-resv.c
185
unsigned int i, j, k, max;
sys/dev/pci/drm/dma-resv.c
215
for (i = 0, j = 0, k = max; i < (old ? old->num_fences : 0); ++i) {
sys/dev/pci/drm/dma-resv.c
221
RCU_INIT_POINTER(new->table[--k], fence);
sys/dev/pci/drm/dma-resv.c
241
for (i = k; i < max; ++i) {
sys/dev/pci/drm/drm_edid.c
3269
BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
sys/dev/pci/drm/drm_edid.c
3271
return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
sys/dev/pci/drm/i915/display/intel_dp.c
644
int i = 0, j = 0, k = 0;
sys/dev/pci/drm/i915/display/intel_dp.c
648
if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
sys/dev/pci/drm/i915/display/intel_dp.c
649
return k;
sys/dev/pci/drm/i915/display/intel_dp.c
650
common_rates[k] = source_rates[i];
sys/dev/pci/drm/i915/display/intel_dp.c
651
++k;
sys/dev/pci/drm/i915/display/intel_dp.c
660
return k;
sys/dev/pci/drm/i915/display/intel_hdcp.c
121
int k;
sys/dev/pci/drm/i915/display/intel_hdcp.c
126
data->k = 0;
sys/dev/pci/drm/i915/display/intel_hdcp.c
143
data->streams[data->k].stream_id =
sys/dev/pci/drm/i915/display/intel_hdcp.c
145
data->k++;
sys/dev/pci/drm/i915/display/intel_hdcp.c
153
if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0))
sys/dev/pci/drm/i915/display/intel_hdcp.c
160
for (k = 0; k < data->k; k++)
sys/dev/pci/drm/i915/display/intel_hdcp.c
161
data->streams[k].stream_type =
sys/dev/pci/drm/i915/display/intel_hdcp.c
1715
msgs.stream_manage.k = cpu_to_be16(data->k);
sys/dev/pci/drm/i915/display/intel_hdcp.c
1717
for (i = 0; i < data->k; i++) {
sys/dev/pci/drm/i915/display/intel_hdcp.c
1722
streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) *
sys/dev/pci/drm/i915/display/intel_hdcp.c
177
data->k = 1;
sys/dev/pci/drm/i915/display/intel_hdcp.c
1909
data->k = 0;
sys/dev/pci/drm/i915/display/intel_hdcp.c
2142
data->k = 0;
sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c
517
cmd_size = struct_size(verify_mprime_in, streams, data->k);
sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c
538
array_size(data->k, sizeof(*data->streams)));
sys/dev/pci/drm/i915/display/intel_hdcp_gsc_message.c
540
verify_mprime_in->k = cpu_to_be16(data->k);
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
250
#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
sys/dev/pci/drm/i915/display/vlv_dpio_phy_regs.h
34
#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1066
int i, j, k, tmp, maxregcount = 0;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1070
for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1071
if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0)
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1074
tmp = guc_cap_list_num_regs(guc->capture, i, j, k);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1609
int i, j, k;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1614
for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) {
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1615
cache = &gc->ads_cache[i][j][k];
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1317
int i, j, k;
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1324
for (k = 0; k < ARRAY_SIZE(types); ++k) {
sys/dev/pci/drm/i915/selftests/intel_memory_region.c
1329
types[k]);
sys/dev/pci/drm/include/drm/display/drm_hdcp.h
216
__be16 k;
sys/dev/pci/drm/include/drm/drm_edid.h
132
u8 k;
sys/dev/pci/drm/include/drm/intel/i915_hdcp_interface.h
17
uint16_t k;
sys/dev/pci/drm/include/linux/ktime.h
100
ktime_add_us(ktime_t k, uint64_t us)
sys/dev/pci/drm/include/linux/ktime.h
102
return k + (us * NSEC_PER_USEC);
sys/dev/pci/drm/include/linux/ktime.h
106
ktime_add_ms(ktime_t k, uint64_t ms)
sys/dev/pci/drm/include/linux/ktime.h
108
return k + (ms * NSEC_PER_MSEC);
sys/dev/pci/drm/include/linux/ktime.h
112
ktime_add_ns(ktime_t k, int64_t ns)
sys/dev/pci/drm/include/linux/ktime.h
114
return k + ns;
sys/dev/pci/drm/include/linux/ktime.h
118
ktime_sub_ns(ktime_t k, int64_t ns)
sys/dev/pci/drm/include/linux/ktime.h
120
return k - ns;
sys/dev/pci/drm/include/linux/ktime.h
45
ktime_to_ms(ktime_t k)
sys/dev/pci/drm/include/linux/ktime.h
47
return k / NSEC_PER_MSEC;
sys/dev/pci/drm/include/linux/ktime.h
51
ktime_to_us(ktime_t k)
sys/dev/pci/drm/include/linux/ktime.h
53
return k / NSEC_PER_USEC;
sys/dev/pci/drm/include/linux/ktime.h
57
ktime_to_ns(ktime_t k)
sys/dev/pci/drm/include/linux/ktime.h
59
return k;
sys/dev/pci/drm/include/linux/ktime.h
75
ktime_to_timespec64(ktime_t k)
sys/dev/pci/drm/include/linux/ktime.h
78
ts.tv_sec = k / NSEC_PER_SEC;
sys/dev/pci/drm/include/linux/ktime.h
79
ts.tv_nsec = k % NSEC_PER_SEC;
sys/dev/pci/drm/include/linux/sysrq.h
10
register_sysrq_key(int k, const struct sysrq_key_op *op)
sys/dev/pci/drm/include/linux/sysrq.h
16
unregister_sysrq_key(int k, const struct sysrq_key_op *op)
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
1012
#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
sys/dev/pci/drm/include/uapi/drm/drm_fourcc.h
1015
(((k) & 0xff) << 12) | \
sys/dev/pci/drm/radeon/btc_dpm.c
1890
u8 i, j, k;
sys/dev/pci/drm/radeon/btc_dpm.c
1899
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/btc_dpm.c
1900
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/btc_dpm.c
1902
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/radeon/btc_dpm.c
1912
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/btc_dpm.c
1913
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/btc_dpm.c
1915
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/btc_dpm.c
1917
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/radeon/btc_dpm.c
1928
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/btc_dpm.c
1929
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/btc_dpm.c
1931
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/ci_dpm.c
409
int i, j, k;
sys/dev/pci/drm/radeon/ci_dpm.c
4292
u8 i, j, k;
sys/dev/pci/drm/radeon/ci_dpm.c
4303
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4304
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ci_dpm.c
4305
((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/radeon/ci_dpm.c
4314
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4315
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ci_dpm.c
4316
(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/ci_dpm.c
4318
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/radeon/ci_dpm.c
4327
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4328
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ci_dpm.c
4329
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/ci_dpm.c
4340
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4341
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ci_dpm.c
4342
(temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/ci_dpm.c
437
for (k = 0; k < SMU7_DTE_SINKS; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
438
dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
sys/dev/pci/drm/radeon/ci_dpm.c
439
dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
sys/dev/pci/drm/radeon/ci_dpm.c
4489
u8 i, k;
sys/dev/pci/drm/radeon/ci_dpm.c
4505
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4506
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
sys/dev/pci/drm/radeon/ci_dpm.c
4507
(table->mc_reg_table_entry[k].mclk_max == 137500))
sys/dev/pci/drm/radeon/ci_dpm.c
4508
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4509
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
sys/dev/pci/drm/radeon/ci_dpm.c
4514
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4515
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
sys/dev/pci/drm/radeon/ci_dpm.c
4516
(table->mc_reg_table_entry[k].mclk_max == 137500))
sys/dev/pci/drm/radeon/ci_dpm.c
4517
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4518
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
sys/dev/pci/drm/radeon/ci_dpm.c
4523
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4524
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
sys/dev/pci/drm/radeon/ci_dpm.c
4525
(table->mc_reg_table_entry[k].mclk_max == 137500))
sys/dev/pci/drm/radeon/ci_dpm.c
4526
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4527
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
sys/dev/pci/drm/radeon/ci_dpm.c
4532
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4533
if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
sys/dev/pci/drm/radeon/ci_dpm.c
4534
(table->mc_reg_table_entry[k].mclk_max == 137500))
sys/dev/pci/drm/radeon/ci_dpm.c
4535
table->mc_reg_table_entry[k].mc_data[i] = 0;
sys/dev/pci/drm/radeon/ci_dpm.c
4539
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4540
if (table->mc_reg_table_entry[k].mclk_max == 125000)
sys/dev/pci/drm/radeon/ci_dpm.c
4541
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4542
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
sys/dev/pci/drm/radeon/ci_dpm.c
4544
else if (table->mc_reg_table_entry[k].mclk_max == 137500)
sys/dev/pci/drm/radeon/ci_dpm.c
4545
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4546
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
sys/dev/pci/drm/radeon/ci_dpm.c
4551
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ci_dpm.c
4552
if (table->mc_reg_table_entry[k].mclk_max == 125000)
sys/dev/pci/drm/radeon/ci_dpm.c
4553
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4554
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
sys/dev/pci/drm/radeon/ci_dpm.c
4556
else if (table->mc_reg_table_entry[k].mclk_max == 137500)
sys/dev/pci/drm/radeon/ci_dpm.c
4557
table->mc_reg_table_entry[k].mc_data[i] =
sys/dev/pci/drm/radeon/ci_dpm.c
4558
(table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
sys/dev/pci/drm/radeon/ci_dpm.c
5495
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/radeon/ci_dpm.c
5549
k = 0;
sys/dev/pci/drm/radeon/ci_dpm.c
5555
if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/radeon/ci_dpm.c
5561
&rdev->pm.dpm.ps[i], k,
sys/dev/pci/drm/radeon/ci_dpm.c
5563
k++;
sys/dev/pci/drm/radeon/cik.c
5783
u32 i, j, k;
sys/dev/pci/drm/radeon/cik.c
5789
for (k = 0; k < rdev->usec_timeout; k++) {
sys/dev/pci/drm/radeon/cik.c
5799
for (k = 0; k < rdev->usec_timeout; k++) {
sys/dev/pci/drm/radeon/cik.c
6549
u32 i, j, k, active_cu_number = 0;
sys/dev/pci/drm/radeon/cik.c
6558
for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
sys/dev/pci/drm/radeon/evergreen.c
4156
u32 dws, data, i, j, k, reg_num;
sys/dev/pci/drm/radeon/evergreen.c
4311
for (k = 0; k < reg_num; k++) {
sys/dev/pci/drm/radeon/evergreen.c
4312
data = cs_data[i].section[j].extent[k];
sys/dev/pci/drm/radeon/evergreen.c
4313
dst_ptr[reg_list_blk_index + k] = cpu_to_le32(data);
sys/dev/pci/drm/radeon/kv_dpm.c
2433
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/radeon/kv_dpm.c
2480
k = 0;
sys/dev/pci/drm/radeon/kv_dpm.c
2486
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/radeon/kv_dpm.c
2492
&rdev->pm.dpm.ps[i], k,
sys/dev/pci/drm/radeon/kv_dpm.c
2494
k++;
sys/dev/pci/drm/radeon/ni_dpm.c
2718
u8 i, j, k;
sys/dev/pci/drm/radeon/ni_dpm.c
2729
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/radeon/ni_dpm.c
2730
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ni_dpm.c
2732
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/radeon/ni_dpm.c
2740
for(k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/ni_dpm.c
2741
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ni_dpm.c
2743
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/ni_dpm.c
2745
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/radeon/ni_dpm.c
2755
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/radeon/ni_dpm.c
2756
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/ni_dpm.c
2758
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/r600_dpm.c
221
u32 k, a, ah, al;
sys/dev/pci/drm/radeon/r600_dpm.c
227
k = (100 * fh) / fl;
sys/dev/pci/drm/radeon/r600_dpm.c
228
t1 = (t * (k - 100));
sys/dev/pci/drm/radeon/radeon_atombios.c
534
int i, j, k, path_size, device_support;
sys/dev/pci/drm/radeon/radeon_atombios.c
652
for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
sys/dev/pci/drm/radeon/radeon_atombios.c
653
u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
sys/dev/pci/drm/radeon/radeon_atombios.c
657
le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
sys/dev/pci/drm/radeon/radeon_atombios.c
683
for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
sys/dev/pci/drm/radeon/radeon_atombios.c
684
u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
sys/dev/pci/drm/radeon/radeon_atombios.c
688
le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
sys/dev/pci/drm/radeon/radeon_atombios.c
696
le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
sys/dev/pci/drm/radeon/radeon_i2c.c
427
int i, j, k, ret = num;
sys/dev/pci/drm/radeon/radeon_i2c.c
571
for (k = 0; k < 32; k++) {
sys/dev/pci/drm/radeon/radeon_i2c.c
603
for (k = 0; k < 32; k++) {
sys/dev/pci/drm/radeon/radeon_i2c.c
631
for (k = 0; k < 32; k++) {
sys/dev/pci/drm/radeon/radeon_test.c
528
int i, j, k;
sys/dev/pci/drm/radeon/radeon_test.c
549
for (k = 0; k < j; ++k) {
sys/dev/pci/drm/radeon/radeon_test.c
550
struct radeon_ring *ringC = &rdev->ring[k];
sys/dev/pci/drm/radeon/radeon_test.c
560
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
sys/dev/pci/drm/radeon/radeon_test.c
563
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
sys/dev/pci/drm/radeon/radeon_test.c
566
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
sys/dev/pci/drm/radeon/radeon_test.c
569
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
sys/dev/pci/drm/radeon/radeon_test.c
572
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
sys/dev/pci/drm/radeon/radeon_test.c
575
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
sys/dev/pci/drm/radeon/si.c
2976
int i, j, k;
sys/dev/pci/drm/radeon/si.c
2986
for (k = 0; k < 16; k++) {
sys/dev/pci/drm/radeon/si.c
2987
mask <<= k;
sys/dev/pci/drm/radeon/si.c
5304
u32 i, j, k, active_cu_number = 0;
sys/dev/pci/drm/radeon/si.c
5313
for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
sys/dev/pci/drm/radeon/si_dpm.c
1777
u32 k = dte_data->k;
sys/dev/pci/drm/radeon/si_dpm.c
1786
for (i = 0; i < k; i++) {
sys/dev/pci/drm/radeon/si_dpm.c
2419
if (dte_data->k <= 0)
sys/dev/pci/drm/radeon/si_dpm.c
2428
table_size = dte_data->k;
sys/dev/pci/drm/radeon/si_dpm.c
5303
u8 i, j, k;
sys/dev/pci/drm/radeon/si_dpm.c
5314
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/radeon/si_dpm.c
5315
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/si_dpm.c
5317
((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
sys/dev/pci/drm/radeon/si_dpm.c
5325
for (k = 0; k < table->num_entries; k++) {
sys/dev/pci/drm/radeon/si_dpm.c
5326
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/si_dpm.c
5328
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/si_dpm.c
5330
table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
sys/dev/pci/drm/radeon/si_dpm.c
5339
for (k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/radeon/si_dpm.c
5340
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/si_dpm.c
5341
(table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
sys/dev/pci/drm/radeon/si_dpm.c
5351
for(k = 0; k < table->num_entries; k++)
sys/dev/pci/drm/radeon/si_dpm.c
5352
table->mc_reg_table_entry[k].mc_data[j] =
sys/dev/pci/drm/radeon/si_dpm.c
5354
(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
sys/dev/pci/drm/radeon/si_dpm.c
6756
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/radeon/si_dpm.c
6806
k = 0;
sys/dev/pci/drm/radeon/si_dpm.c
6812
if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/radeon/si_dpm.c
6818
&rdev->pm.dpm.ps[i], k,
sys/dev/pci/drm/radeon/si_dpm.c
6820
k++;
sys/dev/pci/drm/radeon/si_dpm.h
70
u32 k;
sys/dev/pci/drm/radeon/sumo_dpm.c
1455
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/radeon/sumo_dpm.c
1504
k = 0;
sys/dev/pci/drm/radeon/sumo_dpm.c
1508
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/radeon/sumo_dpm.c
1515
&rdev->pm.dpm.ps[i], k,
sys/dev/pci/drm/radeon/sumo_dpm.c
1517
k++;
sys/dev/pci/drm/radeon/trinity_dpm.c
1686
int i, j, k, non_clock_array_index, clock_array_index;
sys/dev/pci/drm/radeon/trinity_dpm.c
1735
k = 0;
sys/dev/pci/drm/radeon/trinity_dpm.c
1741
if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
sys/dev/pci/drm/radeon/trinity_dpm.c
1747
&rdev->pm.dpm.ps[i], k,
sys/dev/pci/drm/radeon/trinity_dpm.c
1749
k++;
sys/dev/pci/if_ipw.c
1144
struct ieee80211_key *k;
sys/dev/pci/if_ipw.c
1153
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_ipw.c
1155
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_iwi.c
1255
struct ieee80211_key *k;
sys/dev/pci/if_iwi.c
1264
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_iwi.c
1266
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/pci/if_iwm.c
4688
struct ieee80211_key *k = &ni->ni_pairwise_key;
sys/dev/pci/if_iwm.c
4705
prsc = &k->k_rsc[tid];
sys/dev/pci/if_iwm.c
6712
struct ieee80211_key *k = NULL;
sys/dev/pci/if_iwm.c
6823
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_iwm.c
6824
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_iwm.c
6825
(k->k_cipher != IEEE80211_CIPHER_CCMP)) {
sys/dev/pci/if_iwm.c
6826
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_iwm.c
6831
k = NULL; /* skip hardware crypto below */
sys/dev/pci/if_iwm.c
6897
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwm.c
6901
k->k_tsc++; /* increment the 48-bit PN */
sys/dev/pci/if_iwm.c
6902
ivp[0] = k->k_tsc; /* PN0 */
sys/dev/pci/if_iwm.c
6903
ivp[1] = k->k_tsc >> 8; /* PN1 */
sys/dev/pci/if_iwm.c
6905
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/pci/if_iwm.c
6906
ivp[4] = k->k_tsc >> 16; /* PN2 */
sys/dev/pci/if_iwm.c
6907
ivp[5] = k->k_tsc >> 24; /* PN3 */
sys/dev/pci/if_iwm.c
6908
ivp[6] = k->k_tsc >> 32; /* PN4 */
sys/dev/pci/if_iwm.c
6909
ivp[7] = k->k_tsc >> 40; /* PN5 */
sys/dev/pci/if_iwm.c
6912
memcpy(tx->key, k->k_key, MIN(sizeof(tx->key), k->k_len));
sys/dev/pci/if_iwm.c
9114
struct ieee80211_key *k)
sys/dev/pci/if_iwm.c
9123
((k->k_id << IWM_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwm.c
9125
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwm.c
9130
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwm.c
9140
struct ieee80211_key *k)
sys/dev/pci/if_iwm.c
9145
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_iwm.c
9146
k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwm.c
9148
return (ieee80211_set_key(ic, ni, k));
sys/dev/pci/if_iwm.c
9152
return iwm_set_key_v1(ic, ni, k);
sys/dev/pci/if_iwm.c
9158
((k->k_id << IWM_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwm.c
9160
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwm.c
9165
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwm.c
9169
cmd.transmit_seq_cnt = htole64(k->k_tsc);
sys/dev/pci/if_iwm.c
9177
struct ieee80211_key *k)
sys/dev/pci/if_iwm.c
9186
((k->k_id << IWM_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwm.c
9188
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwm.c
9197
struct ieee80211_key *k)
sys/dev/pci/if_iwm.c
9202
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_iwm.c
9203
(k->k_cipher != IEEE80211_CIPHER_CCMP)) {
sys/dev/pci/if_iwm.c
9205
ieee80211_delete_key(ic, ni, k);
sys/dev/pci/if_iwm.c
9213
return iwm_delete_key_v1(ic, ni, k);
sys/dev/pci/if_iwm.c
9219
((k->k_id << IWM_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwm.c
9221
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwn.c
1925
struct ieee80211_key *k = &ni->ni_pairwise_key;
sys/dev/pci/if_iwn.c
1943
prsc = &k->k_rsc[tid];
sys/dev/pci/if_iwn.c
3323
struct ieee80211_key *k = NULL;
sys/dev/pci/if_iwn.c
3418
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_iwn.c
3419
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwn.c
3421
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_iwn.c
3560
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwn.c
3564
k->k_tsc++;
sys/dev/pci/if_iwn.c
3565
ivp[0] = k->k_tsc;
sys/dev/pci/if_iwn.c
3566
ivp[1] = k->k_tsc >> 8;
sys/dev/pci/if_iwn.c
3568
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/pci/if_iwn.c
3569
ivp[4] = k->k_tsc >> 16;
sys/dev/pci/if_iwn.c
3570
ivp[5] = k->k_tsc >> 24;
sys/dev/pci/if_iwn.c
3571
ivp[6] = k->k_tsc >> 32;
sys/dev/pci/if_iwn.c
3572
ivp[7] = k->k_tsc >> 40;
sys/dev/pci/if_iwn.c
3577
memcpy(tx->key, k->k_key, k->k_len);
sys/dev/pci/if_iwn.c
5655
struct ieee80211_key *k)
sys/dev/pci/if_iwn.c
5663
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_iwn.c
5664
k->k_cipher != IEEE80211_CIPHER_CCMP)
sys/dev/pci/if_iwn.c
5665
return ieee80211_set_key(ic, ni, k);
sys/dev/pci/if_iwn.c
5667
kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id);
sys/dev/pci/if_iwn.c
5668
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwn.c
5672
node.id = (k->k_flags & IEEE80211_KEY_GROUP) ?
sys/dev/pci/if_iwn.c
5677
node.kid = k->k_id;
sys/dev/pci/if_iwn.c
5678
memcpy(node.key, k->k_key, k->k_len);
sys/dev/pci/if_iwn.c
5679
DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id));
sys/dev/pci/if_iwn.c
5685
struct ieee80211_key *k)
sys/dev/pci/if_iwn.c
5692
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_iwn.c
5693
k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwn.c
5695
ieee80211_delete_key(ic, ni, k);
sys/dev/pci/if_iwn.c
5701
node.id = (k->k_flags & IEEE80211_KEY_GROUP) ?
sys/dev/pci/if_iwnreg.h
1037
#define IWN_KTOC(k) ((k) - 273)
sys/dev/pci/if_iwx.c
4708
struct ieee80211_key *k;
sys/dev/pci/if_iwx.c
4720
k = ieee80211_get_rxkey(ic, m, ni);
sys/dev/pci/if_iwx.c
4721
if (k == NULL || k->k_cipher != IEEE80211_CIPHER_CCMP)
sys/dev/pci/if_iwx.c
4730
prsc = &k->k_rsc[tid];
sys/dev/pci/if_iwx.c
6225
struct ieee80211_key *k = NULL;
sys/dev/pci/if_iwx.c
6308
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_iwx.c
6317
if (k->k_flags & IEEE80211_KEY_IGTK) {
sys/dev/pci/if_iwx.c
6322
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_iwx.c
6323
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_iwx.c
6329
k->k_tsc++;
sys/dev/pci/if_iwx.c
8380
struct ieee80211_key *k;
sys/dev/pci/if_iwx.c
8390
k = &ic->ic_nw_keys[ic->ic_def_txkey];
sys/dev/pci/if_iwx.c
8391
if ((k->k_flags & IEEE80211_KEY_GROUP) &&
sys/dev/pci/if_iwx.c
8392
k->k_cipher == IEEE80211_CIPHER_CCMP)
sys/dev/pci/if_iwx.c
8393
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/pci/if_iwx.c
8399
k = &ic->ic_nw_keys[ic->ic_igtk_kid];
sys/dev/pci/if_iwx.c
8400
if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/pci/if_iwx.c
8401
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/pci/if_iwx.c
9302
struct ieee80211_key *k)
sys/dev/pci/if_iwx.c
9309
if (k->k_cipher != IEEE80211_CIPHER_CCMP &&
sys/dev/pci/if_iwx.c
9310
(k->k_flags & IEEE80211_KEY_IGTK) == 0) {
sys/dev/pci/if_iwx.c
9312
err = ieee80211_set_key(ic, ni, k);
sys/dev/pci/if_iwx.c
9313
if (!err && in != NULL && (k->k_flags & IEEE80211_KEY_GROUP))
sys/dev/pci/if_iwx.c
9324
a->k = k;
sys/dev/pci/if_iwx.c
9333
struct ieee80211_node *ni, struct ieee80211_key *k,
sys/dev/pci/if_iwx.c
9341
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwx.c
9343
else if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/pci/if_iwx.c
9350
cmd.u.add.key_id = htole32(k->k_id);
sys/dev/pci/if_iwx.c
9352
cmd.u.add.tx_seq = htole64(k->k_tsc);
sys/dev/pci/if_iwx.c
9353
memcpy(cmd.u.add.key, k->k_key, k->k_len);
sys/dev/pci/if_iwx.c
9373
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwx.c
9374
ic->ic_def_txkey = k->k_id;
sys/dev/pci/if_iwx.c
9375
if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/pci/if_iwx.c
9376
ic->ic_igtk_kid = k->k_id;
sys/dev/pci/if_iwx.c
9384
struct ieee80211_node *ni, struct ieee80211_key *k)
sys/dev/pci/if_iwx.c
9395
((k->k_id << IWX_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwx.c
9397
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/pci/if_iwx.c
9406
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwx.c
9409
cmd.transmit_seq_cnt = htole64(k->k_tsc);
sys/dev/pci/if_iwx.c
9425
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwx.c
9426
ic->ic_def_txkey = k->k_id;
sys/dev/pci/if_iwx.c
9433
struct ieee80211_key *k, int remove_key)
sys/dev/pci/if_iwx.c
9438
if (k == &ni->ni_pairwise_key ||
sys/dev/pci/if_iwx.c
9439
(k->k_id != 4 && k->k_id != 5 &&
sys/dev/pci/if_iwx.c
9440
k->k_id != 6 && k->k_id != 7) ||
sys/dev/pci/if_iwx.c
9442
k->k_cipher != IEEE80211_CIPHER_BIP)
sys/dev/pci/if_iwx.c
9447
k->k_cipher != IEEE80211_CIPHER_BIP)
sys/dev/pci/if_iwx.c
9450
igtk_cmd.key_id = htole32(k->k_id);
sys/dev/pci/if_iwx.c
9456
switch (k->k_cipher) {
sys/dev/pci/if_iwx.c
9465
memcpy(igtk_cmd.igtk, k->k_key, k->k_len);
sys/dev/pci/if_iwx.c
9466
igtk_cmd.receive_seq_cnt = htole64(k->k_mgmt_rsc);
sys/dev/pci/if_iwx.c
9471
k->k_id >= 6 ? "B" : "", k->k_id, sta_id));
sys/dev/pci/if_iwx.c
9495
struct ieee80211_key *k)
sys/dev/pci/if_iwx.c
9517
err = iwx_mld_set_sta_key_cmd(sc, sta_id, ni, k, 0);
sys/dev/pci/if_iwx.c
9518
else if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/pci/if_iwx.c
9519
err = iwx_set_sta_igtk(sc, sta_id, ni, k, 0);
sys/dev/pci/if_iwx.c
9521
err = iwx_add_sta_key_cmd(sc, sta_id, ni, k);
sys/dev/pci/if_iwx.c
9525
if (k->k_flags & IEEE80211_KEY_IGTK) {
sys/dev/pci/if_iwx.c
9527
ic->ic_igtk_kid = k->k_id;
sys/dev/pci/if_iwx.c
9528
} else if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/pci/if_iwx.c
9530
ic->ic_def_txkey = k->k_id;
sys/dev/pci/if_iwx.c
9557
err = iwx_add_sta_key(sc, a->sta_id, a->ni, a->k);
sys/dev/pci/if_iwx.c
9560
a->k = NULL;
sys/dev/pci/if_iwx.c
9572
struct ieee80211_key *k)
sys/dev/pci/if_iwx.c
9578
if (k->k_cipher != IEEE80211_CIPHER_CCMP &&
sys/dev/pci/if_iwx.c
9579
(k->k_flags & IEEE80211_KEY_IGTK) == 0) {
sys/dev/pci/if_iwx.c
9581
ieee80211_delete_key(ic, ni, k);
sys/dev/pci/if_iwx.c
9591
iwx_mld_set_sta_key_cmd(sc, IWX_STATION_ID, ni, k, 1);
sys/dev/pci/if_iwx.c
9595
if (k->k_flags & IEEE80211_KEY_IGTK) {
sys/dev/pci/if_iwx.c
9596
iwx_set_sta_igtk(sc, IWX_STATION_ID, ni, k, 1);
sys/dev/pci/if_iwx.c
9604
((k->k_id << IWX_STA_KEY_FLG_KEYID_POS) &
sys/dev/pci/if_iwx.c
9606
memcpy(cmd.common.key, k->k_key, MIN(sizeof(cmd.common.key), k->k_len));
sys/dev/pci/if_iwx.c
9607
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/pci/if_iwxvar.h
444
struct ieee80211_key *k;
sys/dev/pci/if_ix.c
791
uint32_t k, txdctl, rxdctl, rxctrl, mhadd, itr;
sys/dev/pci/if_ix.c
883
for (k = 0; k < 10; k++) {
sys/dev/pci/if_ixv.c
1009
for (k = 0; k < 10; k++) {
sys/dev/pci/if_ixv.c
948
int i, j, k;
sys/dev/pci/if_mwx.c
1243
struct ieee80211_key *k;
sys/dev/pci/if_mwx.c
1254
k = &ic->ic_nw_keys[ic->ic_def_txkey];
sys/dev/pci/if_mwx.c
1255
if ((k->k_flags & IEEE80211_KEY_GROUP) &&
sys/dev/pci/if_mwx.c
1256
k->k_cipher == IEEE80211_CIPHER_CCMP)
sys/dev/pci/if_mwx.c
1257
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/pci/if_mwx.c
1261
k = &ic->ic_nw_keys[ic->ic_igtk_kid];
sys/dev/pci/if_mwx.c
1262
if (k->k_flags & IEEE80211_KEY_IGTK)
sys/dev/pci/if_mwx.c
1263
(*ic->ic_delete_key)(ic, ni, k);
sys/dev/pci/if_mwx.c
1299
struct ieee80211_key *k)
sys/dev/pci/if_mwx.c
1305
DEVNAME(sc), ni, k->k_id, k->k_flags, k->k_cipher);
sys/dev/pci/if_mwx.c
1313
a->k = k;
sys/dev/pci/if_mwx.c
1321
struct ieee80211_key *k)
sys/dev/pci/if_mwx.c
1326
DEVNAME(sc), ni, k->k_id, k->k_flags, k->k_cipher);
sys/dev/pci/if_mwx.c
1328
mt7921_mcu_sta_key_delete(sc, ni, k);
sys/dev/pci/if_mwx.c
1340
mt7921_mcu_sta_key_update(sc, a->ni, a->k);
sys/dev/pci/if_mwx.c
1342
a->k = NULL;
sys/dev/pci/if_mwx.c
289
struct ieee80211_key *k;
sys/dev/pci/if_mwx.c
6118
mt7921_key_to_cipher_id(struct ieee80211_key *k)
sys/dev/pci/if_mwx.c
6120
switch (k->k_cipher) {
sys/dev/pci/if_mwx.c
6138
struct ieee80211_key *k, int add)
sys/dev/pci/if_mwx.c
6151
key->cipher_id = mt7921_key_to_cipher_id(k);
sys/dev/pci/if_mwx.c
6153
key->key_id = k->k_id;
sys/dev/pci/if_mwx.c
6154
key->key_len = k->k_len;
sys/dev/pci/if_mwx.c
6156
CTASSERT(sizeof(k->k_key) == sizeof(key->key));
sys/dev/pci/if_mwx.c
6157
memcpy(key->key, k->k_key, k->k_len);
sys/dev/pci/if_mwx.c
6160
k->k_len == sizeof(key->key)) {
sys/dev/pci/if_mwx.c
6162
memcpy(key->key + 16, k->k_key + 24, 8);
sys/dev/pci/if_mwx.c
6163
memcpy(key->key + 24, k->k_key + 16, 8);
sys/dev/pci/if_mwx.c
6173
struct ieee80211_key *k)
sys/dev/pci/if_mwx.c
6185
if ((k->k_flags & IEEE80211_KEY_GROUP) != 0) {
sys/dev/pci/if_mwx.c
6197
DEVNAME(sc), "add key", ni, k->k_id, k->k_flags, k->k_cipher, wcid);
sys/dev/pci/if_mwx.c
6199
mt7921_mcu_add_key_tlv(m, &tlvnum, k, 1);
sys/dev/pci/if_mwx.c
6207
if ((k->k_flags & IEEE80211_KEY_GROUP) != 0)
sys/dev/pci/if_mwx.c
6226
struct ieee80211_key *k)
sys/dev/pci/if_mwx.c
6235
if ((k->k_flags & IEEE80211_KEY_GROUP) != 0) {
sys/dev/pci/if_mwx.c
6247
DEVNAME(sc), "delete key", ni, k->k_id, k->k_flags, k->k_cipher,
sys/dev/pci/if_mwx.c
6250
mt7921_mcu_add_key_tlv(m, &tlvnum, k, 0);
sys/dev/pci/if_rtwn.c
1033
if (k != NULL) {
sys/dev/pci/if_rtwn.c
1034
switch (k->k_cipher) {
sys/dev/pci/if_rtwn.c
983
struct ieee80211_key *k = NULL;
sys/dev/pci/if_rtwn.c
995
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_rtwn.c
996
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_wpi.c
1130
wpi_ccmp_decap(struct wpi_softc *sc, struct mbuf *m, struct ieee80211_key *k)
sys/dev/pci/if_wpi.c
1150
prsc = &k->k_rsc[tid];
sys/dev/pci/if_wpi.c
1655
struct ieee80211_key *k = NULL;
sys/dev/pci/if_wpi.c
1714
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/pci/if_wpi.c
1715
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_wpi.c
1717
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/pci/if_wpi.c
1793
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_wpi.c
1797
k->k_tsc++;
sys/dev/pci/if_wpi.c
1798
ivp[0] = k->k_tsc;
sys/dev/pci/if_wpi.c
1799
ivp[1] = k->k_tsc >> 8;
sys/dev/pci/if_wpi.c
1801
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/pci/if_wpi.c
1802
ivp[4] = k->k_tsc >> 16;
sys/dev/pci/if_wpi.c
1803
ivp[5] = k->k_tsc >> 24;
sys/dev/pci/if_wpi.c
1804
ivp[6] = k->k_tsc >> 32;
sys/dev/pci/if_wpi.c
1805
ivp[7] = k->k_tsc >> 40;
sys/dev/pci/if_wpi.c
1808
memcpy(tx->key, k->k_key, k->k_len);
sys/dev/pci/if_wpi.c
2739
struct ieee80211_key *k)
sys/dev/pci/if_wpi.c
2746
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_wpi.c
2747
k->k_cipher != IEEE80211_CIPHER_CCMP)
sys/dev/pci/if_wpi.c
2748
return ieee80211_set_key(ic, ni, k);
sys/dev/pci/if_wpi.c
2750
kflags = WPI_KFLAG_CCMP | WPI_KFLAG_KID(k->k_id);
sys/dev/pci/if_wpi.c
2756
memcpy(node.key, k->k_key, k->k_len);
sys/dev/pci/if_wpi.c
2757
DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id));
sys/dev/pci/if_wpi.c
2763
struct ieee80211_key *k)
sys/dev/pci/if_wpi.c
2769
if ((k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/pci/if_wpi.c
2770
k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/pci/if_wpi.c
2772
ieee80211_delete_key(ic, ni, k);
sys/dev/pci/igc_i225.c
537
uint32_t i, k, eewr = 0;
sys/dev/pci/igc_i225.c
559
for (k = 0; k < attempts; k++) {
sys/dev/usb/if_athn_usb.c
1633
struct ieee80211_key *k)
sys/dev/usb/if_athn_usb.c
1643
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_athn_usb.c
1645
return ieee80211_set_key(ic, ni, k);
sys/dev/usb/if_athn_usb.c
1650
cmd.key = k;
sys/dev/usb/if_athn_usb.c
1681
struct ieee80211_key *k)
sys/dev/usb/if_athn_usb.c
1690
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_athn_usb.c
1691
ieee80211_delete_key(ic, ni, k);
sys/dev/usb/if_athn_usb.c
1697
cmd.key = k;
sys/dev/usb/if_athn_usb.c
2280
struct ieee80211_key *k = NULL;
sys/dev/usb/if_athn_usb.c
2293
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_athn_usb.c
2294
if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_athn_usb.c
2296
if (ar5008_ccmp_encap(m, hdrlen, k) != 0)
sys/dev/usb/if_athn_usb.c
2299
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/usb/if_athn_usb.c
2301
k = NULL; /* skip hardware crypto further below */
sys/dev/usb/if_athn_usb.c
2360
if (k != NULL) {
sys/dev/usb/if_athn_usb.c
2362
if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_athn_usb.c
2370
txf->key_idx = (uintptr_t)k->k_priv;
sys/dev/usb/if_mtw.c
1765
struct ieee80211_key *k)
sys/dev/usb/if_mtw.c
1776
cmd.key = *k;
sys/dev/usb/if_mtw.c
1788
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_mtw.c
1796
switch (k->k_cipher) {
sys/dev/usb/if_mtw.c
1819
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_mtw.c
1821
base = MTW_SKEY(0, k->k_id);
sys/dev/usb/if_mtw.c
1827
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/usb/if_mtw.c
1828
mtw_write_region_1(sc, base, k->k_key, 16);
sys/dev/usb/if_mtw.c
1829
mtw_write_region_1(sc, base + 16, &k->k_key[24], 8);
sys/dev/usb/if_mtw.c
1830
mtw_write_region_1(sc, base + 24, &k->k_key[16], 8);
sys/dev/usb/if_mtw.c
1833
mtw_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1);
sys/dev/usb/if_mtw.c
1836
if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/usb/if_mtw.c
1837
(k->k_flags & IEEE80211_KEY_TX)) {
sys/dev/usb/if_mtw.c
1839
if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/usb/if_mtw.c
1840
k->k_cipher == IEEE80211_CIPHER_WEP104) {
sys/dev/usb/if_mtw.c
1844
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/usb/if_mtw.c
1845
iv[0] = k->k_tsc >> 8;
sys/dev/usb/if_mtw.c
1847
iv[2] = k->k_tsc;
sys/dev/usb/if_mtw.c
1849
iv[0] = k->k_tsc;
sys/dev/usb/if_mtw.c
1850
iv[1] = k->k_tsc >> 8;
sys/dev/usb/if_mtw.c
1853
iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/usb/if_mtw.c
1854
iv[4] = k->k_tsc >> 16;
sys/dev/usb/if_mtw.c
1855
iv[5] = k->k_tsc >> 24;
sys/dev/usb/if_mtw.c
1856
iv[6] = k->k_tsc >> 32;
sys/dev/usb/if_mtw.c
1857
iv[7] = k->k_tsc >> 40;
sys/dev/usb/if_mtw.c
1862
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_mtw.c
1865
attr &= ~(0xf << (k->k_id * 4));
sys/dev/usb/if_mtw.c
1866
attr |= mode << (k->k_id * 4);
sys/dev/usb/if_mtw.c
1869
if (k->k_cipher & (IEEE80211_CIPHER_WEP104 |
sys/dev/usb/if_mtw.c
1897
struct ieee80211_key *k)
sys/dev/usb/if_mtw.c
1907
cmd.key = *k;
sys/dev/usb/if_mtw.c
1916
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_mtw.c
1920
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_mtw.c
1923
attr &= ~(0xf << (k->k_id * 4));
sys/dev/usb/if_otus.c
1280
struct ieee80211_key *k;
sys/dev/usb/if_otus.c
1289
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_otus.c
1290
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/usb/if_otus.c
2038
struct ieee80211_key *k)
sys/dev/usb/if_otus.c
2049
cmd.key = *k;
sys/dev/usb/if_otus.c
2060
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_otus.c
2068
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_otus.c
2069
key.uid = htole16(k->k_id);
sys/dev/usb/if_otus.c
2078
switch (k->k_cipher) {
sys/dev/usb/if_otus.c
2098
memcpy(key.key, k->k_key, MIN(k->k_len, 16));
sys/dev/usb/if_otus.c
2100
if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) {
sys/dev/usb/if_otus.c
2109
memcpy(key.key, k->k_key + 16, 16);
sys/dev/usb/if_otus.c
2122
struct ieee80211_key *k)
sys/dev/usb/if_otus.c
2132
cmd.key = *k;
sys/dev/usb/if_otus.c
2141
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_otus.c
2144
if (k->k_flags & IEEE80211_KEY_GROUP)
sys/dev/usb/if_otus.c
2145
uid = htole32(k->k_id);
sys/dev/usb/if_ral.c
1014
struct ieee80211_key *k;
sys/dev/usb/if_ral.c
1023
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_ral.c
1025
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/usb/if_ral.c
1944
struct ieee80211_key *k = &ic->ic_nw_keys[i];
sys/dev/usb/if_ral.c
1946
k->k_key, IEEE80211_KEYBUF_SIZE);
sys/dev/usb/if_rsu.c
1510
struct ieee80211_key *k = NULL;
sys/dev/usb/if_rsu.c
1522
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_rsu.c
1523
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/usb/if_rsu.c
1556
if (k != NULL) {
sys/dev/usb/if_rsu.c
1557
switch (k->k_cipher) {
sys/dev/usb/if_rsu.c
1573
SM(R92S_TXDW1_KEYIDX, k->k_id));
sys/dev/usb/if_rsu.c
885
struct ieee80211_key *k)
sys/dev/usb/if_rsu.c
896
cmd.key = *k;
sys/dev/usb/if_rsu.c
908
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_rsu.c
915
switch (k->k_cipher) {
sys/dev/usb/if_rsu.c
934
key.id = k->k_id;
sys/dev/usb/if_rsu.c
935
key.grpkey = (k->k_flags & IEEE80211_KEY_GROUP) != 0;
sys/dev/usb/if_rsu.c
936
memcpy(key.key, k->k_key, MIN(k->k_len, sizeof(key.key)));
sys/dev/usb/if_rsu.c
949
struct ieee80211_key *k)
sys/dev/usb/if_rsu.c
959
cmd.key = *k;
sys/dev/usb/if_rsu.c
967
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_rsu.c
971
key.id = k->k_id;
sys/dev/usb/if_rum.c
1031
struct ieee80211_key *k;
sys/dev/usb/if_rum.c
1040
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_rum.c
1042
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/usb/if_run.c
1912
struct ieee80211_key *k)
sys/dev/usb/if_run.c
1923
cmd.key = *k;
sys/dev/usb/if_run.c
1936
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_run.c
1944
switch (k->k_cipher) {
sys/dev/usb/if_run.c
1964
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_run.c
1966
base = RT2860_SKEY(0, k->k_id);
sys/dev/usb/if_run.c
1972
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/usb/if_run.c
1973
run_write_region_1(sc, base, k->k_key, 16);
sys/dev/usb/if_run.c
1974
run_write_region_1(sc, base + 16, &k->k_key[24], 8);
sys/dev/usb/if_run.c
1975
run_write_region_1(sc, base + 24, &k->k_key[16], 8);
sys/dev/usb/if_run.c
1978
run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1);
sys/dev/usb/if_run.c
1981
if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
sys/dev/usb/if_run.c
1982
(k->k_flags & IEEE80211_KEY_TX)) {
sys/dev/usb/if_run.c
1984
if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
sys/dev/usb/if_run.c
1985
k->k_cipher == IEEE80211_CIPHER_WEP104) {
sys/dev/usb/if_run.c
1989
if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
sys/dev/usb/if_run.c
1990
iv[0] = k->k_tsc >> 8;
sys/dev/usb/if_run.c
1992
iv[2] = k->k_tsc;
sys/dev/usb/if_run.c
1994
iv[0] = k->k_tsc;
sys/dev/usb/if_run.c
1995
iv[1] = k->k_tsc >> 8;
sys/dev/usb/if_run.c
1998
iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
sys/dev/usb/if_run.c
1999
iv[4] = k->k_tsc >> 16;
sys/dev/usb/if_run.c
2000
iv[5] = k->k_tsc >> 24;
sys/dev/usb/if_run.c
2001
iv[6] = k->k_tsc >> 32;
sys/dev/usb/if_run.c
2002
iv[7] = k->k_tsc >> 40;
sys/dev/usb/if_run.c
2007
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_run.c
2010
attr &= ~(0xf << (k->k_id * 4));
sys/dev/usb/if_run.c
2011
attr |= mode << (k->k_id * 4);
sys/dev/usb/if_run.c
2029
struct ieee80211_key *k)
sys/dev/usb/if_run.c
2039
cmd.key = *k;
sys/dev/usb/if_run.c
2048
struct ieee80211_key *k = &cmd->key;
sys/dev/usb/if_run.c
2052
if (k->k_flags & IEEE80211_KEY_GROUP) {
sys/dev/usb/if_run.c
2055
attr &= ~(0xf << (k->k_id * 4));
sys/dev/usb/if_run.c
2972
rf = (rf & ~0x0f) | rt3070_freqs[i].k;
sys/dev/usb/if_run.c
3045
run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k);
sys/dev/usb/if_run.c
3196
run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
sys/dev/usb/if_run.c
3347
run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
sys/dev/usb/if_run.c
3479
rf |= (freqs->k & 0x0f);
sys/dev/usb/if_run.c
472
uint8_t n, r, k;
sys/dev/usb/if_run.c
479
uint8_t k, m, r;
sys/dev/usb/if_uath.c
1695
uath_set_key(struct uath_softc *sc, const struct ieee80211_key *k, int index)
sys/dev/usb/if_uath.c
1714
for (i = 0; i < k->k_len; i++)
sys/dev/usb/if_uath.c
1715
crypto.key[i] = k->k_key[i] ^ 0xaa;
sys/dev/usb/if_uath.c
1717
DPRINTF(("setting crypto key index=%d len=%d\n", index, k->k_len));
sys/dev/usb/if_uath.c
1728
const struct ieee80211_key *k = &ic->ic_nw_keys[i];
sys/dev/usb/if_uath.c
1730
if (k->k_len > 0 && (error = uath_set_key(sc, k, i)) != 0)
sys/dev/usb/if_upgt.c
1432
struct ieee80211_key *k;
sys/dev/usb/if_upgt.c
1462
k = ieee80211_get_txkey(ic, wh, ic->ic_bss);
sys/dev/usb/if_upgt.c
1464
if ((m = ieee80211_encrypt(ic, m, k)) == NULL) {
sys/dev/usb/if_urtw.c
2568
struct ieee80211_key *k;
sys/dev/usb/if_urtw.c
2575
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_urtw.c
2577
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
sys/dev/usb/if_urtwn.c
1034
struct ieee80211_key *k)
sys/dev/usb/if_urtwn.c
1042
if (k->k_cipher != IEEE80211_CIPHER_CCMP)
sys/dev/usb/if_urtwn.c
1043
return ieee80211_set_key(ic, ni, k);
sys/dev/usb/if_urtwn.c
1051
cmd.key = *k;
sys/dev/usb/if_urtwn.c
1083
struct ieee80211_key *k)
sys/dev/usb/if_urtwn.c
1091
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_urtwn.c
1092
ieee80211_delete_key(ic, ni, k);
sys/dev/usb/if_urtwn.c
1101
cmd.key = *k;
sys/dev/usb/if_urtwn.c
1120
struct ieee80211_key *k;
sys/dev/usb/if_urtwn.c
1127
k = ieee80211_get_rxkey(ic, m, ni);
sys/dev/usb/if_urtwn.c
1128
if (k == NULL)
sys/dev/usb/if_urtwn.c
1141
prsc = &k->k_rsc[tid];
sys/dev/usb/if_urtwn.c
1450
struct ieee80211_frame *wh, struct ieee80211_key *k,
sys/dev/usb/if_urtwn.c
1463
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_urtwn.c
1553
struct ieee80211_frame *wh, struct ieee80211_key *k,
sys/dev/usb/if_urtwn.c
1568
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_urtwn.c
1639
struct ieee80211_key *k = NULL;
sys/dev/usb/if_urtwn.c
1650
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_urtwn.c
1651
if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_urtwn.c
1652
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/usb/if_urtwn.c
1679
urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni);
sys/dev/usb/if_urtwn.c
1681
urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni);
sys/dev/usb/if_urtwn.c
1708
if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) {
sys/dev/usb/if_urtwn.c
1716
k->k_tsc++;
sys/dev/usb/if_urtwn.c
1717
txdp[0] = k->k_tsc;
sys/dev/usb/if_urtwn.c
1718
txdp[1] = k->k_tsc >> 8;
sys/dev/usb/if_urtwn.c
1720
txdp[3] = k->k_id | IEEE80211_WEP_EXTIV;
sys/dev/usb/if_urtwn.c
1721
txdp[4] = k->k_tsc >> 16;
sys/dev/usb/if_urtwn.c
1722
txdp[5] = k->k_tsc >> 24;
sys/dev/usb/if_urtwn.c
1723
txdp[6] = k->k_tsc >> 32;
sys/dev/usb/if_urtwn.c
1724
txdp[7] = k->k_tsc >> 40;
sys/dev/usb/if_zyd.c
2099
struct ieee80211_key *k;
sys/dev/usb/if_zyd.c
2107
k = ieee80211_get_txkey(ic, wh, ni);
sys/dev/usb/if_zyd.c
2108
if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
sys/dev/wscons/wsksymdef.h
699
#define KS_GROUP(k) ((k) >= 0x0300 && (k) < 0x0370 ? KS_GROUP_Dead : \
sys/dev/wscons/wsksymdef.h
700
(((k) & 0xf000) == 0xe000 ? KS_GROUP_Keycode : \
sys/dev/wscons/wsksymdef.h
701
(((k) & 0xf800) == 0xf000 ? ((k) & 0xff00) : \
sys/dev/wscons/wsksymdef.h
704
#define KS_VALUE(k) (((k) & 0xf000) == 0xe000 ? ((k) & 0x0fff) : \
sys/dev/wscons/wsksymdef.h
705
(((k) & 0xf800) == 0xf000 ? ((k) & 0x00ff) : (k)))
sys/dev/wscons/wsmouse.c
1254
int i, j, k, d, e, row, col, delta;
sys/dev/wscons/wsmouse.c
1281
for (k = 0; (j = r2c[row]) >= 0;) {
sys/dev/wscons/wsmouse.c
1282
cs[k++] = j;
sys/dev/wscons/wsmouse.c
1302
for (i = 0; i < k; i++) {
sys/kern/subr_userconf.c
1183
int i = 0, j = 0, k;
sys/kern/subr_userconf.c
1196
k = -1;
sys/kern/subr_userconf.c
1200
k = j;
sys/kern/subr_userconf.c
1208
if (k == -1) {
sys/kern/subr_userconf.c
1212
switch (*userconf_cmds[k+1]) {
sys/kern/subr_userconf.c
686
int j = 0, k;
sys/kern/subr_userconf.c
691
k = strlen(userconf_cmds[j]);
sys/kern/subr_userconf.c
692
while (k < 10) {
sys/kern/subr_userconf.c
694
k++;
sys/lib/libsa/blowfish.c
412
u_int16_t k;
sys/lib/libsa/blowfish.c
435
for (k = 0; k < 256; k += 2) {
sys/lib/libsa/blowfish.c
438
c->S[i][k] = datal;
sys/lib/libsa/blowfish.c
439
c->S[i][k + 1] = datar;
sys/lib/libsa/blowfish.c
450
u_int16_t k;
sys/lib/libsa/blowfish.c
475
for (k = 0; k < 256; k += 2) {
sys/lib/libsa/blowfish.c
480
c->S[i][k] = datal;
sys/lib/libsa/blowfish.c
481
c->S[i][k + 1] = datar;
sys/lib/libsa/blowfish.c
488
blf_key(blf_ctx *c, const u_int8_t *k, u_int16_t len)
sys/lib/libsa/blowfish.c
494
Blowfish_expand0state(c, k, len);
sys/lib/libz/crc32.c
182
local uLong x2nmodp(z_off64_t n, unsigned k) {
sys/lib/libz/crc32.c
188
p = multmodp(x2n_table[k & 31], p);
sys/lib/libz/crc32.c
190
k++;
sys/lib/libz/crc32.c
279
int k, n;
sys/lib/libz/crc32.c
338
for (k = 0; k < 8; k++) {
sys/lib/libz/crc32.c
340
write_table(out, ltl[k], 256);
sys/lib/libz/crc32.c
341
fprintf(out, "}%s", k < 7 ? ",\n" : "");
sys/lib/libz/crc32.c
347
for (k = 0; k < 8; k++) {
sys/lib/libz/crc32.c
349
write_table64(out, big[k], 256);
sys/lib/libz/crc32.c
350
fprintf(out, "}%s", k < 7 ? ",\n" : "");
sys/lib/libz/crc32.c
364
for (k = 0; k < 4; k++) {
sys/lib/libz/crc32.c
366
write_table(out, ltl[k], 256);
sys/lib/libz/crc32.c
367
fprintf(out, "}%s", k < 3 ? ",\n" : "");
sys/lib/libz/crc32.c
373
for (k = 0; k < 4; k++) {
sys/lib/libz/crc32.c
375
write_table32hi(out, big[k], 256);
sys/lib/libz/crc32.c
376
fprintf(out, "}%s", k < 3 ? ",\n" : "");
sys/lib/libz/crc32.c
408
local void write_table(FILE *out, const z_crc_t FAR *table, int k) {
sys/lib/libz/crc32.c
411
for (n = 0; n < k; n++)
sys/lib/libz/crc32.c
414
n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", "));
sys/lib/libz/crc32.c
421
local void write_table32hi(FILE *out, const z_word_t FAR *table, int k) {
sys/lib/libz/crc32.c
424
for (n = 0; n < k; n++)
sys/lib/libz/crc32.c
427
n == k - 1 ? "" : (n % 5 == 4 ? ",\n" : ", "));
sys/lib/libz/crc32.c
437
local void write_table64(FILE *out, const z_word_t FAR *table, int k) {
sys/lib/libz/crc32.c
440
for (n = 0; n < k; n++)
sys/lib/libz/crc32.c
443
n == k - 1 ? "" : (n % 3 == 2 ? ",\n" : ", "));
sys/lib/libz/crc32.c
460
int k;
sys/lib/libz/crc32.c
462
for (k = 0; k < w; k++) {
sys/lib/libz/crc32.c
463
p = (z_crc_t)x2nmodp((n * w + 3 - k) << 3, 0);
sys/lib/libz/crc32.c
464
ltl[k][0] = 0;
sys/lib/libz/crc32.c
465
big[w - 1 - k][0] = 0;
sys/lib/libz/crc32.c
467
ltl[k][i] = q = (z_crc_t)multmodp(i << 24, p);
sys/lib/libz/crc32.c
468
big[w - 1 - k][i] = byte_swap(q);
sys/lib/libz/crc32.c
607
int k;
sys/lib/libz/crc32.c
608
for (k = 0; k < W; k++)
sys/lib/libz/crc32.c
614
int k;
sys/lib/libz/crc32.c
615
for (k = 0; k < W; k++)
sys/lib/libz/crc32.c
642
int k;
sys/lib/libz/crc32.c
746
for (k = 1; k < W; k++) {
sys/lib/libz/crc32.c
747
crc0 ^= crc_braid_table[k][(word0 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
749
crc1 ^= crc_braid_table[k][(word1 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
751
crc2 ^= crc_braid_table[k][(word2 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
753
crc3 ^= crc_braid_table[k][(word3 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
755
crc4 ^= crc_braid_table[k][(word4 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
757
crc5 ^= crc_braid_table[k][(word5 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
868
for (k = 1; k < W; k++) {
sys/lib/libz/crc32.c
869
crc0 ^= crc_braid_big_table[k][(word0 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
871
crc1 ^= crc_braid_big_table[k][(word1 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
873
crc2 ^= crc_braid_big_table[k][(word2 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
875
crc3 ^= crc_braid_big_table[k][(word3 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
877
crc4 ^= crc_braid_big_table[k][(word4 >> (k << 3)) & 0xff];
sys/lib/libz/crc32.c
879
crc5 ^= crc_braid_big_table[k][(word5 >> (k << 3)) & 0xff];
sys/lib/libz/trees.c
507
local void pqdownheap(deflate_state *s, ct_data *tree, int k) {
sys/lib/libz/trees.c
508
int v = s->heap[k];
sys/lib/libz/trees.c
509
int j = k << 1; /* left son of k */
sys/lib/libz/trees.c
520
s->heap[k] = s->heap[j]; k = j;
sys/lib/libz/trees.c
525
s->heap[k] = v;
sys/net/art.c
1001
k <<= 1;
sys/net/art.c
1002
if (k < at->at_minfringe)
sys/net/art.c
1007
ahep = &heap[k];
sys/net/art.c
1019
if (k % 2)
sys/net/art.c
1021
k++;
sys/net/art.c
1025
ahe = SMR_PTR_GET_LOCKED(&heap[k]);
sys/net/art.c
1029
if (k % 2)
sys/net/art.c
1031
k++;
sys/net/art.c
1034
k >>= 1;
sys/net/art.c
1035
SMR_PTR_SET_LOCKED(&heap[k], nahe);
sys/net/art.c
1038
if (k != i)
sys/net/art.c
217
uint32_t k;
sys/net/art.c
241
k = (addr[0] & ((1 << (8 - boff)) - 1)) << (bend - 8);
sys/net/art.c
242
k |= addr[1] << (bend - 16);
sys/net/art.c
243
k |= addr[2] << (bend - 24);
sys/net/art.c
244
k |= addr[3] >> (32 - bend);
sys/net/art.c
246
k = (addr[0] & ((1 << (8 - boff)) - 1)) << (bend - 8);
sys/net/art.c
247
k |= addr[1] << (bend - 16);
sys/net/art.c
248
k |= addr[2] >> (24 - bend);
sys/net/art.c
250
k = (addr[0] & ((1 << (8 - boff)) - 1)) << (bend - 8);
sys/net/art.c
251
k |= addr[1] >> (16 - bend);
sys/net/art.c
253
k = (addr[0] >> (8 - bend)) & ((1 << bits) - 1);
sys/net/art.c
259
return ((k >> (bits - plen)) + (1 << plen));
sys/net/art.c
994
unsigned int k = i;
sys/net/bpf.c
1946
bpf_mbuf_ldw(const void *m0, u_int32_t k, int *err)
sys/net/bpf.c
1950
if (bpf_mbuf_copy(m0, k, &v, sizeof(v)) != 0) {
sys/net/bpf.c
1960
bpf_mbuf_ldh(const void *m0, u_int32_t k, int *err)
sys/net/bpf.c
1964
if (bpf_mbuf_copy(m0, k, &v, sizeof(v)) != 0) {
sys/net/bpf.c
1974
bpf_mbuf_ldb(const void *m0, u_int32_t k, int *err)
sys/net/bpf.c
1979
while (k >= m->m_len) {
sys/net/bpf.c
1980
k -= m->m_len;
sys/net/bpf.c
1988
v = m->m_data[k];
sys/net/bpf.h
285
u_int32_t k;
sys/net/bpf.h
308
#define BPF_STMT(code, k) { (u_int16_t)(code), 0, 0, k }
sys/net/bpf.h
309
#define BPF_JUMP(code, k, jt, jf) { (u_int16_t)(code), jt, jf, k }
sys/net/bpf_filter.c
105
bpf_mem_ldh(const void *mem, u_int32_t k, int *err)
sys/net/bpf_filter.c
109
if (bpf_memcpy(&v, mem, k, sizeof(v)) == -1) {
sys/net/bpf_filter.c
119
bpf_mem_ldb(const void *mem, u_int32_t k, int *err)
sys/net/bpf_filter.c
123
if (bpf_memcpy(&v, mem, k, sizeof(v)) == -1) {
sys/net/bpf_filter.c
154
u_int32_t k;
sys/net/bpf_filter.c
179
return (u_int)pc->k;
sys/net/bpf_filter.c
185
A = ops->ldw(pkt, pc->k, &err);
sys/net/bpf_filter.c
191
A = ops->ldh(pkt, pc->k, &err);
sys/net/bpf_filter.c
197
A = ops->ldb(pkt, pc->k, &err);
sys/net/bpf_filter.c
215
k = X + pc->k;
sys/net/bpf_filter.c
216
A = ops->ldw(pkt, k, &err);
sys/net/bpf_filter.c
222
k = X + pc->k;
sys/net/bpf_filter.c
223
A = ops->ldh(pkt, k, &err);
sys/net/bpf_filter.c
229
k = X + pc->k;
sys/net/bpf_filter.c
230
A = ops->ldb(pkt, k, &err);
sys/net/bpf_filter.c
236
X = ops->ldb(pkt, pc->k, &err);
sys/net/bpf_filter.c
244
A = pc->k;
sys/net/bpf_filter.c
248
X = pc->k;
sys/net/bpf_filter.c
252
A = mem[pc->k];
sys/net/bpf_filter.c
256
X = mem[pc->k];
sys/net/bpf_filter.c
260
mem[pc->k] = A;
sys/net/bpf_filter.c
264
mem[pc->k] = X;
sys/net/bpf_filter.c
268
pc += pc->k;
sys/net/bpf_filter.c
272
pc += (A > pc->k) ? pc->jt : pc->jf;
sys/net/bpf_filter.c
276
pc += (A >= pc->k) ? pc->jt : pc->jf;
sys/net/bpf_filter.c
280
pc += (A == pc->k) ? pc->jt : pc->jf;
sys/net/bpf_filter.c
284
pc += (A & pc->k) ? pc->jt : pc->jf;
sys/net/bpf_filter.c
348
A += pc->k;
sys/net/bpf_filter.c
352
A -= pc->k;
sys/net/bpf_filter.c
356
A *= pc->k;
sys/net/bpf_filter.c
360
A /= pc->k;
sys/net/bpf_filter.c
364
A %= pc->k;
sys/net/bpf_filter.c
368
A &= pc->k;
sys/net/bpf_filter.c
372
A |= pc->k;
sys/net/bpf_filter.c
376
A ^= pc->k;
sys/net/bpf_filter.c
380
A <<= pc->k;
sys/net/bpf_filter.c
384
A >>= pc->k;
sys/net/bpf_filter.c
439
if (p->k >= bpf_maxbufsize)
sys/net/bpf_filter.c
443
if (p->k >= BPF_MEMWORDS)
sys/net/bpf_filter.c
455
if (p->k >= BPF_MEMWORDS)
sys/net/bpf_filter.c
475
if (BPF_SRC(p->code) == BPF_K && p->k == 0)
sys/net/bpf_filter.c
490
if (from + p->k < from || from + p->k >= len)
sys/net/bpf_filter.c
91
bpf_mem_ldw(const void *mem, u_int32_t k, int *err)
sys/net/bpf_filter.c
95
if (bpf_memcpy(&v, mem, k, sizeof(v)) == -1) {
sys/net/bridgectl.c
491
int k, error = 0;
sys/net/bridgectl.c
494
for (k = 0; k < BRIDGE_RTABLE_SIZE; k++) {
sys/net/bridgectl.c
495
LIST_FOREACH(n, &sc->sc_rts[k], brt_next)
sys/net/bridgectl.c
511
for (k = 0; k < BRIDGE_RTABLE_SIZE; k++) {
sys/net/bridgectl.c
512
LIST_FOREACH(n, &sc->sc_rts[k], brt_next) {
sys/net/if_bpe.c
725
struct bpe_key k = { .k_if = ifp0->if_index, .k_isid = isid };
sys/net/if_bpe.c
729
sc = (struct bpe_softc *)RBT_FIND(bpe_tree, &bpe_interfaces, &k);
sys/net/pf.c
281
#define BOUND_IFACE(r, k) \
sys/net/pf.c
282
((r)->rule_flag & PFRULE_IFBOUND) ? (k) : pfi_all
sys/net/pf.c
858
struct pf_src_node k;
sys/net/pf.c
861
k.af = af;
sys/net/pf.c
862
k.type = type;
sys/net/pf.c
863
pf_addrcpy(&k.addr, src, af);
sys/net/pf.c
864
k.rule.ptr = rule;
sys/net/pf.c
866
*sn = RB_FIND(pf_src_tree, &tree_src_tracking, &k);
sys/net/pf_if.c
730
int i, j, k;
sys/net/pf_if.c
774
for (k = 0; k < 2; k++) {
sys/net/pf_if.c
775
pfs->pcounters[i][j][k] +=
sys/net/pf_if.c
776
p->pfik_packets[i][j][k];
sys/net/pf_if.c
778
p->pfik_bytes[i][j][k];
sys/net/pf_lb.c
260
struct pf_src_node k;
sys/net/pf_lb.c
263
k.af = af;
sys/net/pf_lb.c
264
k.type = type;
sys/net/pf_lb.c
265
pf_addrcpy(&k.addr, saddr, af);
sys/net/pf_lb.c
266
k.rule.ptr = r;
sys/net/pf_lb.c
268
sns[type] = RB_FIND(pf_src_tree, &tree_src_tracking, &k);
sys/net/pf_lb.c
293
pf_print_host(&k.addr, 0, af);
sys/net/pf_lb.c
319
pf_print_host(&k.addr, 0, af);
sys/net/toeplitz.c
200
uint8_t *k = key;
sys/net/toeplitz.c
207
k[i + 0] = skey >> 8;
sys/net/toeplitz.c
208
k[i + 1] = skey;
sys/net80211/ieee80211_crypto.c
109
struct ieee80211_key *k = &ic->ic_nw_keys[i];
sys/net80211/ieee80211_crypto.c
110
if (k->k_cipher != IEEE80211_CIPHER_NONE)
sys/net80211/ieee80211_crypto.c
111
(*ic->ic_delete_key)(ic, NULL, k);
sys/net80211/ieee80211_crypto.c
112
explicit_bzero(k, sizeof(*k));
sys/net80211/ieee80211_crypto.c
140
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto.c
144
switch (k->k_cipher) {
sys/net80211/ieee80211_crypto.c
147
error = ieee80211_wep_set_key(ic, k);
sys/net80211/ieee80211_crypto.c
150
error = ieee80211_tkip_set_key(ic, k);
sys/net80211/ieee80211_crypto.c
153
error = ieee80211_ccmp_set_key(ic, k);
sys/net80211/ieee80211_crypto.c
156
error = ieee80211_bip_set_key(ic, k);
sys/net80211/ieee80211_crypto.c
164
k->k_flags |= IEEE80211_KEY_SWCRYPTO;
sys/net80211/ieee80211_crypto.c
171
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto.c
173
switch (k->k_cipher) {
sys/net80211/ieee80211_crypto.c
176
ieee80211_wep_delete_key(ic, k);
sys/net80211/ieee80211_crypto.c
179
ieee80211_tkip_delete_key(ic, k);
sys/net80211/ieee80211_crypto.c
182
ieee80211_ccmp_delete_key(ic, k);
sys/net80211/ieee80211_crypto.c
185
ieee80211_bip_delete_key(ic, k);
sys/net80211/ieee80211_crypto.c
191
explicit_bzero(k, sizeof(*k));
sys/net80211/ieee80211_crypto.c
218
struct ieee80211_key *k = NULL;
sys/net80211/ieee80211_crypto.c
228
k = &ni->ni_pairwise_key;
sys/net80211/ieee80211_crypto.c
239
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_crypto.c
252
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_crypto.c
255
return k;
sys/net80211/ieee80211_crypto.c
260
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto.c
262
if ((k->k_flags & IEEE80211_KEY_SWCRYPTO) == 0)
sys/net80211/ieee80211_crypto.c
264
__func__, k->k_id, k->k_cipher, k->k_flags);
sys/net80211/ieee80211_crypto.c
266
switch (k->k_cipher) {
sys/net80211/ieee80211_crypto.c
269
m0 = ieee80211_wep_encrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
272
m0 = ieee80211_tkip_encrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
275
m0 = ieee80211_ccmp_encrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
278
m0 = ieee80211_bip_encap(ic, m0, k);
sys/net80211/ieee80211_crypto.c
282
panic("invalid key cipher 0x%x", k->k_cipher);
sys/net80211/ieee80211_crypto.c
291
struct ieee80211_key *k;
sys/net80211/ieee80211_crypto.c
294
k = ieee80211_get_rxkey(ic, m0, ni);
sys/net80211/ieee80211_crypto.c
295
if (k == NULL || (k->k_flags & IEEE80211_KEY_SWCRYPTO) == 0) {
sys/net80211/ieee80211_crypto.c
300
switch (k->k_cipher) {
sys/net80211/ieee80211_crypto.c
303
m0 = ieee80211_wep_decrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
306
m0 = ieee80211_tkip_decrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
309
m0 = ieee80211_ccmp_decrypt(ic, m0, k);
sys/net80211/ieee80211_crypto.c
312
m0 = ieee80211_bip_decap(ic, m0, k);
sys/net80211/ieee80211_crypto_bip.c
130
LE_WRITE_2(&mmie[2], k->k_id);
sys/net80211/ieee80211_crypto_bip.c
131
LE_WRITE_6(&mmie[4], k->k_tsc);
sys/net80211/ieee80211_crypto_bip.c
142
k->k_tsc++;
sys/net80211/ieee80211_crypto_bip.c
153
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_bip.c
155
struct ieee80211_bip_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_bip.c
174
if (ipn <= k->k_mgmt_rsc) {
sys/net80211/ieee80211_crypto_bip.c
216
k->k_mgmt_rsc = ipn;
sys/net80211/ieee80211_crypto_bip.c
56
ieee80211_bip_set_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_bip.c
63
AES_CMAC_SetKey(&ctx->cmac, k->k_key);
sys/net80211/ieee80211_crypto_bip.c
64
k->k_priv = ctx;
sys/net80211/ieee80211_crypto_bip.c
69
ieee80211_bip_delete_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_bip.c
71
if (k->k_priv != NULL) {
sys/net80211/ieee80211_crypto_bip.c
72
explicit_bzero(k->k_priv, sizeof(struct ieee80211_bip_ctx));
sys/net80211/ieee80211_crypto_bip.c
73
free(k->k_priv, M_DEVBUF, sizeof(struct ieee80211_bip_ctx));
sys/net80211/ieee80211_crypto_bip.c
75
k->k_priv = NULL;
sys/net80211/ieee80211_crypto_bip.c
88
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_bip.c
90
struct ieee80211_bip_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_ccmp.c
167
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_ccmp.c
169
struct ieee80211_ccmp_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_ccmp.c
199
k->k_tsc++; /* increment the 48-bit PN */
sys/net80211/ieee80211_crypto_ccmp.c
203
ivp[0] = k->k_tsc; /* PN0 */
sys/net80211/ieee80211_crypto_ccmp.c
204
ivp[1] = k->k_tsc >> 8; /* PN1 */
sys/net80211/ieee80211_crypto_ccmp.c
206
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; /* KeyID | ExtIV */
sys/net80211/ieee80211_crypto_ccmp.c
207
ivp[4] = k->k_tsc >> 16; /* PN2 */
sys/net80211/ieee80211_crypto_ccmp.c
208
ivp[5] = k->k_tsc >> 24; /* PN3 */
sys/net80211/ieee80211_crypto_ccmp.c
209
ivp[6] = k->k_tsc >> 32; /* PN4 */
sys/net80211/ieee80211_crypto_ccmp.c
210
ivp[7] = k->k_tsc >> 40; /* PN5 */
sys/net80211/ieee80211_crypto_ccmp.c
213
ieee80211_ccmp_phase1(&ctx->aesctx, wh, k->k_tsc,
sys/net80211/ieee80211_crypto_ccmp.c
305
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_ccmp.c
327
*prsc = &k->k_rsc[tid];
sys/net80211/ieee80211_crypto_ccmp.c
329
*prsc = &k->k_mgmt_rsc;
sys/net80211/ieee80211_crypto_ccmp.c
344
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_ccmp.c
346
struct ieee80211_ccmp_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_ccmp.c
370
if (ieee80211_ccmp_get_pn(&pn, &prsc, m0, k) != 0) {
sys/net80211/ieee80211_crypto_ccmp.c
54
ieee80211_ccmp_set_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_ccmp.c
61
AES_Setkey(&ctx->aesctx, k->k_key, 16);
sys/net80211/ieee80211_crypto_ccmp.c
62
k->k_priv = ctx;
sys/net80211/ieee80211_crypto_ccmp.c
67
ieee80211_ccmp_delete_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_ccmp.c
69
if (k->k_priv != NULL) {
sys/net80211/ieee80211_crypto_ccmp.c
70
explicit_bzero(k->k_priv, sizeof(struct ieee80211_ccmp_ctx));
sys/net80211/ieee80211_crypto_ccmp.c
71
free(k->k_priv, M_DEVBUF, sizeof(struct ieee80211_ccmp_ctx));
sys/net80211/ieee80211_crypto_ccmp.c
73
k->k_priv = NULL;
sys/net80211/ieee80211_crypto_tkip.c
101
k->k_priv = NULL;
sys/net80211/ieee80211_crypto_tkip.c
186
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_tkip.c
188
struct ieee80211_tkip_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_tkip.c
216
k->k_tsc++; /* increment the 48-bit TSC */
sys/net80211/ieee80211_crypto_tkip.c
220
ivp[0] = k->k_tsc >> 8; /* TSC1 */
sys/net80211/ieee80211_crypto_tkip.c
223
ivp[2] = k->k_tsc; /* TSC0 */
sys/net80211/ieee80211_crypto_tkip.c
224
ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; /* KeyID | ExtIV */
sys/net80211/ieee80211_crypto_tkip.c
225
ivp[4] = k->k_tsc >> 16; /* TSC2 */
sys/net80211/ieee80211_crypto_tkip.c
226
ivp[5] = k->k_tsc >> 24; /* TSC3 */
sys/net80211/ieee80211_crypto_tkip.c
227
ivp[6] = k->k_tsc >> 32; /* TSC4 */
sys/net80211/ieee80211_crypto_tkip.c
228
ivp[7] = k->k_tsc >> 40; /* TSC5 */
sys/net80211/ieee80211_crypto_tkip.c
231
if (!ctx->txttak_ok || (k->k_tsc & 0xffff) == 0) {
sys/net80211/ieee80211_crypto_tkip.c
232
Phase1(ctx->txttak, k->k_key, wh->i_addr2, k->k_tsc >> 16);
sys/net80211/ieee80211_crypto_tkip.c
235
Phase2((u_int8_t *)wepseed, k->k_key, ctx->txttak, k->k_tsc & 0xffff);
sys/net80211/ieee80211_crypto_tkip.c
318
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_tkip.c
339
*prsc = &k->k_rsc[tid];
sys/net80211/ieee80211_crypto_tkip.c
354
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_tkip.c
356
struct ieee80211_tkip_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_tkip.c
380
if (ieee80211_tkip_get_tsc(&tsc, &prsc, m0, k) != 0) {
sys/net80211/ieee80211_crypto_tkip.c
414
Phase1(ctx->rxttak, k->k_key, wh->i_addr2, tsc >> 16);
sys/net80211/ieee80211_crypto_tkip.c
416
Phase2((u_int8_t *)wepseed, k->k_key, ctx->rxttak, tsc & 0xffff);
sys/net80211/ieee80211_crypto_tkip.c
69
ieee80211_tkip_set_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_tkip.c
82
ctx->txmic = &k->k_key[16];
sys/net80211/ieee80211_crypto_tkip.c
83
ctx->rxmic = &k->k_key[24];
sys/net80211/ieee80211_crypto_tkip.c
87
ctx->rxmic = &k->k_key[16];
sys/net80211/ieee80211_crypto_tkip.c
88
ctx->txmic = &k->k_key[24];
sys/net80211/ieee80211_crypto_tkip.c
90
k->k_priv = ctx;
sys/net80211/ieee80211_crypto_tkip.c
95
ieee80211_tkip_delete_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_tkip.c
97
if (k->k_priv != NULL) {
sys/net80211/ieee80211_crypto_tkip.c
98
explicit_bzero(k->k_priv, sizeof(struct ieee80211_tkip_ctx));
sys/net80211/ieee80211_crypto_tkip.c
99
free(k->k_priv, M_DEVBUF, sizeof(struct ieee80211_tkip_ctx));
sys/net80211/ieee80211_crypto_wep.c
122
ivp[3] = k->k_id << 6;
sys/net80211/ieee80211_crypto_wep.c
126
memcpy(wepseed + IEEE80211_WEP_IVLEN, k->k_key, k->k_len);
sys/net80211/ieee80211_crypto_wep.c
127
rc4_keysetup(&ctx->rc4, wepseed, IEEE80211_WEP_IVLEN + k->k_len);
sys/net80211/ieee80211_crypto_wep.c
201
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_wep.c
203
struct ieee80211_wep_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_crypto_wep.c
222
memcpy(wepseed + IEEE80211_WEP_IVLEN, k->k_key, k->k_len);
sys/net80211/ieee80211_crypto_wep.c
223
rc4_keysetup(&ctx->rc4, wepseed, IEEE80211_WEP_IVLEN + k->k_len);
sys/net80211/ieee80211_crypto_wep.c
55
ieee80211_wep_set_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_wep.c
62
k->k_priv = ctx;
sys/net80211/ieee80211_crypto_wep.c
67
ieee80211_wep_delete_key(struct ieee80211com *ic, struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_wep.c
69
if (k->k_priv != NULL) {
sys/net80211/ieee80211_crypto_wep.c
70
explicit_bzero(k->k_priv, sizeof(struct ieee80211_wep_ctx));
sys/net80211/ieee80211_crypto_wep.c
71
free(k->k_priv, M_DEVBUF, sizeof(struct ieee80211_wep_ctx));
sys/net80211/ieee80211_crypto_wep.c
73
k->k_priv = NULL;
sys/net80211/ieee80211_crypto_wep.c
82
struct ieee80211_key *k)
sys/net80211/ieee80211_crypto_wep.c
84
struct ieee80211_wep_ctx *ctx = k->k_priv;
sys/net80211/ieee80211_input.c
162
struct ieee80211_key *k;
sys/net80211/ieee80211_input.c
167
k = ieee80211_get_rxkey(ic, m, ni);
sys/net80211/ieee80211_input.c
168
if (k == NULL)
sys/net80211/ieee80211_input.c
183
switch (k->k_cipher) {
sys/net80211/ieee80211_input.c
193
if (ieee80211_ccmp_get_pn(&pn, &prsc, m, k) != 0) {
sys/net80211/ieee80211_input.c
225
if (ieee80211_tkip_get_tsc(&pn, &prsc, m, k) != 0)
sys/net80211/ieee80211_ioctl.c
187
struct ieee80211_key *k;
sys/net80211/ieee80211_ioctl.c
191
k = &ic->ic_nw_keys[i];
sys/net80211/ieee80211_ioctl.c
192
if (k->k_cipher != IEEE80211_CIPHER_NONE)
sys/net80211/ieee80211_ioctl.c
193
(*ic->ic_delete_key)(ic, NULL, k);
sys/net80211/ieee80211_ioctl.c
194
explicit_bzero(k, sizeof(*k));
sys/net80211/ieee80211_ioctl.c
216
struct ieee80211_key *k;
sys/net80211/ieee80211_ioctl.c
239
k = &ic->ic_nw_keys[i];
sys/net80211/ieee80211_ioctl.c
240
if (k->k_cipher != IEEE80211_CIPHER_NONE)
sys/net80211/ieee80211_ioctl.c
241
(*ic->ic_delete_key)(ic, NULL, k);
sys/net80211/ieee80211_ioctl.c
242
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_ioctl.c
244
k->k_cipher = IEEE80211_CIPHER_WEP40;
sys/net80211/ieee80211_ioctl.c
246
k->k_cipher = IEEE80211_CIPHER_WEP104;
sys/net80211/ieee80211_ioctl.c
247
k->k_len = ieee80211_cipher_keylen(k->k_cipher);
sys/net80211/ieee80211_ioctl.c
248
k->k_flags = IEEE80211_KEY_GROUP | IEEE80211_KEY_TX;
sys/net80211/ieee80211_ioctl.c
249
error = copyin(nwkey->i_key[i].i_keydat, k->k_key, k->k_len);
sys/net80211/ieee80211_ioctl.c
252
error = (*ic->ic_set_key)(ic, NULL, k);
sys/net80211/ieee80211_node.c
1040
struct ieee80211_key *k;
sys/net80211/ieee80211_node.c
1059
k = &ic->ic_nw_keys[ic->ic_def_txkey];
sys/net80211/ieee80211_node.c
1060
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_node.c
1061
k->k_id = ic->ic_def_txkey;
sys/net80211/ieee80211_node.c
1062
k->k_cipher = ni->ni_rsngroupcipher;
sys/net80211/ieee80211_node.c
1063
k->k_flags = IEEE80211_KEY_GROUP | IEEE80211_KEY_TX;
sys/net80211/ieee80211_node.c
1064
k->k_len = ieee80211_cipher_keylen(k->k_cipher);
sys/net80211/ieee80211_node.c
1065
arc4random_buf(k->k_key, k->k_len);
sys/net80211/ieee80211_node.c
1066
(*ic->ic_set_key)(ic, ni, k); /* XXX */
sys/net80211/ieee80211_node.c
1070
k = &ic->ic_nw_keys[ic->ic_igtk_kid];
sys/net80211/ieee80211_node.c
1071
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_node.c
1072
k->k_id = ic->ic_igtk_kid;
sys/net80211/ieee80211_node.c
1073
k->k_cipher = ni->ni_rsngroupmgmtcipher;
sys/net80211/ieee80211_node.c
1074
k->k_flags = IEEE80211_KEY_IGTK | IEEE80211_KEY_TX;
sys/net80211/ieee80211_node.c
1075
k->k_len = 16;
sys/net80211/ieee80211_node.c
1076
arc4random_buf(k->k_key, k->k_len);
sys/net80211/ieee80211_node.c
1077
(*ic->ic_set_key)(ic, ni, k); /* XXX */
sys/net80211/ieee80211_node.c
235
struct ieee80211_key *k;
sys/net80211/ieee80211_node.c
255
k = &ess->nw_keys[i];
sys/net80211/ieee80211_node.c
256
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_node.c
258
k->k_cipher = IEEE80211_CIPHER_WEP40;
sys/net80211/ieee80211_node.c
260
k->k_cipher = IEEE80211_CIPHER_WEP104;
sys/net80211/ieee80211_node.c
261
k->k_len = ieee80211_cipher_keylen(k->k_cipher);
sys/net80211/ieee80211_node.c
262
k->k_flags = IEEE80211_KEY_GROUP | IEEE80211_KEY_TX;
sys/net80211/ieee80211_node.c
263
error = copyin(nwkey->i_key[i].i_keydat, k->k_key, k->k_len);
sys/net80211/ieee80211_node.c
689
struct ieee80211_key *k;
sys/net80211/ieee80211_node.c
693
k = &ic->ic_nw_keys[i];
sys/net80211/ieee80211_node.c
694
if (k->k_cipher != IEEE80211_CIPHER_NONE)
sys/net80211/ieee80211_node.c
695
(*ic->ic_delete_key)(ic, NULL, k);
sys/net80211/ieee80211_node.c
698
if (k->k_cipher != IEEE80211_CIPHER_NONE)
sys/net80211/ieee80211_node.c
699
(*ic->ic_set_key)(ic, NULL, k);
sys/net80211/ieee80211_pae_input.c
1038
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_input.c
1040
if (ieee80211_must_update_group_key(k, gtk, keylen)) {
sys/net80211/ieee80211_pae_input.c
1041
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
1042
k->k_id = kid; /* 0-3 */
sys/net80211/ieee80211_pae_input.c
1043
k->k_cipher = ni->ni_rsngroupcipher;
sys/net80211/ieee80211_pae_input.c
1044
k->k_flags = IEEE80211_KEY_GROUP;
sys/net80211/ieee80211_pae_input.c
1046
k->k_flags |= IEEE80211_KEY_TX;
sys/net80211/ieee80211_pae_input.c
1047
k->k_rsc[0] = LE_READ_6(key->rsc);
sys/net80211/ieee80211_pae_input.c
1048
k->k_len = keylen;
sys/net80211/ieee80211_pae_input.c
1049
memcpy(k->k_key, gtk, k->k_len);
sys/net80211/ieee80211_pae_input.c
1051
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
1084
(void)ieee80211_send_group_msg2(ic, ni, k);
sys/net80211/ieee80211_pae_input.c
351
ieee80211_must_update_group_key(struct ieee80211_key *k, const uint8_t *gtk,
sys/net80211/ieee80211_pae_input.c
354
return (k->k_cipher == IEEE80211_CIPHER_NONE || k->k_len != len ||
sys/net80211/ieee80211_pae_input.c
355
memcmp(k->k_key, gtk, len) != 0);
sys/net80211/ieee80211_pae_input.c
366
struct ieee80211_key *k;
sys/net80211/ieee80211_pae_input.c
562
k = &ni->ni_pairwise_key;
sys/net80211/ieee80211_pae_input.c
563
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
564
k->k_cipher = ni->ni_rsncipher;
sys/net80211/ieee80211_pae_input.c
565
k->k_rsc[0] = prsc;
sys/net80211/ieee80211_pae_input.c
566
k->k_len = keylen;
sys/net80211/ieee80211_pae_input.c
567
memcpy(k->k_key, ni->ni_ptk.tk, k->k_len);
sys/net80211/ieee80211_pae_input.c
569
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
597
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_input.c
598
if (ieee80211_must_update_group_key(k, >k[8], keylen)) {
sys/net80211/ieee80211_pae_input.c
599
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
600
k->k_id = kid; /* 0-3 */
sys/net80211/ieee80211_pae_input.c
601
k->k_cipher = ni->ni_rsngroupcipher;
sys/net80211/ieee80211_pae_input.c
602
k->k_flags = IEEE80211_KEY_GROUP;
sys/net80211/ieee80211_pae_input.c
604
k->k_flags |= IEEE80211_KEY_TX;
sys/net80211/ieee80211_pae_input.c
605
k->k_rsc[0] = LE_READ_6(key->rsc);
sys/net80211/ieee80211_pae_input.c
606
k->k_len = keylen;
sys/net80211/ieee80211_pae_input.c
607
memcpy(k->k_key, >k[8], k->k_len);
sys/net80211/ieee80211_pae_input.c
609
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
636
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_input.c
637
if (ieee80211_must_update_group_key(k, &igtk[14], 16)) {
sys/net80211/ieee80211_pae_input.c
638
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
639
k->k_id = kid; /* either 4 or 5 */
sys/net80211/ieee80211_pae_input.c
640
k->k_cipher = ni->ni_rsngroupmgmtcipher;
sys/net80211/ieee80211_pae_input.c
641
k->k_flags = IEEE80211_KEY_IGTK;
sys/net80211/ieee80211_pae_input.c
642
k->k_mgmt_rsc = LE_READ_6(&igtk[8]); /* IPN */
sys/net80211/ieee80211_pae_input.c
643
k->k_len = 16;
sys/net80211/ieee80211_pae_input.c
644
memcpy(k->k_key, &igtk[14], k->k_len);
sys/net80211/ieee80211_pae_input.c
646
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
723
struct ieee80211_key *k;
sys/net80211/ieee80211_pae_input.c
726
k = &ni->ni_pairwise_key;
sys/net80211/ieee80211_pae_input.c
727
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
728
k->k_cipher = ni->ni_rsncipher;
sys/net80211/ieee80211_pae_input.c
729
k->k_len = ieee80211_cipher_keylen(k->k_cipher);
sys/net80211/ieee80211_pae_input.c
730
memcpy(k->k_key, ni->ni_ptk.tk, k->k_len);
sys/net80211/ieee80211_pae_input.c
732
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
818
struct ieee80211_key *k;
sys/net80211/ieee80211_pae_input.c
894
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_input.c
895
if (ieee80211_must_update_group_key(k, >k[8], keylen)) {
sys/net80211/ieee80211_pae_input.c
896
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
897
k->k_id = kid; /* 0-3 */
sys/net80211/ieee80211_pae_input.c
898
k->k_cipher = ni->ni_rsngroupcipher;
sys/net80211/ieee80211_pae_input.c
899
k->k_flags = IEEE80211_KEY_GROUP;
sys/net80211/ieee80211_pae_input.c
901
k->k_flags |= IEEE80211_KEY_TX;
sys/net80211/ieee80211_pae_input.c
902
k->k_rsc[0] = LE_READ_6(key->rsc);
sys/net80211/ieee80211_pae_input.c
903
k->k_len = keylen;
sys/net80211/ieee80211_pae_input.c
904
memcpy(k->k_key, >k[8], k->k_len);
sys/net80211/ieee80211_pae_input.c
906
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
928
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_input.c
929
if (ieee80211_must_update_group_key(k, &igtk[14], 16)) {
sys/net80211/ieee80211_pae_input.c
930
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_pae_input.c
931
k->k_id = kid; /* either 4 or 5 */
sys/net80211/ieee80211_pae_input.c
932
k->k_cipher = ni->ni_rsngroupmgmtcipher;
sys/net80211/ieee80211_pae_input.c
933
k->k_flags = IEEE80211_KEY_IGTK;
sys/net80211/ieee80211_pae_input.c
934
k->k_mgmt_rsc = LE_READ_6(&igtk[8]); /* IPN */
sys/net80211/ieee80211_pae_input.c
935
k->k_len = 16;
sys/net80211/ieee80211_pae_input.c
936
memcpy(k->k_key, &igtk[14], k->k_len);
sys/net80211/ieee80211_pae_input.c
938
switch ((*ic->ic_set_key)(ic, ni, k)) {
sys/net80211/ieee80211_pae_input.c
989
struct ieee80211_key *k;
sys/net80211/ieee80211_pae_output.c
174
const struct ieee80211_key *k)
sys/net80211/ieee80211_pae_output.c
176
KASSERT(k->k_flags & IEEE80211_KEY_GROUP);
sys/net80211/ieee80211_pae_output.c
179
*frm++ = 6 + k->k_len;
sys/net80211/ieee80211_pae_output.c
182
*frm = k->k_id & 3;
sys/net80211/ieee80211_pae_output.c
191
memcpy(frm, k->k_key, k->k_len);
sys/net80211/ieee80211_pae_output.c
192
return frm + k->k_len;
sys/net80211/ieee80211_pae_output.c
213
ieee80211_add_igtk_kde(u_int8_t *frm, const struct ieee80211_key *k)
sys/net80211/ieee80211_pae_output.c
215
KASSERT(k->k_flags & IEEE80211_KEY_IGTK);
sys/net80211/ieee80211_pae_output.c
221
LE_WRITE_2(frm, k->k_id); frm += 2;
sys/net80211/ieee80211_pae_output.c
222
LE_WRITE_6(frm, k->k_tsc); frm += 6; /* IPN */
sys/net80211/ieee80211_pae_output.c
223
memcpy(frm, k->k_key, 16);
sys/net80211/ieee80211_pae_output.c
366
struct ieee80211_key *k = NULL;
sys/net80211/ieee80211_pae_output.c
379
k = &ic->ic_nw_keys[ic->ic_def_txkey];
sys/net80211/ieee80211_pae_output.c
381
2 + IEEE80211_RSNIE_MAXLEN + 2 + 6 + k->k_len + 15 +
sys/net80211/ieee80211_pae_output.c
411
frm = ieee80211_add_gtk_kde(frm, ni, k);
sys/net80211/ieee80211_pae_output.c
412
LE_WRITE_6(key->rsc, k->k_tsc);
sys/net80211/ieee80211_pae_output.c
489
const struct ieee80211_key *k;
sys/net80211/ieee80211_pae_output.c
506
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_pae_output.c
510
k->k_len : 2 + 6 + k->k_len) +
sys/net80211/ieee80211_pae_output.c
527
BE_WRITE_2(key->keylen, k->k_len);
sys/net80211/ieee80211_pae_output.c
528
memcpy(frm, k->k_key, k->k_len);
sys/net80211/ieee80211_pae_output.c
529
frm += k->k_len;
sys/net80211/ieee80211_pae_output.c
530
info |= (k->k_id & 0x3) << EAPOL_KEY_WPA_KID_SHIFT;
sys/net80211/ieee80211_pae_output.c
534
frm = ieee80211_add_gtk_kde(frm, ni, k);
sys/net80211/ieee80211_pae_output.c
545
LE_WRITE_6(key->rsc, k->k_tsc);
sys/net80211/ieee80211_pae_output.c
566
const struct ieee80211_key *k)
sys/net80211/ieee80211_pae_output.c
585
BE_WRITE_2(key->keylen, k->k_len);
sys/net80211/ieee80211_pae_output.c
586
info |= (k->k_id & 3) << EAPOL_KEY_WPA_KID_SHIFT;
sys/net80211/ieee80211_proto.c
436
struct ieee80211_key *k;
sys/net80211/ieee80211_proto.c
442
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_proto.c
443
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_proto.c
444
k->k_id = kid;
sys/net80211/ieee80211_proto.c
445
k->k_cipher = ic->ic_bss->ni_rsngroupcipher;
sys/net80211/ieee80211_proto.c
446
k->k_flags = IEEE80211_KEY_GROUP | IEEE80211_KEY_TX;
sys/net80211/ieee80211_proto.c
447
k->k_len = ieee80211_cipher_keylen(k->k_cipher);
sys/net80211/ieee80211_proto.c
448
arc4random_buf(k->k_key, k->k_len);
sys/net80211/ieee80211_proto.c
453
k = &ic->ic_nw_keys[kid];
sys/net80211/ieee80211_proto.c
454
memset(k, 0, sizeof(*k));
sys/net80211/ieee80211_proto.c
455
k->k_id = kid;
sys/net80211/ieee80211_proto.c
456
k->k_cipher = ic->ic_bss->ni_rsngroupmgmtcipher;
sys/net80211/ieee80211_proto.c
457
k->k_flags = IEEE80211_KEY_IGTK | IEEE80211_KEY_TX;
sys/net80211/ieee80211_proto.c
458
k->k_len = 16;
sys/net80211/ieee80211_proto.c
459
arc4random_buf(k->k_key, k->k_len);
sys/sys/systm.h
130
#define SCARG(p, k) ((p)->k.be.datum) /* get arg from args pointer */
sys/sys/systm.h
132
#define SCARG(p, k) ((p)->k.le.datum) /* get arg from args pointer */
sys/uvm/uvm_amap.c
533
int i, j, k, n, srcslot;
sys/uvm/uvm_amap.c
650
for (k = 0; k < n; i++, j++, k++) {
usr.bin/awk/b.c
1492
int i, j, k;
usr.bin/awk/b.c
1505
if ((k = f->re[p[i]].ltype) != FINAL) {
usr.bin/awk/b.c
1506
if ((k == CHAR && c == ptoi(f->re[p[i]].lval.np))
usr.bin/awk/b.c
1507
|| (k == DOT && c != 0 && c != HAT)
usr.bin/awk/b.c
1508
|| (k == ALL && c != 0)
usr.bin/awk/b.c
1509
|| (k == EMPTYRE && c != 0)
usr.bin/awk/b.c
1510
|| (k == CCL && member(c, (int *) f->re[p[i]].lval.rp))
usr.bin/awk/b.c
1511
|| (k == NCCL && !member(c, (int *) f->re[p[i]].lval.rp) && c != 0 && c != HAT)) {
usr.bin/awk/b.c
1536
if ((k = tmpset[0]) != p[0])
usr.bin/awk/b.c
1538
for (j = 1; j <= k; j++)
usr.bin/awk/b.c
265
int i, k;
usr.bin/awk/b.c
269
k = *(f->re[0].lfollow);
usr.bin/awk/b.c
271
f->posns[2] = intalloc(k + 1, __func__);
usr.bin/awk/b.c
272
for (i = 0; i <= k; i++) {
usr.bin/awk/b.c
280
*f->posns[2] = k-1; /* leave out position 0 */
usr.bin/awk/b.c
281
for (i = 0; i < k; i++) {
usr.bin/awk/b.c
866
char *i, *j, *k, *buf = *pbuf;
usr.bin/awk/b.c
881
i = j = k = buf;
usr.bin/awk/b.c
888
if (k - j < (int)awk_mb_cur_max) {
usr.bin/awk/b.c
889
if (k + awk_mb_cur_max > buf + bufsize) {
usr.bin/awk/b.c
900
k = buf + (k - obuf);
usr.bin/awk/b.c
907
*k++ = (c = getc(f)) != EOF ? c : 0;
usr.bin/awk/b.c
956
if (*--k && ungetc(*k, f) == EOF)
usr.bin/awk/b.c
957
FATAL("unable to ungetc '%c'", *k);
usr.bin/awk/b.c
958
while (k > patbeg + patlen);
usr.bin/awk/b.c
959
*k = '\0';
usr.bin/awk/run.c
1000
else if (m > k)
usr.bin/awk/run.c
1001
m = k;
usr.bin/awk/run.c
1007
n = k - 1;
usr.bin/awk/run.c
1010
else if (n > k - m)
usr.bin/awk/run.c
1011
n = k - m;
usr.bin/awk/run.c
1513
int k;
usr.bin/awk/run.c
1518
k = (n == PREINCR || n == POSTINCR) ? 1 : -1;
usr.bin/awk/run.c
1520
setfval(x, xf + k);
usr.bin/awk/run.c
1525
setfval(x, xf + k);
usr.bin/awk/run.c
562
Cell *ap, *k;
usr.bin/awk/run.c
575
k = lookup(buf, (Array *) ap->sval);
usr.bin/awk/run.c
578
if (k == NULL)
usr.bin/awk/run.c
975
int k, m, n;
usr.bin/awk/run.c
986
k = u8_strlen(s) + 1;
usr.bin/awk/run.c
987
if (k <= 1) {
usr.bin/cdio/cddb.c
350
int k;
usr.bin/cdio/cddb.c
365
k = strtonum(line, 0, n - 1, &errstr);
usr.bin/cdio/cddb.c
368
safe_copy(&result[k], end);
usr.bin/cdio/mmc.c
184
int current, error, j, k;
usr.bin/cdio/mmc.c
265
for (k = 0; mmc_profile[k].name != NULL; k++)
usr.bin/cdio/mmc.c
266
if (profile == mmc_profile[k].id)
usr.bin/cdio/mmc.c
268
if (mmc_profile[k].name == NULL)
usr.bin/cdio/mmc.c
271
printf(" %s", mmc_profile[k].name);
usr.bin/ctfconv/hash.c
177
uint32_t k;
usr.bin/ctfconv/hash.c
182
k = 0;
usr.bin/ctfconv/hash.c
184
k = *s++;
usr.bin/ctfconv/hash.c
186
k = ((k << 2) | (k >> 30)) ^ *s++;
usr.bin/ctfconv/hash.c
187
return k;
usr.bin/cvs/diff3.c
793
int j, k;
usr.bin/cvs/diff3.c
802
for (k = de[n].new.to-de[n].new.from; k > 0; k-= j) {
usr.bin/cvs/diff3.c
804
j = k > BUFSIZ ? BUFSIZ : k;
usr.bin/cvs/diff_internals.c
545
int i, k, y, j, l;
usr.bin/cvs/diff_internals.c
556
k = 0;
usr.bin/cvs/diff_internals.c
569
l = search(c, k, y);
usr.bin/cvs/diff_internals.c
572
if (l <= k) {
usr.bin/cvs/diff_internals.c
582
k++;
usr.bin/cvs/diff_internals.c
587
return (k);
usr.bin/cvs/diff_internals.c
607
search(int *c, int k, int y)
usr.bin/cvs/diff_internals.c
611
if (clist[c[k]].y < y) /* quick look for typical case */
usr.bin/cvs/diff_internals.c
612
return (k + 1);
usr.bin/cvs/diff_internals.c
614
j = k + 1;
usr.bin/cvs/diff_internals.c
753
int j, m = 0, k;
usr.bin/cvs/diff_internals.c
760
k = n - m;
usr.bin/cvs/diff_internals.c
761
for (j = 1; j <= k; j++) {
usr.bin/cvs/hash_func.c
45
const char *k;
usr.bin/cvs/hash_func.c
47
#define HASH4 h = (h << 5) + h + *k++;
usr.bin/cvs/hash_func.c
50
k = key;
usr.bin/cvs/rcs.h
91
#define RCS_KWEXP_INVAL(k) \
usr.bin/cvs/rcs.h
92
((k & RCS_KWEXP_ERR) || \
usr.bin/cvs/rcs.h
93
((k & RCS_KWEXP_OLD) && (k & ~RCS_KWEXP_OLD)))
usr.bin/cvs/rcsparse.c
1251
kw_cmp(const void *k, const void *e)
usr.bin/cvs/rcsparse.c
1253
return (strcmp(k, ((const struct rcs_keyword *)e)->k_name));
usr.bin/diff/diffreg.c
594
int i, k, y, j, l;
usr.bin/diff/diffreg.c
605
k = 0;
usr.bin/diff/diffreg.c
618
l = search(c, k, y);
usr.bin/diff/diffreg.c
621
if (l <= k) {
usr.bin/diff/diffreg.c
631
k++;
usr.bin/diff/diffreg.c
636
return (k);
usr.bin/diff/diffreg.c
656
search(int *c, int k, int y)
usr.bin/diff/diffreg.c
660
if (clist[c[k]].y < y) /* quick look for typical case */
usr.bin/diff/diffreg.c
661
return (k + 1);
usr.bin/diff/diffreg.c
663
j = k + 1;
usr.bin/diff/diffreg.c
806
int j, m = 0, k;
usr.bin/diff/diffreg.c
813
k = n - m;
usr.bin/diff/diffreg.c
814
for (j = 1; j <= k; j++) {
usr.bin/diff3/diff3prog.c
550
int j,k;
usr.bin/diff3/diff3prog.c
559
for (k = de[n].new.to-de[n].new.from; k > 0; k-= j) {
usr.bin/diff3/diff3prog.c
561
j = k > BUFSIZ ? BUFSIZ : k;
usr.bin/dig/lib/dns/rdata.c
183
unsigned int i, j, k;
usr.bin/dig/lib/dns/rdata.c
203
for (k = 0; k < 8; k++) {
usr.bin/dig/lib/dns/rdata.c
204
if ((sr->base[i + j] & (0x80 >> k)) == 0)
usr.bin/dig/lib/dns/rdata.c
206
t = window * 256 + j * 8 + k;
usr.bin/dig/lib/dns/rdata.c
740
type_cmp(const void *k, const void *e)
usr.bin/dig/lib/dns/rdata.c
742
return (strcasecmp(k, ((const dns_rdata_type_lookup_t *)e)->type));
usr.bin/dig/lib/isc/include/isc/util.h
70
union { const void *k; void *v; } _u; \
usr.bin/dig/lib/isc/include/isc/util.h
71
_u.k = konst; \
usr.bin/dig/lib/isc/symtab.c
132
#define FIND(s, k, t, b, e) \
usr.bin/dig/lib/isc/symtab.c
133
b = hash((k), (s)->case_sensitive) % (s)->size; \
usr.bin/dig/lib/isc/symtab.c
137
strcmp(e->key, (k)) == 0) \
usr.bin/dig/lib/isc/symtab.c
143
strcasecmp(e->key, (k)) == 0) \
usr.bin/less/decode.c
40
#define SK(k) \
usr.bin/less/decode.c
41
SK_SPECIAL_KEY, (k), 6, 1, 1, 1
usr.bin/lex/dfa.c
1018
int tch, i, j, k, ns, dupfwd[CSIZE + 1], lenccl, cclp, ich;
usr.bin/lex/dfa.c
1061
for (k = 0; k < lenccl; ++k) {
usr.bin/lex/dfa.c
1062
ich = ccltbl[cclp + k];
usr.bin/lex/dfa.c
1076
for (k = 0; k < lenccl; ++k) {
usr.bin/lex/dfa.c
1077
ich = ccltbl[cclp + k];
usr.bin/lex/gen.c
1059
int i, j, k, *accset, nacc, *acc_array, total_states;
usr.bin/lex/gen.c
1124
for (k = 1; k <= nacc; ++k) {
usr.bin/lex/gen.c
1125
int accnum = accset[k];
usr.bin/lex/gen.c
1148
accset[k]);
usr.bin/lex/gen.c
1150
if (k < nacc)
usr.bin/lex/gen.c
1195
k = lastdfa + 2;
usr.bin/lex/gen.c
1204
++k;
usr.bin/lex/gen.c
1207
"yy_accept", k);
usr.bin/lex/gen.c
1215
yyacc_tbl->td_lolen = k;
usr.bin/m4/eval.c
872
const char *ap, *fc, *k;
usr.bin/m4/eval.c
889
for (k = fc + nc - 1; k >= fc; k--)
usr.bin/m4/eval.c
890
pushback(*k);
usr.bin/make/cond.c
1005
if (k == K_COND_ELIFMAKE && len == strlen(COND_ELIFMAKE) &&
usr.bin/make/cond.c
1012
if (k == K_COND_ELIFNMAKE && len == strlen(COND_ELIFNMAKE) &&
usr.bin/make/cond.c
1021
if (k == K_COND_ELSE && len == strlen(COND_ELSE) &&
usr.bin/make/cond.c
1035
if (k == K_COND_ENDIF && len == strlen(COND_ENDIF) &&
usr.bin/make/cond.c
1063
if (k == K_COND_FOR && len == strlen(COND_FOR) &&
usr.bin/make/cond.c
1069
if (k == K_COND_UNDEF && len == strlen(COND_UNDEF) &&
usr.bin/make/cond.c
1075
if (k == K_COND_POISON && len == strlen(COND_POISON) &&
usr.bin/make/cond.c
1081
if (k == K_COND_INCLUDE && len == strlen(COND_INCLUDE) &&
usr.bin/make/cond.c
932
uint32_t k;
usr.bin/make/cond.c
946
k = ohash_interval(line, &end);
usr.bin/make/cond.c
947
switch(k % MAGICSLOTS2) {
usr.bin/make/cond.c
949
if (k == K_COND_IF && len == strlen(COND_IF) &&
usr.bin/make/cond.c
956
if (k == K_COND_IFDEF && len == strlen(COND_IFDEF) &&
usr.bin/make/cond.c
963
if (k == K_COND_IFNDEF && len == strlen(COND_IFNDEF) &&
usr.bin/make/cond.c
970
if (k == K_COND_IFMAKE && len == strlen(COND_IFMAKE) &&
usr.bin/make/cond.c
977
if (k == K_COND_IFNMAKE && len == strlen(COND_IFNMAKE) &&
usr.bin/make/cond.c
984
if (k == K_COND_ELIF && len == strlen(COND_ELIF) &&
usr.bin/make/cond.c
991
if (k == K_COND_ELIFDEF && len == strlen(COND_ELIFDEF) &&
usr.bin/make/cond.c
998
if (k == K_COND_ELIFNDEF && len == strlen(COND_ELIFNDEF) &&
usr.bin/make/job.c
279
Job *j, *k, *jnext;
usr.bin/make/job.c
282
k = errorJobs;
usr.bin/make/job.c
284
for (j = k; j != NULL; j = jnext) {
usr.bin/make/job.c
302
Job *j, *k, *jnext;
usr.bin/make/job.c
316
k = errorJobs;
usr.bin/make/job.c
318
for (j = k; j != NULL; j = jnext) {
usr.bin/make/job.c
320
if (j->location->fname == k->location->fname)
usr.bin/make/parse.c
177
#define P(k) k, sizeof(k), K_##k
usr.bin/make/suff.c
198
uint32_t k;
usr.bin/make/suff.c
204
k = 0;
usr.bin/make/suff.c
206
k = *--p;
usr.bin/make/suff.c
208
reverse_hash_add_char(&k, --p);
usr.bin/make/suff.c
210
return k;
usr.bin/make/var.c
1001
idx = classify_var(name.s, &name.e, &k, &ext);
usr.bin/make/var.c
1002
val = get_expanded_value(name.s, name.e, idx, k, ext, ctxt, err,
usr.bin/make/var.c
1118
uint32_t k;
usr.bin/make/var.c
1138
idx = classify_var(name.s, &name.e, &k, &ext);
usr.bin/make/var.c
1188
uint32_t k;
usr.bin/make/var.c
1196
k = ohash_interval(name, &ename);
usr.bin/make/var.c
1198
l->me = find_global_var_without_env(name, ename, k);
usr.bin/make/var.c
1309
uint32_t k;
usr.bin/make/var.c
1312
k = ohash_interval(name, &ename);
usr.bin/make/var.c
1313
v = find_global_var_without_env(name, ename, k);
usr.bin/make/var.c
1324
uint32_t k;
usr.bin/make/var.c
1327
k = ohash_interval(name, &ename);
usr.bin/make/var.c
1328
v = find_global_var_without_env(name, ename, k);
usr.bin/make/var.c
250
uint32_t k;
usr.bin/make/var.c
258
k = *pk;
usr.bin/make/var.c
262
k = name[0];
usr.bin/make/var.c
265
switch (k % MAGICSLOTS1) { /* MAGICSLOTS should be the */
usr.bin/make/var.c
446
find_global_var_without_env(const char *name, const char *ename, uint32_t k)
usr.bin/make/var.c
451
slot = ohash_lookup_interval(&global_variables, name, ename, k);
usr.bin/make/var.c
484
find_global_var(const char *name, const char *ename, uint32_t k)
usr.bin/make/var.c
488
v = find_global_var_without_env(name, ename, k);
usr.bin/make/var.c
504
uint32_t k;
usr.bin/make/var.c
507
idx = classify_var(name, &ename, &k, &ext);
usr.bin/make/var.c
516
v = find_global_var(name, ename, k);
usr.bin/make/var.c
558
uint32_t k;
usr.bin/make/var.c
563
idx = classify_var(name, &ename, &k, &ext);
usr.bin/make/var.c
569
slot = ohash_lookup_interval(&global_variables, name, ename, k);
usr.bin/make/var.c
593
uint32_t k;
usr.bin/make/var.c
597
idx = classify_var(name, &ename, &k, &ext);
usr.bin/make/var.c
604
v = find_global_var(name, ename, k);
usr.bin/make/var.c
692
uint32_t k;
usr.bin/make/var.c
696
idx = classify_var(name, &ename, &k, &ext);
usr.bin/make/var.c
703
v = find_global_var(name, ename, k);
usr.bin/make/var.c
716
uint32_t k;
usr.bin/make/var.c
720
idx = classify_var(name, &ename, &k, &ext);
usr.bin/make/var.c
725
v = find_global_var(name, ename, k);
usr.bin/make/var.c
893
get_expanded_value(const char *name, const char *ename, int idx, uint32_t k,
usr.bin/make/var.c
907
Var *v = find_global_var(name, ename, k);
usr.bin/make/var.c
984
uint32_t k;
usr.bin/mg/cinfo.c
106
getkeyname(char *cp, size_t len, int k)
usr.bin/mg/cinfo.c
111
if (k < 0)
usr.bin/mg/cinfo.c
112
k = CHARMASK(k); /* sign extended char */
usr.bin/mg/cinfo.c
113
switch (k) {
usr.bin/mg/cinfo.c
133
if (k >= KFIRST && k <= KLAST &&
usr.bin/mg/cinfo.c
134
(np = keystrings[k - KFIRST]) != NULL)
usr.bin/mg/cinfo.c
136
if (k > CCHR('?')) {
usr.bin/mg/cinfo.c
138
*cp++ = ((k >> 6) & 7) + '0';
usr.bin/mg/cinfo.c
139
*cp++ = ((k >> 3) & 7) + '0';
usr.bin/mg/cinfo.c
140
*cp++ = (k & 7) + '0';
usr.bin/mg/cinfo.c
143
} else if (k < ' ') {
usr.bin/mg/cinfo.c
146
k = CCHR(k);
usr.bin/mg/cinfo.c
147
if (ISUPPER(k))
usr.bin/mg/cinfo.c
148
k = TOLOWER(k);
usr.bin/mg/cinfo.c
150
*cp++ = k;
usr.bin/mg/display.c
1018
int k;
usr.bin/mg/display.c
1044
k = offs + j - ndraw;
usr.bin/mg/display.c
1045
uline(k, vscreen[k], &blanks);
usr.bin/mg/display.c
1068
k = offs + j - 1;
usr.bin/mg/display.c
1069
uline(k, vscreen[k], pscreen[offs + i - 1]);
usr.bin/mg/re_search.c
251
int j, k, s, more, num, state;
usr.bin/mg/re_search.c
301
k = regex_match[num].rm_eo - regex_match[num].rm_so;
usr.bin/mg/re_search.c
302
if (j + k >= REPLEN)
usr.bin/mg/re_search.c
305
&repstr[j], k);
usr.bin/mg/re_search.c
306
j += k;
usr.bin/openssl/ca.c
1248
int k;
usr.bin/openssl/ca.c
1270
k = snprintf(pempath, sizeof(pempath),
usr.bin/openssl/ca.c
1273
if (k < 0 || k >= sizeof(pempath)) {
usr.bin/openssl/s_client.c
1425
k = SSL_write(con, &(cbuf[cbuf_off]),
usr.bin/openssl/s_client.c
1427
switch (SSL_get_error(con, k)) {
usr.bin/openssl/s_client.c
1429
cbuf_off += k;
usr.bin/openssl/s_client.c
1430
cbuf_len -= k;
usr.bin/openssl/s_client.c
1431
if (k <= 0)
usr.bin/openssl/s_client.c
1468
if ((k != 0) || (cbuf_len != 0)) {
usr.bin/openssl/s_client.c
1512
k = p = SSL_peek(con, pbuf, 1024 /* BUFSIZZ */ );
usr.bin/openssl/s_client.c
1518
k = SSL_read(con, sbuf, p);
usr.bin/openssl/s_client.c
1521
k = SSL_read(con, sbuf, 1024 /* BUFSIZZ */ );
usr.bin/openssl/s_client.c
1524
switch (SSL_get_error(con, k)) {
usr.bin/openssl/s_client.c
1526
if (k <= 0)
usr.bin/openssl/s_client.c
1529
sbuf_len = k;
usr.bin/openssl/s_client.c
1538
if (k < p) {
usr.bin/openssl/s_client.c
1549
p, k);
usr.bin/openssl/s_client.c
867
int s, k, p = 0, pending = 0;
usr.bin/openssl/s_server.c
1475
int k, i;
usr.bin/openssl/s_server.c
1679
l = k = 0;
usr.bin/openssl/s_server.c
1691
k = SSL_write(con, &(buf[l]), (unsigned int) i);
usr.bin/openssl/s_server.c
1692
switch (SSL_get_error(con, k)) {
usr.bin/openssl/s_server.c
1712
if (k <= 0)
usr.bin/openssl/s_server.c
1714
l += k;
usr.bin/openssl/s_server.c
1715
i -= k;
usr.bin/openssl/s_server.c
1899
int i, j, k, dot;
usr.bin/openssl/s_server.c
2160
k = BIO_write(io, &(buf[j]), i - j);
usr.bin/openssl/s_server.c
2161
if (k <= 0) {
usr.bin/openssl/s_server.c
2169
j += k;
usr.bin/openssl/speed.c
1034
int i, j, k;
usr.bin/openssl/speed.c
2546
for (k = 0; k < ALGOR_NUM; k++) {
usr.bin/openssl/speed.c
2547
if (!doit[k])
usr.bin/openssl/speed.c
2550
fprintf(stdout, "+F:%d:%s", k, names[k]);
usr.bin/openssl/speed.c
2552
fprintf(stdout, "%-13s", names[k]);
usr.bin/openssl/speed.c
2554
if (results[k][j] > 10000 && !mr)
usr.bin/openssl/speed.c
2555
fprintf(stdout, " %11.2fk", results[k][j] / 1e3);
usr.bin/openssl/speed.c
2557
fprintf(stdout, mr ? ":%.2f" : " %11.2f ", results[k][j]);
usr.bin/openssl/speed.c
2562
for (k = 0; k < RSA_NUM; k++) {
usr.bin/openssl/speed.c
2563
if (!rsa_doit[k])
usr.bin/openssl/speed.c
2571
k, rsa_bits[k], rsa_results[k][0],
usr.bin/openssl/speed.c
2572
rsa_results[k][1]);
usr.bin/openssl/speed.c
2575
rsa_bits[k], rsa_results[k][0], rsa_results[k][1],
usr.bin/openssl/speed.c
2576
1.0 / rsa_results[k][0], 1.0 / rsa_results[k][1]);
usr.bin/openssl/speed.c
2579
for (k = 0; k < DSA_NUM; k++) {
usr.bin/openssl/speed.c
2580
if (!dsa_doit[k])
usr.bin/openssl/speed.c
2588
k, dsa_bits[k], dsa_results[k][0], dsa_results[k][1]);
usr.bin/openssl/speed.c
2591
dsa_bits[k], dsa_results[k][0], dsa_results[k][1],
usr.bin/openssl/speed.c
2592
1.0 / dsa_results[k][0], 1.0 / dsa_results[k][1]);
usr.bin/openssl/speed.c
2595
for (k = 0; k < EC_NUM; k++) {
usr.bin/openssl/speed.c
2596
if (!ecdsa_doit[k])
usr.bin/openssl/speed.c
2604
k, test_curves_bits[k],
usr.bin/openssl/speed.c
2605
ecdsa_results[k][0], ecdsa_results[k][1]);
usr.bin/openssl/speed.c
2609
test_curves_bits[k],
usr.bin/openssl/speed.c
2610
test_curves_names[k],
usr.bin/openssl/speed.c
2611
ecdsa_results[k][0], ecdsa_results[k][1],
usr.bin/openssl/speed.c
2612
1.0 / ecdsa_results[k][0], 1.0 / ecdsa_results[k][1]);
usr.bin/openssl/speed.c
2617
for (k = 0; k < EC_NUM; k++) {
usr.bin/openssl/speed.c
2618
if (!ecdh_doit[k])
usr.bin/openssl/speed.c
2626
k, test_curves_bits[k],
usr.bin/openssl/speed.c
2627
ecdh_results[k][0], 1.0 / ecdh_results[k][0]);
usr.bin/openssl/speed.c
2631
test_curves_bits[k],
usr.bin/openssl/speed.c
2632
test_curves_names[k],
usr.bin/openssl/speed.c
2633
ecdh_results[k][0], 1.0 / ecdh_results[k][0]);
usr.bin/openssl/speed.c
2637
for (k = 0; k < MLKEM_NUM; k++) {
usr.bin/openssl/speed.c
2638
if (!mlkem_doit[k])
usr.bin/openssl/speed.c
2649
mlkem_params[k].bits,
usr.bin/openssl/speed.c
2650
mlkem_results[k][2], 1.0 / mlkem_results[k][2],
usr.bin/openssl/speed.c
2651
mlkem_results[k][0], 1.0 / mlkem_results[k][0],
usr.bin/openssl/speed.c
2652
mlkem_results[k][1], 1.0 / mlkem_results[k][1]);
usr.bin/openssl/speed.c
2656
mlkem_params[k].bits,
usr.bin/openssl/speed.c
2657
mlkem_results[k][2], 1.0 / mlkem_results[k][2],
usr.bin/openssl/speed.c
2658
mlkem_results[k][0], 1.0 / mlkem_results[k][0],
usr.bin/openssl/speed.c
2659
mlkem_results[k][1], 1.0 / mlkem_results[k][1]);
usr.bin/openssl/speed.c
2810
int k;
usr.bin/openssl/speed.c
2814
k = strtonum(sstrsep(&p, sep),
usr.bin/openssl/speed.c
2820
rsa_results[k][0] = 1 / (1 / rsa_results[k][0] + 1 / d);
usr.bin/openssl/speed.c
2822
rsa_results[k][0] = d;
usr.bin/openssl/speed.c
2826
rsa_results[k][1] = 1 / (1 / rsa_results[k][1] + 1 / d);
usr.bin/openssl/speed.c
2828
rsa_results[k][1] = d;
usr.bin/openssl/speed.c
2830
int k;
usr.bin/openssl/speed.c
2834
k = strtonum(sstrsep(&p, sep),
usr.bin/openssl/speed.c
2840
rsa_results[k][0] = 1 / (1 / rsa_results[k][0] + 1 / d);
usr.bin/openssl/speed.c
2842
rsa_results[k][0] = d;
usr.bin/openssl/speed.c
2846
rsa_results[k][1] = 1 / (1 / rsa_results[k][1] + 1 / d);
usr.bin/openssl/speed.c
2848
rsa_results[k][1] = d;
usr.bin/openssl/speed.c
2850
int k;
usr.bin/openssl/speed.c
2854
k = strtonum(sstrsep(&p, sep),
usr.bin/openssl/speed.c
2860
dsa_results[k][0] = 1 / (1 / dsa_results[k][0] + 1 / d);
usr.bin/openssl/speed.c
2862
dsa_results[k][0] = d;
usr.bin/openssl/speed.c
2866
dsa_results[k][1] = 1 / (1 / dsa_results[k][1] + 1 / d);
usr.bin/openssl/speed.c
2868
dsa_results[k][1] = d;
usr.bin/openssl/speed.c
2870
int k;
usr.bin/openssl/speed.c
2874
k = strtonum(sstrsep(&p, sep),
usr.bin/openssl/speed.c
2880
ecdsa_results[k][0] = 1 / (1 / ecdsa_results[k][0] + 1 / d);
usr.bin/openssl/speed.c
2882
ecdsa_results[k][0] = d;
usr.bin/openssl/speed.c
2886
ecdsa_results[k][1] = 1 / (1 / ecdsa_results[k][1] + 1 / d);
usr.bin/openssl/speed.c
2888
ecdsa_results[k][1] = d;
usr.bin/openssl/speed.c
2890
int k;
usr.bin/openssl/speed.c
2894
k = strtonum(sstrsep(&p, sep),
usr.bin/openssl/speed.c
2900
ecdh_results[k][0] = 1 / (1 / ecdh_results[k][0] + 1 / d);
usr.bin/openssl/speed.c
2902
ecdh_results[k][0] = d;
usr.bin/rcs/diff.c
527
int i, k, y, j, l;
usr.bin/rcs/diff.c
538
k = 0;
usr.bin/rcs/diff.c
551
l = search(c, k, y);
usr.bin/rcs/diff.c
554
if (l <= k) {
usr.bin/rcs/diff.c
564
k++;
usr.bin/rcs/diff.c
569
return (k);
usr.bin/rcs/diff.c
589
search(int *c, int k, int y)
usr.bin/rcs/diff.c
593
if (clist[c[k]].y < y) /* quick look for typical case */
usr.bin/rcs/diff.c
594
return (k + 1);
usr.bin/rcs/diff.c
596
j = k + 1;
usr.bin/rcs/diff.c
735
int j, m = 0, k;
usr.bin/rcs/diff.c
742
k = n - m;
usr.bin/rcs/diff.c
743
for (j = 1; j <= k; j++) {
usr.bin/rcs/diff3.c
888
int j, k;
usr.bin/rcs/diff3.c
897
for (k = de[n].new.to-de[n].new.from; k > 0; k-= j) {
usr.bin/rcs/diff3.c
899
j = k > BUFSIZ ? BUFSIZ : k;
usr.bin/rcs/rcs.h
92
#define RCS_KWEXP_INVAL(k) \
usr.bin/rcs/rcs.h
93
((k & RCS_KWEXP_ERR) || \
usr.bin/rcs/rcs.h
94
((k & RCS_KWEXP_OLD) && (k & ~RCS_KWEXP_OLD)))
usr.bin/rcs/rcsparse.c
1249
kw_cmp(const void *k, const void *e)
usr.bin/rcs/rcsparse.c
1251
return (strcmp(k, ((const struct rcs_keyword *)e)->k_name));
usr.bin/sort/coll.c
100
if (ka->key[i].k && ka->key[i].k != s)
usr.bin/sort/coll.c
1006
s1 = kv1->k;
usr.bin/sort/coll.c
1007
s2 = kv2->k;
usr.bin/sort/coll.c
101
bwsfree(ka->key[i].k);
usr.bin/sort/coll.c
1086
bwsprintf(stdout, kv1->k, "; k1=<", ">");
usr.bin/sort/coll.c
1087
bwsprintf(stdout, kv2->k, "; k2=<", ">");
usr.bin/sort/coll.c
1092
d1 = bwstod(kv1->k, &empty1);
usr.bin/sort/coll.c
1110
d2 = bwstod(kv2->k, &empty2);
usr.bin/sort/coll.c
1157
d1 = bwstod(kv1->k, &empty1);
usr.bin/sort/coll.c
1163
d2 = bwstod(kv2->k, &empty2);
usr.bin/sort/coll.c
117
if (kv->k != s)
usr.bin/sort/coll.c
118
bwsfree(kv->k);
usr.bin/sort/coll.c
119
kv->k = s;
usr.bin/sort/coll.c
1240
bwsprintf(stdout, kv1->k, "; k1=<", ">");
usr.bin/sort/coll.c
1241
bwsprintf(stdout, kv2->k, "; k2=<", ">");
usr.bin/sort/coll.c
1245
kv1->hint->v.Mh.m = bws_month_score(kv1->k);
usr.bin/sort/coll.c
1251
kv2->hint->v.Mh.m = bws_month_score(kv2->k);
usr.bin/sort/coll.c
1267
val1 = bws_month_score(kv1->k);
usr.bin/sort/coll.c
1269
val2 = bws_month_score(kv2->k);
usr.bin/sort/coll.c
152
if (kv->k != si->str)
usr.bin/sort/coll.c
153
ret += bws_memsize(kv->k);
usr.bin/sort/coll.c
753
bwsprintf(stdout, kv1->k, "; k1=<", ">");
usr.bin/sort/coll.c
754
printf("(%zu)", BWSLEN(kv1->k));
usr.bin/sort/coll.c
755
bwsprintf(stdout, kv2->k, ", k2=<", ">");
usr.bin/sort/coll.c
756
printf("(%zu)", BWSLEN(kv2->k));
usr.bin/sort/coll.c
759
return bwscoll(kv1->k, kv2->k, offset);
usr.bin/sort/coll.c
786
s1 = kv1->k;
usr.bin/sort/coll.c
787
s2 = kv2->k;
usr.bin/sort/coll.c
955
s1 = kv1->k;
usr.bin/sort/coll.c
956
s2 = kv2->k;
usr.bin/sort/coll.h
86
struct bwstring *k; /* key string */
usr.bin/sort/radixsort.c
154
bws = sli->ka.key[0].k;
usr.bin/ssh/auth-options.c
499
sshauthopt_from_cert(struct sshkey *k)
usr.bin/ssh/auth-options.c
503
if (k == NULL || !sshkey_type_is_cert(k->type) || k->cert == NULL ||
usr.bin/ssh/auth-options.c
504
k->cert->type != SSH2_CERT_TYPE_USER)
usr.bin/ssh/auth-options.c
511
if (cert_option_list(ret, k->cert->critical,
usr.bin/ssh/auth-options.c
516
if (cert_option_list(ret, k->cert->extensions,
usr.bin/ssh/auth-options.h
98
struct sshauthopt *sshauthopt_from_cert(struct sshkey *k);
usr.bin/ssh/authfile.c
197
struct sshkey *k = NULL;
usr.bin/ssh/authfile.c
211
if ((k = sshkey_new(KEY_UNSPEC)) == NULL) {
usr.bin/ssh/authfile.c
231
if ((r = sshkey_read(k, &cp)) == 0) {
usr.bin/ssh/authfile.c
240
*kp = k;
usr.bin/ssh/authfile.c
247
free(k);
usr.bin/ssh/bitmap.c
169
size_t i, j, k, need = bitmap_nbytes(b);
usr.bin/ssh/bitmap.c
176
for (i = k = 0; i < b->top + 1; i++) {
usr.bin/ssh/bitmap.c
178
if (k >= l)
usr.bin/ssh/bitmap.c
180
s[need - 1 - k++] = (b->d[i] >> (j * 8)) & 0xff;
usr.bin/ssh/chacha.c
53
chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)
usr.bin/ssh/chacha.c
57
x->input[4] = U8TO32_LITTLE(k + 0);
usr.bin/ssh/chacha.c
58
x->input[5] = U8TO32_LITTLE(k + 4);
usr.bin/ssh/chacha.c
59
x->input[6] = U8TO32_LITTLE(k + 8);
usr.bin/ssh/chacha.c
60
x->input[7] = U8TO32_LITTLE(k + 12);
usr.bin/ssh/chacha.c
62
k += 16;
usr.bin/ssh/chacha.c
67
x->input[8] = U8TO32_LITTLE(k + 0);
usr.bin/ssh/chacha.c
68
x->input[9] = U8TO32_LITTLE(k + 4);
usr.bin/ssh/chacha.c
69
x->input[10] = U8TO32_LITTLE(k + 8);
usr.bin/ssh/chacha.c
70
x->input[11] = U8TO32_LITTLE(k + 12);
usr.bin/ssh/chacha.h
25
void chacha_keysetup(struct chacha_ctx *x, const u_char *k, u_int kbits)
usr.bin/ssh/cipher-aesctr.c
53
aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits)
usr.bin/ssh/cipher-aesctr.c
55
x->rounds = rijndaelKeySetupEnc(x->ek, k, kbits);
usr.bin/ssh/cipher-aesctr.h
31
void aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits);
usr.bin/ssh/crypto_api.h
73
int crypto_kem_sntrup761_enc(unsigned char *cstr, unsigned char *k,
usr.bin/ssh/crypto_api.h
75
int crypto_kem_sntrup761_dec(unsigned char *k,
usr.bin/ssh/hostfile.c
314
check_key_not_revoked(struct hostkeys *hostkeys, struct sshkey *k)
usr.bin/ssh/hostfile.c
316
int is_cert = sshkey_is_cert(k);
usr.bin/ssh/hostfile.c
322
if (sshkey_equal_public(k, hostkeys->entries[i].key))
usr.bin/ssh/hostfile.c
324
if (is_cert && k != NULL &&
usr.bin/ssh/hostfile.c
325
sshkey_equal_public(k->cert->signature_key,
usr.bin/ssh/hostfile.c
349
struct sshkey *k, int keytype, int nid, const struct hostkey_entry **found)
usr.bin/ssh/hostfile.c
353
int want_cert = sshkey_is_cert(k);
usr.bin/ssh/hostfile.c
362
if (k == NULL) {
usr.bin/ssh/hostfile.c
372
k = hostkeys->entries[i].key;
usr.bin/ssh/hostfile.c
376
if (sshkey_equal_public(k->cert->signature_key,
usr.bin/ssh/hostfile.c
385
if (sshkey_equal(k, hostkeys->entries[i].key)) {
usr.bin/ssh/hostfile.c
397
if (check_key_not_revoked(hostkeys, k) != 0) {
usr.bin/ssh/kex-names.c
101
const struct kexalg *k;
usr.bin/ssh/kex-names.c
103
for (k = kexalgs; k->name != NULL; k++) {
usr.bin/ssh/kex-names.c
104
if (strcmp(k->name, name) == 0)
usr.bin/ssh/kex-names.c
105
return k;
usr.bin/ssh/kex-names.c
119
const struct kexalg *k;
usr.bin/ssh/kex-names.c
121
if ((k = kex_alg_by_name(name)) == NULL)
usr.bin/ssh/kex-names.c
123
return k->pq_alg == KEX_IS_PQ;
usr.bin/ssh/kex-names.c
129
const struct kexalg *k;
usr.bin/ssh/kex-names.c
131
if ((k = kex_alg_by_name(name)) == NULL)
usr.bin/ssh/kex-names.c
133
return k->type;
usr.bin/ssh/kex-names.c
139
const struct kexalg *k;
usr.bin/ssh/kex-names.c
141
if ((k = kex_alg_by_name(name)) == NULL)
usr.bin/ssh/kex-names.c
143
return k->hash_alg;
usr.bin/ssh/kex-names.c
149
const struct kexalg *k;
usr.bin/ssh/kex-names.c
151
if ((k = kex_alg_by_name(name)) == NULL)
usr.bin/ssh/kex-names.c
153
return k->ec_nid;
usr.bin/ssh/kex-names.c
89
const struct kexalg *k;
usr.bin/ssh/kex-names.c
92
for (k = kexalgs; k->name != NULL; k++)
usr.bin/ssh/kex-names.c
93
xextendf(&ret, sep_str, "%s", k->name);
usr.bin/ssh/kex.c
866
choose_kex(struct kex *k, char *client, char *server)
usr.bin/ssh/kex.c
868
k->name = match_list(client, server, NULL);
usr.bin/ssh/kex.c
870
debug("kex: algorithm: %s", k->name ? k->name : "(no match)");
usr.bin/ssh/kex.c
871
if (k->name == NULL)
usr.bin/ssh/kex.c
873
if (!kex_name_valid(k->name)) {
usr.bin/ssh/kex.c
874
error_f("unsupported KEX method %s", k->name);
usr.bin/ssh/kex.c
877
k->kex_type = kex_type_from_name(k->name);
usr.bin/ssh/kex.c
878
k->hash_alg = kex_hash_from_name(k->name);
usr.bin/ssh/kex.c
879
k->ec_nid = kex_nid_from_name(k->name);
usr.bin/ssh/kex.c
884
choose_hostkeyalg(struct kex *k, char *client, char *server)
usr.bin/ssh/kex.c
886
free(k->hostkey_alg);
usr.bin/ssh/kex.c
887
k->hostkey_alg = match_list(client, server, NULL);
usr.bin/ssh/kex.c
890
k->hostkey_alg ? k->hostkey_alg : "(no match)");
usr.bin/ssh/kex.c
891
if (k->hostkey_alg == NULL)
usr.bin/ssh/kex.c
893
k->hostkey_type = sshkey_type_from_name(k->hostkey_alg);
usr.bin/ssh/kex.c
894
if (k->hostkey_type == KEY_UNSPEC) {
usr.bin/ssh/kex.c
895
error_f("unsupported hostkey algorithm %s", k->hostkey_alg);
usr.bin/ssh/kex.c
898
k->hostkey_nid = sshkey_ecdsa_nid_from_name(k->hostkey_alg);
usr.bin/ssh/libcrux_internal.h
16777
size_t k = i;
usr.bin/ssh/libcrux_internal.h
16778
libcrux_ml_dsa_polynomial_from_i32_array_ff_37(Eurydice_array_to_slice_shared_2c0(&tmp_stack.ptr[k]),
usr.bin/ssh/libcrux_internal.h
16779
&matrix.ptr[start_index + k]);
usr.bin/ssh/libcrux_internal.h
21310
k =
usr.bin/ssh/libcrux_internal.h
21315
libcrux_secrets_int_as_i32_f5(libcrux_secrets_int_as_i16_36(k)) *
usr.bin/ssh/libcrux_internal.h
9898
k =
usr.bin/ssh/libcrux_internal.h
9901
int64_t k_times_modulus = (int64_t)k * (int64_t)LIBCRUX_ML_DSA_SIMD_TRAITS_FIELD_MODULUS;
usr.bin/ssh/sntrup761.c
2091
static void HashSession(unsigned char *k, int b, const unsigned char *y, const unsigned char *z) {
usr.bin/ssh/sntrup761.c
2096
Hash_prefix(k, b, x, sizeof x);
usr.bin/ssh/sntrup761.c
2115
int crypto_kem_sntrup761_enc(unsigned char *c, unsigned char *k, const unsigned char *pk) {
usr.bin/ssh/sntrup761.c
2121
HashSession(k, 1, r_enc, c);
usr.bin/ssh/sntrup761.c
2132
int crypto_kem_sntrup761_dec(unsigned char *k, const unsigned char *c, const unsigned char *sk) {
usr.bin/ssh/sntrup761.c
2143
HashSession(k, 1 + mask, r_enc, c);
usr.bin/ssh/ssh-add.c
818
struct sshkey *k, **certs = NULL;
usr.bin/ssh/ssh-add.c
984
if ((r = sshkey_load_public(argv[i], &k, NULL)) != 0)
usr.bin/ssh/ssh-add.c
988
debug2("%s: %s", argv[i], sshkey_ssh_name(k));
usr.bin/ssh/ssh-add.c
989
certs[ncerts++] = k;
usr.bin/ssh/ssh-agent.c
1082
struct sshkey *k = NULL;
usr.bin/ssh/ssh-agent.c
1114
if ((r = sshkey_froms(b, &k)) != 0 ||
usr.bin/ssh/ssh-agent.c
1117
if ((fp = sshkey_fingerprint(k, SSH_FP_HASH_DEFAULT,
usr.bin/ssh/ssh-agent.c
1123
dch->hostname, key_is_ca ? "CA " : "", sshkey_type(k), fp);
usr.bin/ssh/ssh-agent.c
1125
dch->keys[dch->nkeys] = k;
usr.bin/ssh/ssh-agent.c
1128
k = NULL; /* transferred */
usr.bin/ssh/ssh-agent.c
1133
sshkey_free(k);
usr.bin/ssh/ssh-agent.c
1196
struct sshkey *k;
usr.bin/ssh/ssh-agent.c
1267
if ((r = sshkey_froms(b, &k)) != 0) {
usr.bin/ssh/ssh-agent.c
1271
(*certs)[(*ncerts)++] = k;
usr.bin/ssh/ssh-agent.c
1287
parse_key_constraints(struct sshbuf *m, struct sshkey *k, time_t *deathp,
usr.bin/ssh/ssh-agent.c
1352
struct sshkey *k = NULL;
usr.bin/ssh/ssh-agent.c
1356
if ((r = sshkey_private_deserialize(e->request, &k)) != 0 ||
usr.bin/ssh/ssh-agent.c
1357
k == NULL ||
usr.bin/ssh/ssh-agent.c
1362
if (parse_key_constraints(e->request, k, &death, &seconds, &confirm,
usr.bin/ssh/ssh-agent.c
1372
if (!sshkey_is_sk(k)) {
usr.bin/ssh/ssh-agent.c
1374
"authenticator-hosted key", sshkey_type(k));
usr.bin/ssh/ssh-agent.c
1402
if ((r = sshkey_shield_private(k)) != 0) {
usr.bin/ssh/ssh-agent.c
1408
if ((id = lookup_identity(k)) == NULL) {
usr.bin/ssh/ssh-agent.c
1425
id->key = k;
usr.bin/ssh/ssh-agent.c
1433
if ((fp = sshkey_fingerprint(k, SSH_FP_HASH_DEFAULT,
usr.bin/ssh/ssh-agent.c
1438
sshkey_ssh_name(k), fp, comment, seconds, confirm,
usr.bin/ssh/ssh-agent.c
1442
k = NULL;
usr.bin/ssh/ssh-agent.c
1451
sshkey_free(k);
usr.bin/ssh/ssh-agent.c
1559
struct sshkey **keys = NULL, *k;
usr.bin/ssh/ssh-agent.c
1608
if (pkcs11_make_cert(keys[i], certs[j], &k) != 0)
usr.bin/ssh/ssh-agent.c
1610
add_p11_identity(k, xstrdup(comments[i]),
usr.bin/ssh/ssh-ecdsa-sk.c
50
ssh_ecdsa_sk_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-ecdsa-sk.c
52
sshkey_sk_cleanup(k);
usr.bin/ssh/ssh-ecdsa-sk.c
53
sshkey_ecdsa_funcs.cleanup(k);
usr.bin/ssh/ssh-ecdsa.c
110
ssh_ecdsa_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-ecdsa.c
112
EVP_PKEY_free(k->pkey);
usr.bin/ssh/ssh-ecdsa.c
113
k->pkey = NULL;
usr.bin/ssh/ssh-ecdsa.c
157
ssh_ecdsa_generate(struct sshkey *k, int bits)
usr.bin/ssh/ssh-ecdsa.c
163
if ((k->ecdsa_nid = sshkey_ecdsa_bits_to_nid(bits)) == -1)
usr.bin/ssh/ssh-ecdsa.c
170
EVP_PKEY_CTX_set_ec_paramgen_curve_nid(ctx, k->ecdsa_nid) <= 0 ||
usr.bin/ssh/ssh-ecdsa.c
176
k->pkey = res;
usr.bin/ssh/ssh-ecdsa.c
42
sshkey_ecdsa_fixup_group(EVP_PKEY *k)
usr.bin/ssh/ssh-ecdsa.c
56
if ((ec = EVP_PKEY_get1_EC_KEY(k)) == NULL ||
usr.bin/ssh/ssh-ecdsa.c
84
EVP_PKEY_set1_EC_KEY(k, ec) != 1)
usr.bin/ssh/ssh-ed25519-sk.c
38
ssh_ed25519_sk_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-ed25519-sk.c
40
sshkey_sk_cleanup(k);
usr.bin/ssh/ssh-ed25519-sk.c
41
sshkey_ed25519_funcs.cleanup(k);
usr.bin/ssh/ssh-ed25519.c
33
ssh_ed25519_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-ed25519.c
35
freezero(k->ed25519_pk, ED25519_PK_SZ);
usr.bin/ssh/ssh-ed25519.c
36
freezero(k->ed25519_sk, ED25519_SK_SZ);
usr.bin/ssh/ssh-ed25519.c
37
k->ed25519_pk = NULL;
usr.bin/ssh/ssh-ed25519.c
38
k->ed25519_sk = NULL;
usr.bin/ssh/ssh-ed25519.c
79
ssh_ed25519_generate(struct sshkey *k, int bits)
usr.bin/ssh/ssh-ed25519.c
81
if ((k->ed25519_pk = malloc(ED25519_PK_SZ)) == NULL ||
usr.bin/ssh/ssh-ed25519.c
82
(k->ed25519_sk = malloc(ED25519_SK_SZ)) == NULL)
usr.bin/ssh/ssh-ed25519.c
84
if (crypto_sign_ed25519_keypair(k->ed25519_pk, k->ed25519_sk) != 0)
usr.bin/ssh/ssh-keygen.c
2431
struct sshkey *k;
usr.bin/ssh/ssh-keygen.c
2439
if ((r = sshkey_load_public(argv[i], &k, &comment)) != 0)
usr.bin/ssh/ssh-keygen.c
2441
r = ssh_krl_check_key(krl, k);
usr.bin/ssh/ssh-keygen.c
2447
sshkey_free(k);
usr.bin/ssh/ssh-keygen.c
320
do_convert_to_ssh2(struct passwd *pw, struct sshkey *k)
usr.bin/ssh/ssh-keygen.c
328
if ((r = sshkey_putb(k, b)) != 0)
usr.bin/ssh/ssh-keygen.c
336
sshkey_size(k), sshkey_type(k),
usr.bin/ssh/ssh-keygen.c
339
sshkey_free(k);
usr.bin/ssh/ssh-keygen.c
349
do_convert_to_pkcs8(struct sshkey *k)
usr.bin/ssh/ssh-keygen.c
351
switch (sshkey_type_plain(k->type)) {
usr.bin/ssh/ssh-keygen.c
354
EVP_PKEY_get0_RSA(k->pkey)))
usr.bin/ssh/ssh-keygen.c
359
EVP_PKEY_get0_EC_KEY(k->pkey)))
usr.bin/ssh/ssh-keygen.c
363
fatal_f("unsupported key type %s", sshkey_type(k));
usr.bin/ssh/ssh-keygen.c
368
do_convert_to_pem(struct sshkey *k)
usr.bin/ssh/ssh-keygen.c
370
switch (sshkey_type_plain(k->type)) {
usr.bin/ssh/ssh-keygen.c
373
EVP_PKEY_get0_RSA(k->pkey)))
usr.bin/ssh/ssh-keygen.c
378
EVP_PKEY_get0_EC_KEY(k->pkey)))
usr.bin/ssh/ssh-keygen.c
382
fatal_f("unsupported key type %s", sshkey_type(k));
usr.bin/ssh/ssh-keygen.c
389
struct sshkey *k;
usr.bin/ssh/ssh-keygen.c
397
if ((r = sshkey_load_public(identity_file, &k, NULL)) != 0)
usr.bin/ssh/ssh-keygen.c
398
k = load_identity(identity_file, NULL);
usr.bin/ssh/ssh-keygen.c
401
do_convert_to_ssh2(pw, k);
usr.bin/ssh/ssh-keygen.c
404
do_convert_to_pkcs8(k);
usr.bin/ssh/ssh-keygen.c
407
do_convert_to_pem(k);
usr.bin/ssh/ssh-keygen.c
590
do_convert_from_ssh2(struct passwd *pw, struct sshkey **k, int *private)
usr.bin/ssh/ssh-keygen.c
633
if ((*k = do_convert_private_ssh2(buf)) == NULL)
usr.bin/ssh/ssh-keygen.c
635
} else if ((r = sshkey_fromb(buf, k)) != 0)
usr.bin/ssh/ssh-keygen.c
642
do_convert_from_pkcs8(struct sshkey **k, int *private)
usr.bin/ssh/ssh-keygen.c
656
if ((*k = sshkey_new(KEY_UNSPEC)) == NULL)
usr.bin/ssh/ssh-keygen.c
658
(*k)->type = KEY_RSA;
usr.bin/ssh/ssh-keygen.c
659
(*k)->pkey = pubkey;
usr.bin/ssh/ssh-keygen.c
663
if ((*k = sshkey_new(KEY_UNSPEC)) == NULL)
usr.bin/ssh/ssh-keygen.c
665
if (((*k)->ecdsa_nid = sshkey_ecdsa_fixup_group(pubkey)) == -1)
usr.bin/ssh/ssh-keygen.c
667
(*k)->type = KEY_ECDSA;
usr.bin/ssh/ssh-keygen.c
668
(*k)->pkey = pubkey;
usr.bin/ssh/ssh-keygen.c
679
do_convert_from_pem(struct sshkey **k, int *private)
usr.bin/ssh/ssh-keygen.c
687
if ((*k = sshkey_new(KEY_UNSPEC)) == NULL)
usr.bin/ssh/ssh-keygen.c
689
if (((*k)->pkey = EVP_PKEY_new()) == NULL)
usr.bin/ssh/ssh-keygen.c
691
(*k)->type = KEY_RSA;
usr.bin/ssh/ssh-keygen.c
692
if (EVP_PKEY_set1_RSA((*k)->pkey, rsa) != 1)
usr.bin/ssh/ssh-keygen.c
704
struct sshkey *k = NULL;
usr.bin/ssh/ssh-keygen.c
715
do_convert_from_ssh2(pw, &k, &private);
usr.bin/ssh/ssh-keygen.c
718
do_convert_from_pkcs8(&k, &private);
usr.bin/ssh/ssh-keygen.c
721
do_convert_from_pem(&k, &private);
usr.bin/ssh/ssh-keygen.c
728
if ((r = sshkey_write(k, stdout)) == 0)
usr.bin/ssh/ssh-keygen.c
733
switch (k->type) {
usr.bin/ssh/ssh-keygen.c
736
EVP_PKEY_get0_EC_KEY(k->pkey), NULL, NULL, 0,
usr.bin/ssh/ssh-keygen.c
741
EVP_PKEY_get0_RSA(k->pkey), NULL, NULL, 0,
usr.bin/ssh/ssh-keygen.c
745
fatal_f("unsupported key type %s", sshkey_type(k));
usr.bin/ssh/ssh-keygen.c
751
sshkey_free(k);
usr.bin/ssh/ssh-mldsa-eddsa.c
240
ssh_mldsa44_ed25519_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-mldsa-eddsa.c
242
freezero(k->mldsa_ed25519_pk, MLDSA44_ED25519_PK_SZ);
usr.bin/ssh/ssh-mldsa-eddsa.c
243
freezero(k->mldsa_ed25519_sk, MLDSA44_ED25519_SK_SZ);
usr.bin/ssh/ssh-mldsa-eddsa.c
244
k->mldsa_ed25519_pk = NULL;
usr.bin/ssh/ssh-mldsa-eddsa.c
245
k->mldsa_ed25519_sk = NULL;
usr.bin/ssh/ssh-mldsa-eddsa.c
340
ssh_mldsa44_ed25519_generate(struct sshkey *k, int bits)
usr.bin/ssh/ssh-mldsa-eddsa.c
342
ssh_mldsa44_ed25519_cleanup(k);
usr.bin/ssh/ssh-mldsa-eddsa.c
343
if ((k->mldsa_ed25519_pk = malloc(MLDSA44_ED25519_PK_SZ)) == NULL ||
usr.bin/ssh/ssh-mldsa-eddsa.c
344
(k->mldsa_ed25519_sk = malloc(MLDSA44_ED25519_SK_SZ)) == NULL) {
usr.bin/ssh/ssh-mldsa-eddsa.c
345
ssh_mldsa44_ed25519_cleanup(k);
usr.bin/ssh/ssh-mldsa-eddsa.c
348
if (crypto_sign_mldsa44_ed25519_keygen(k->mldsa_ed25519_pk,
usr.bin/ssh/ssh-mldsa-eddsa.c
349
k->mldsa_ed25519_sk) != 0) {
usr.bin/ssh/ssh-mldsa-eddsa.c
350
ssh_mldsa44_ed25519_cleanup(k);
usr.bin/ssh/ssh-pkcs11-client.c
384
struct sshkey *k;
usr.bin/ssh/ssh-pkcs11-client.c
417
if ((r = sshkey_froms(msg, &k)) != 0 ||
usr.bin/ssh/ssh-pkcs11-client.c
420
k->flags |= SSHKEY_FLAG_EXT;
usr.bin/ssh/ssh-pkcs11-client.c
421
helper_add_key(helper, k);
usr.bin/ssh/ssh-pkcs11-client.c
422
(*keysp)[i] = k;
usr.bin/ssh/ssh-pkcs11.c
2085
struct sshkey *k = NULL;
usr.bin/ssh/ssh-pkcs11.c
2113
if ((k = pkcs11_rsa_generate_private_key(p, slotidx, label,
usr.bin/ssh/ssh-pkcs11.c
2120
if ((k = pkcs11_ecdsa_generate_private_key(p, slotidx, label,
usr.bin/ssh/ssh-pkcs11.c
2140
return (k);
usr.bin/ssh/ssh-pkcs11.c
2149
struct sshkey *k = NULL;
usr.bin/ssh/ssh-pkcs11.c
2221
k = pkcs11_fetch_rsa_pubkey(p, slotidx, &obj);
usr.bin/ssh/ssh-pkcs11.c
2224
k = pkcs11_fetch_ecdsa_pubkey(p, slotidx, &obj);
usr.bin/ssh/ssh-pkcs11.c
2227
k = pkcs11_fetch_ed25519_pubkey(p, slotidx, &obj);
usr.bin/ssh/ssh-pkcs11.c
2249
return (k);
usr.bin/ssh/ssh-rsa.c
114
ssh_rsa_generate(struct sshkey *k, int bits)
usr.bin/ssh/ssh-rsa.c
142
k->pkey = res;
usr.bin/ssh/ssh-rsa.c
33
ssh_rsa_size(const struct sshkey *k)
usr.bin/ssh/ssh-rsa.c
35
if (k->pkey == NULL)
usr.bin/ssh/ssh-rsa.c
37
return EVP_PKEY_bits(k->pkey);
usr.bin/ssh/ssh-rsa.c
41
ssh_rsa_alloc(struct sshkey *k)
usr.bin/ssh/ssh-rsa.c
43
if ((k->pkey = EVP_PKEY_new()) == NULL)
usr.bin/ssh/ssh-rsa.c
49
ssh_rsa_cleanup(struct sshkey *k)
usr.bin/ssh/ssh-rsa.c
51
EVP_PKEY_free(k->pkey);
usr.bin/ssh/ssh-rsa.c
52
k->pkey = NULL;
usr.bin/ssh/ssh.c
506
check_load(int r, struct sshkey **k, const char *path, const char *message)
usr.bin/ssh/ssh.c
512
if (k == NULL || *k == NULL)
usr.bin/ssh/ssh.c
515
if ((r = sshkey_check_rsa_length(*k,
usr.bin/ssh/ssh.c
518
free(*k);
usr.bin/ssh/ssh.c
519
*k = NULL;
usr.bin/ssh/ssh.c
522
if ((fp = sshkey_fingerprint(*k,
usr.bin/ssh/ssh.c
525
sshkey_type(*k), message, path);
usr.bin/ssh/ssh.c
528
sshkey_type(*k), fp);
usr.bin/ssh/ssh.c
543
if (k != NULL && *k == NULL)
usr.bin/ssh/ssh_api.c
159
struct key_entry *k;
usr.bin/ssh/ssh_api.c
168
while ((k = TAILQ_FIRST(&ssh->public_keys)) != NULL) {
usr.bin/ssh/ssh_api.c
169
TAILQ_REMOVE(&ssh->public_keys, k, next);
usr.bin/ssh/ssh_api.c
171
sshkey_free(k->key);
usr.bin/ssh/ssh_api.c
172
free(k);
usr.bin/ssh/ssh_api.c
174
while ((k = TAILQ_FIRST(&ssh->private_keys)) != NULL) {
usr.bin/ssh/ssh_api.c
175
TAILQ_REMOVE(&ssh->private_keys, k, next);
usr.bin/ssh/ssh_api.c
176
free(k);
usr.bin/ssh/ssh_api.c
199
struct key_entry *k = NULL, *k_prv = NULL;
usr.bin/ssh/ssh_api.c
205
if ((k = malloc(sizeof(*k))) == NULL ||
usr.bin/ssh/ssh_api.c
207
free(k);
usr.bin/ssh/ssh_api.c
215
k->key = pubkey;
usr.bin/ssh/ssh_api.c
216
TAILQ_INSERT_TAIL(&ssh->public_keys, k, next);
usr.bin/ssh/ssh_api.c
219
if ((k = malloc(sizeof(*k))) == NULL)
usr.bin/ssh/ssh_api.c
221
k->key = key;
usr.bin/ssh/ssh_api.c
222
TAILQ_INSERT_TAIL(&ssh->public_keys, k, next);
usr.bin/ssh/ssh_api.c
479
struct key_entry *k;
usr.bin/ssh/ssh_api.c
482
TAILQ_FOREACH(k, &ssh->public_keys, next) {
usr.bin/ssh/ssh_api.c
483
debug3_f("check %s", sshkey_type(k->key));
usr.bin/ssh/ssh_api.c
484
if (k->key->type == type &&
usr.bin/ssh/ssh_api.c
485
(type != KEY_ECDSA || k->key->ecdsa_nid == nid))
usr.bin/ssh/ssh_api.c
486
return (k->key);
usr.bin/ssh/ssh_api.c
494
struct key_entry *k;
usr.bin/ssh/ssh_api.c
497
TAILQ_FOREACH(k, &ssh->private_keys, next) {
usr.bin/ssh/ssh_api.c
498
debug3_f("check %s", sshkey_type(k->key));
usr.bin/ssh/ssh_api.c
499
if (k->key->type == type &&
usr.bin/ssh/ssh_api.c
500
(type != KEY_ECDSA || k->key->ecdsa_nid == nid))
usr.bin/ssh/ssh_api.c
501
return (k->key);
usr.bin/ssh/ssh_api.c
509
struct key_entry *k;
usr.bin/ssh/ssh_api.c
512
TAILQ_FOREACH(k, &ssh->public_keys, next) {
usr.bin/ssh/ssh_api.c
513
debug3_f("check %s", sshkey_type(k->key));
usr.bin/ssh/ssh_api.c
514
if (sshkey_equal_public(hostkey, k->key))
usr.bin/ssh/ssh_api.c
524
struct key_entry *k;
usr.bin/ssh/ssh_api.c
548
TAILQ_FOREACH(k, &ssh->public_keys, next) {
usr.bin/ssh/ssh_api.c
549
if (k->key->type != ktype &&
usr.bin/ssh/ssh_api.c
550
(!sshkey_is_cert(k->key) ||
usr.bin/ssh/ssh_api.c
551
k->key->type != sshkey_type_plain(ktype)))
usr.bin/ssh/ssh_api.c
553
if (sshkey_type_plain(k->key->type) == KEY_ECDSA &&
usr.bin/ssh/ssh_api.c
554
k->key->ecdsa_nid != nid)
usr.bin/ssh/sshd-auth.c
370
struct sshkey *k;
usr.bin/ssh/sshd-auth.c
382
k = NULL;
usr.bin/ssh/sshd-auth.c
385
if (len != 0 && (r = sshkey_from_blob(cp, len, &k)) != 0)
usr.bin/ssh/sshd-auth.c
387
host_pubkeys[num_keys] = k;
usr.bin/ssh/sshd-auth.c
388
if (k)
usr.bin/ssh/sshd-auth.c
389
debug2_f("key %u: %s", num_keys, sshkey_ssh_name(k));
usr.bin/ssh/sshd-auth.c
391
k = NULL;
usr.bin/ssh/sshd-auth.c
394
if (len != 0 && (r = sshkey_from_blob(cp, len, &k)) != 0)
usr.bin/ssh/sshd-auth.c
396
host_certificates[num_keys] = k;
usr.bin/ssh/sshd-auth.c
397
if (k)
usr.bin/ssh/sshd-auth.c
398
debug2_f("cert %u: %s", num_keys, sshkey_ssh_name(k));
usr.bin/ssh/sshd-session.c
557
struct sshkey *k;
usr.bin/ssh/sshd-session.c
575
k = NULL;
usr.bin/ssh/sshd-session.c
579
(r = sshkey_private_deserialize(kbuf, &k)) != 0)
usr.bin/ssh/sshd-session.c
581
sensitive_data.host_keys[num_keys] = k;
usr.bin/ssh/sshd-session.c
583
if (k)
usr.bin/ssh/sshd-session.c
584
debug2_f("privkey %u: %s", num_keys, sshkey_ssh_name(k));
usr.bin/ssh/sshd-session.c
586
k = NULL;
usr.bin/ssh/sshd-session.c
589
if (len != 0 && (r = sshkey_from_blob(cp, len, &k)) != 0)
usr.bin/ssh/sshd-session.c
591
sensitive_data.host_pubkeys[num_keys] = k;
usr.bin/ssh/sshd-session.c
592
if (k)
usr.bin/ssh/sshd-session.c
593
debug2_f("pubkey %u: %s", num_keys, sshkey_ssh_name(k));
usr.bin/ssh/sshd-session.c
595
k = NULL;
usr.bin/ssh/sshd-session.c
598
if (len != 0 && (r = sshkey_from_blob(cp, len, &k)) != 0)
usr.bin/ssh/sshd-session.c
600
sensitive_data.host_certificates[num_keys] = k;
usr.bin/ssh/sshd-session.c
601
if (k)
usr.bin/ssh/sshd-session.c
602
debug2_f("cert %u: %s", num_keys, sshkey_ssh_name(k));
usr.bin/ssh/sshkey.c
1105
const struct sshkey *k)
usr.bin/ssh/sshkey.c
1156
sshkey_type(k), sshkey_size(k));
usr.bin/ssh/sshkey.c
1159
r = snprintf(title, sizeof(title), "[%s]", sshkey_type(k));
usr.bin/ssh/sshkey.c
1201
sshkey_fingerprint(const struct sshkey *k, int dgst_alg,
usr.bin/ssh/sshkey.c
1208
if (sshkey_fingerprint_raw(k, dgst_alg, &dgst_raw, &dgst_raw_len) != 0)
usr.bin/ssh/sshkey.c
1233
dgst_raw, dgst_raw_len, k);
usr.bin/ssh/sshkey.c
1267
struct sshkey *k;
usr.bin/ssh/sshkey.c
1308
if ((r = sshkey_fromb(blob, &k)) != 0) {
usr.bin/ssh/sshkey.c
1319
if (k->type != type) {
usr.bin/ssh/sshkey.c
1320
sshkey_free(k);
usr.bin/ssh/sshkey.c
1323
if (key_type_is_ecdsa_variant(type) && curve_nid != k->ecdsa_nid) {
usr.bin/ssh/sshkey.c
1324
sshkey_free(k);
usr.bin/ssh/sshkey.c
1330
*ret = *k;
usr.bin/ssh/sshkey.c
1331
freezero(k, sizeof(*k));
usr.bin/ssh/sshkey.c
1408
sshkey_cert_type(const struct sshkey *k)
usr.bin/ssh/sshkey.c
1410
switch (k->cert->type) {
usr.bin/ssh/sshkey.c
1421
sshkey_check_rsa_length(const struct sshkey *k, int min_size)
usr.bin/ssh/sshkey.c
1426
if (k == NULL || k->pkey == NULL ||
usr.bin/ssh/sshkey.c
1427
(k->type != KEY_RSA && k->type != KEY_RSA_CERT))
usr.bin/ssh/sshkey.c
1429
nbits = EVP_PKEY_bits(k->pkey);
usr.bin/ssh/sshkey.c
1439
sshkey_ecdsa_key_to_nid(const EC_KEY *k)
usr.bin/ssh/sshkey.c
1444
if (k == NULL || (g = EC_KEY_get0_group(k)) == NULL)
usr.bin/ssh/sshkey.c
1461
struct sshkey *k;
usr.bin/ssh/sshkey.c
1472
if ((k = sshkey_new(KEY_UNSPEC)) == NULL)
usr.bin/ssh/sshkey.c
1474
k->type = type;
usr.bin/ssh/sshkey.c
1475
if ((ret = impl->funcs->generate(k, bits)) != 0) {
usr.bin/ssh/sshkey.c
1476
sshkey_free(k);
usr.bin/ssh/sshkey.c
1480
*keyp = k;
usr.bin/ssh/sshkey.c
1564
sshkey_from_private(const struct sshkey *k, struct sshkey **pkp)
usr.bin/ssh/sshkey.c
1571
if ((impl = sshkey_impl_from_key(k)) == NULL)
usr.bin/ssh/sshkey.c
1573
if ((n = sshkey_new(k->type)) == NULL) {
usr.bin/ssh/sshkey.c
1577
if ((r = impl->funcs->copy_public(k, n)) != 0)
usr.bin/ssh/sshkey.c
1579
if (sshkey_is_cert(k) && (r = sshkey_cert_copy(k, n)) != 0)
usr.bin/ssh/sshkey.c
1591
sshkey_is_shielded(struct sshkey *k)
usr.bin/ssh/sshkey.c
1593
return k != NULL && k->shielded_private != NULL;
usr.bin/ssh/sshkey.c
1597
sshkey_shield_private(struct sshkey *k)
usr.bin/ssh/sshkey.c
1608
fprintf(stderr, "%s: entering for %s\n", __func__, sshkey_ssh_name(k));
usr.bin/ssh/sshkey.c
1642
if (sshkey_is_shielded(k) && (r = sshkey_unshield_private(k)) != 0)
usr.bin/ssh/sshkey.c
1644
if ((r = sshkey_private_serialize(k, prvbuf)) != 0)
usr.bin/ssh/sshkey.c
165
sshkey_impl_from_key(const struct sshkey *k)
usr.bin/ssh/sshkey.c
167
if (k == NULL)
usr.bin/ssh/sshkey.c
1671
if ((r = sshkey_from_private(k, &kswap)) != 0)
usr.bin/ssh/sshkey.c
1676
*kswap = *k;
usr.bin/ssh/sshkey.c
1677
*k = tmp;
usr.bin/ssh/sshkey.c
1680
k->shielded_private = enc;
usr.bin/ssh/sshkey.c
1681
k->shielded_len = enclen;
usr.bin/ssh/sshkey.c
1682
k->shield_prekey = prekey;
usr.bin/ssh/sshkey.c
1683
k->shield_prekey_len = SSHKEY_SHIELD_PREKEY_LEN;
usr.bin/ssh/sshkey.c
1688
k->sk_flags = kswap->sk_flags;
usr.bin/ssh/sshkey.c
169
return sshkey_impl_from_type_nid(k->type, k->ecdsa_nid);
usr.bin/ssh/sshkey.c
173
sshkey_type(const struct sshkey *k)
usr.bin/ssh/sshkey.c
1731
sshkey_unshield_private(struct sshkey *k)
usr.bin/ssh/sshkey.c
1741
fprintf(stderr, "%s: entering for %s\n", __func__, sshkey_ssh_name(k));
usr.bin/ssh/sshkey.c
1743
if (!sshkey_is_shielded(k))
usr.bin/ssh/sshkey.c
1756
if (k->shielded_len < cipher_blocksize(cipher) ||
usr.bin/ssh/sshkey.c
1757
(k->shielded_len % cipher_blocksize(cipher)) != 0) {
usr.bin/ssh/sshkey.c
1764
k->shield_prekey, k->shield_prekey_len,
usr.bin/ssh/sshkey.c
177
if ((impl = sshkey_impl_from_key(k)) == NULL)
usr.bin/ssh/sshkey.c
1781
if ((r = sshbuf_reserve(prvbuf, k->shielded_len, &cp)) != 0)
usr.bin/ssh/sshkey.c
1786
sshbuf_dump_data(k->shielded_private, k->shielded_len, stderr);
usr.bin/ssh/sshkey.c
1789
k->shielded_private, k->shielded_len, 0, 0)) != 0)
usr.bin/ssh/sshkey.c
1804
*kswap = *k;
usr.bin/ssh/sshkey.c
1805
*k = tmp;
usr.bin/ssh/sshkey.c
203
sshkey_ssh_name(const struct sshkey *k)
usr.bin/ssh/sshkey.c
205
return sshkey_ssh_name_from_type_nid(k->type, k->ecdsa_nid);
usr.bin/ssh/sshkey.c
209
sshkey_ssh_name_plain(const struct sshkey *k)
usr.bin/ssh/sshkey.c
211
return sshkey_ssh_name_from_type_nid(sshkey_type_plain(k->type),
usr.bin/ssh/sshkey.c
212
k->ecdsa_nid);
usr.bin/ssh/sshkey.c
2208
sshkey_to_certified(struct sshkey *k)
usr.bin/ssh/sshkey.c
2212
if ((newtype = sshkey_type_certified(k->type)) == -1)
usr.bin/ssh/sshkey.c
2214
if ((k->cert = cert_new()) == NULL)
usr.bin/ssh/sshkey.c
2216
k->type = newtype;
usr.bin/ssh/sshkey.c
2222
sshkey_drop_cert(struct sshkey *k)
usr.bin/ssh/sshkey.c
2224
if (!sshkey_type_is_cert(k->type))
usr.bin/ssh/sshkey.c
2226
cert_free(k->cert);
usr.bin/ssh/sshkey.c
2227
k->cert = NULL;
usr.bin/ssh/sshkey.c
2228
k->type = sshkey_type_plain(k->type);
usr.bin/ssh/sshkey.c
2234
sshkey_certify_custom(struct sshkey *k, struct sshkey *ca, const char *alg,
usr.bin/ssh/sshkey.c
2246
if (k == NULL || k->cert == NULL ||
usr.bin/ssh/sshkey.c
2247
k->cert->certblob == NULL || ca == NULL)
usr.bin/ssh/sshkey.c
2249
if (!sshkey_is_cert(k))
usr.bin/ssh/sshkey.c
2253
if ((impl = sshkey_impl_from_key(k)) == NULL)
usr.bin/ssh/sshkey.c
2261
alg = k->cert->signature_type;
usr.bin/ssh/sshkey.c
2262
else if (k->cert->signature_type != NULL &&
usr.bin/ssh/sshkey.c
2263
strcmp(alg, k->cert->signature_type) != 0)
usr.bin/ssh/sshkey.c
2276
cert = k->cert->certblob; /* for readability */
usr.bin/ssh/sshkey.c
2278
if ((ret = sshbuf_put_cstring(cert, sshkey_ssh_name(k))) != 0)
usr.bin/ssh/sshkey.c
2287
if ((ret = impl->funcs->serialize_public(k, cert,
usr.bin/ssh/sshkey.c
2292
if ((ret = sshbuf_put_u64(cert, k->cert->serial)) != 0 ||
usr.bin/ssh/sshkey.c
2293
(ret = sshbuf_put_u32(cert, k->cert->type)) != 0 ||
usr.bin/ssh/sshkey.c
2294
(ret = sshbuf_put_cstring(cert, k->cert->key_id)) != 0)
usr.bin/ssh/sshkey.c
2301
for (i = 0; i < k->cert->nprincipals; i++) {
usr.bin/ssh/sshkey.c
2303
k->cert->principals[i])) != 0)
usr.bin/ssh/sshkey.c
2307
(ret = sshbuf_put_u64(cert, k->cert->valid_after)) != 0 ||
usr.bin/ssh/sshkey.c
2308
(ret = sshbuf_put_u64(cert, k->cert->valid_before)) != 0 ||
usr.bin/ssh/sshkey.c
2309
(ret = sshbuf_put_stringb(cert, k->cert->critical)) != 0 ||
usr.bin/ssh/sshkey.c
2310
(ret = sshbuf_put_stringb(cert, k->cert->extensions)) != 0 ||
usr.bin/ssh/sshkey.c
2326
if (k->cert->signature_type == NULL) {
usr.bin/ssh/sshkey.c
2327
k->cert->signature_type = sigtype;
usr.bin/ssh/sshkey.c
2357
sshkey_certify(struct sshkey *k, struct sshkey *ca, const char *alg,
usr.bin/ssh/sshkey.c
2360
return sshkey_certify_custom(k, ca, alg, sk_provider, sk_pin,
usr.bin/ssh/sshkey.c
2365
sshkey_cert_check_authority(const struct sshkey *k,
usr.bin/ssh/sshkey.c
2373
if (!sshkey_is_cert(k)) {
usr.bin/ssh/sshkey.c
2378
if (k->cert->type != SSH2_CERT_TYPE_HOST) {
usr.bin/ssh/sshkey.c
2383
if (k->cert->type != SSH2_CERT_TYPE_USER) {
usr.bin/ssh/sshkey.c
2388
if (verify_time < k->cert->valid_after) {
usr.bin/ssh/sshkey.c
2392
if (verify_time >= k->cert->valid_before) {
usr.bin/ssh/sshkey.c
2396
if (k->cert->nprincipals == 0) {
usr.bin/ssh/sshkey.c
2404
for (i = 0; i < k->cert->nprincipals; i++) {
usr.bin/ssh/sshkey.c
2406
if (match_pattern(name, k->cert->principals[i])) {
usr.bin/ssh/sshkey.c
2410
} else if (strcmp(name, k->cert->principals[i]) == 0) {
usr.bin/ssh/sshkey.c
2424
sshkey_cert_check_authority_now(const struct sshkey *k,
usr.bin/ssh/sshkey.c
2435
return sshkey_cert_check_authority(k, want_host, wildcard_pattern,
usr.bin/ssh/sshkey.c
2553
sshkey_private_deserialize_sk(struct sshbuf *buf, struct sshkey *k)
usr.bin/ssh/sshkey.c
2557
if ((k->sk_key_handle = sshbuf_new()) == NULL ||
usr.bin/ssh/sshkey.c
2558
(k->sk_reserved = sshbuf_new()) == NULL)
usr.bin/ssh/sshkey.c
2560
if ((r = sshbuf_get_cstring(buf, &k->sk_application, NULL)) != 0 ||
usr.bin/ssh/sshkey.c
2561
(r = sshbuf_get_u8(buf, &k->sk_flags)) != 0 ||
usr.bin/ssh/sshkey.c
2562
(r = sshbuf_get_stringb(buf, k->sk_key_handle)) != 0 ||
usr.bin/ssh/sshkey.c
2563
(r = sshbuf_get_stringb(buf, k->sk_reserved)) != 0)
usr.bin/ssh/sshkey.c
2576
struct sshkey *k = NULL;
usr.bin/ssh/sshkey.c
2590
if ((r = sshkey_froms(buf, &k)) != 0)
usr.bin/ssh/sshkey.c
2592
if (k->type != type) {
usr.bin/ssh/sshkey.c
2597
if (k->type == KEY_ECDSA &&
usr.bin/ssh/sshkey.c
2598
k->ecdsa_nid != sshkey_ecdsa_nid_from_name(tname)) {
usr.bin/ssh/sshkey.c
2606
expect_sk_application = k->sk_application;
usr.bin/ssh/sshkey.c
2607
expect_ed25519_pk = k->ed25519_pk;
usr.bin/ssh/sshkey.c
2608
k->sk_application = NULL;
usr.bin/ssh/sshkey.c
2609
k->ed25519_pk = NULL;
usr.bin/ssh/sshkey.c
2611
if ((k = sshkey_new(type)) == NULL) {
usr.bin/ssh/sshkey.c
2620
if ((r = impl->funcs->deserialize_private(tname, buf, k)) != 0)
usr.bin/ssh/sshkey.c
2623
if ((expect_sk_application != NULL && (k->sk_application == NULL ||
usr.bin/ssh/sshkey.c
2624
strcmp(expect_sk_application, k->sk_application) != 0)) ||
usr.bin/ssh/sshkey.c
2625
(expect_ed25519_pk != NULL && (k->ed25519_pk == NULL ||
usr.bin/ssh/sshkey.c
2626
memcmp(expect_ed25519_pk, k->ed25519_pk, ED25519_PK_SZ) != 0))) {
usr.bin/ssh/sshkey.c
2633
*kp = k;
usr.bin/ssh/sshkey.c
2634
k = NULL;
usr.bin/ssh/sshkey.c
2638
sshkey_free(k);
usr.bin/ssh/sshkey.c
3137
struct sshkey *k = NULL, *pubkey = NULL;
usr.bin/ssh/sshkey.c
3157
if ((r = sshkey_private_deserialize(decrypted, &k)) != 0 ||
usr.bin/ssh/sshkey.c
3166
if (!sshkey_equal(pubkey, k)) {
usr.bin/ssh/sshkey.c
3174
*keyp = k;
usr.bin/ssh/sshkey.c
3175
k = NULL;
usr.bin/ssh/sshkey.c
3185
sshkey_free(k);
usr.bin/ssh/sshkey.c
372
sshkey_size(const struct sshkey *k)
usr.bin/ssh/sshkey.c
376
if ((impl = sshkey_impl_from_key(k)) == NULL)
usr.bin/ssh/sshkey.c
379
return impl->funcs->size(k);
usr.bin/ssh/sshkey.c
395
sshkey_is_cert(const struct sshkey *k)
usr.bin/ssh/sshkey.c
397
if (k == NULL)
usr.bin/ssh/sshkey.c
399
return sshkey_type_is_cert(k->type);
usr.bin/ssh/sshkey.c
403
sshkey_is_sk(const struct sshkey *k)
usr.bin/ssh/sshkey.c
405
if (k == NULL)
usr.bin/ssh/sshkey.c
407
switch (sshkey_type_plain(k->type)) {
usr.bin/ssh/sshkey.c
672
struct sshkey *k;
usr.bin/ssh/sshkey.c
680
if ((k = calloc(1, sizeof(*k))) == NULL)
usr.bin/ssh/sshkey.c
682
k->type = type;
usr.bin/ssh/sshkey.c
683
k->ecdsa_nid = -1;
usr.bin/ssh/sshkey.c
685
if (impl->funcs->alloc(k) != 0) {
usr.bin/ssh/sshkey.c
686
free(k);
usr.bin/ssh/sshkey.c
690
if (sshkey_is_cert(k)) {
usr.bin/ssh/sshkey.c
691
if ((k->cert = cert_new()) == NULL) {
usr.bin/ssh/sshkey.c
692
sshkey_free(k);
usr.bin/ssh/sshkey.c
697
return k;
usr.bin/ssh/sshkey.c
702
sshkey_sk_cleanup(struct sshkey *k)
usr.bin/ssh/sshkey.c
704
free(k->sk_application);
usr.bin/ssh/sshkey.c
705
sshbuf_free(k->sk_key_handle);
usr.bin/ssh/sshkey.c
706
sshbuf_free(k->sk_reserved);
usr.bin/ssh/sshkey.c
707
k->sk_application = NULL;
usr.bin/ssh/sshkey.c
708
k->sk_key_handle = k->sk_reserved = NULL;
usr.bin/ssh/sshkey.c
733
sshkey_free_contents(struct sshkey *k)
usr.bin/ssh/sshkey.c
737
if (k == NULL)
usr.bin/ssh/sshkey.c
739
if ((k->flags & SSHKEY_FLAG_EXT) != 0)
usr.bin/ssh/sshkey.c
740
pkcs11_key_free(k);
usr.bin/ssh/sshkey.c
741
if ((impl = sshkey_impl_from_type(k->type)) != NULL &&
usr.bin/ssh/sshkey.c
743
impl->funcs->cleanup(k);
usr.bin/ssh/sshkey.c
744
if (sshkey_is_cert(k))
usr.bin/ssh/sshkey.c
745
cert_free(k->cert);
usr.bin/ssh/sshkey.c
746
freezero(k->shielded_private, k->shielded_len);
usr.bin/ssh/sshkey.c
747
sshkey_prekey_free(k->shield_prekey, k->shield_prekey_len);
usr.bin/ssh/sshkey.c
751
sshkey_free(struct sshkey *k)
usr.bin/ssh/sshkey.c
753
sshkey_free_contents(k);
usr.bin/ssh/sshkey.c
754
freezero(k, sizeof(*k));
usr.bin/ssh/sshkey.c
942
sshkey_fingerprint_raw(const struct sshkey *k, int dgst_alg,
usr.bin/ssh/sshkey.c
957
if ((r = to_blob(k, &blob, &blob_len, 1, SSHKEY_SERIALIZE_DEFAULT))
usr.bin/ssh/sshkey.h
191
int sshkey_fingerprint_raw(const struct sshkey *k,
usr.bin/ssh/sshkey.h
306
int sshkey_ecdsa_fixup_group(EVP_PKEY *k); /* ssh-ecdsa.c */
usr.bin/ssh/sshkey.h
311
void sshkey_sk_cleanup(struct sshkey *k);
usr.bin/ssh/sshkey.h
317
int sshkey_private_deserialize_sk(struct sshbuf *buf, struct sshkey *k);
usr.bin/ssh/umac.c
335
UINT32 *k = (UINT32 *)kp;
usr.bin/ssh/umac.c
346
k0 = *(k+0); k1 = *(k+1); k2 = *(k+2); k3 = *(k+3);
usr.bin/ssh/umac.c
347
k4 = *(k+4); k5 = *(k+5); k6 = *(k+6); k7 = *(k+7);
usr.bin/ssh/umac.c
354
k += 8;
usr.bin/ssh/umac.c
368
UINT32 *k = (UINT32 *)kp;
usr.bin/ssh/umac.c
376
k0 = *(k+0); k1 = *(k+1); k2 = *(k+2); k3 = *(k+3);
usr.bin/ssh/umac.c
382
k4 = *(k+4); k5 = *(k+5); k6 = *(k+6); k7 = *(k+7);
usr.bin/ssh/umac.c
383
k8 = *(k+8); k9 = *(k+9); k10 = *(k+10); k11 = *(k+11);
usr.bin/ssh/umac.c
400
k += 8;
usr.bin/ssh/umac.c
415
UINT32 *k = (UINT32 *)kp;
usr.bin/ssh/umac.c
424
k0 = *(k+0); k1 = *(k+1); k2 = *(k+2); k3 = *(k+3);
usr.bin/ssh/umac.c
425
k4 = *(k+4); k5 = *(k+5); k6 = *(k+6); k7 = *(k+7);
usr.bin/ssh/umac.c
431
k8 = *(k+8); k9 = *(k+9); k10 = *(k+10); k11 = *(k+11);
usr.bin/ssh/umac.c
432
k12 = *(k+12); k13 = *(k+13); k14 = *(k+14); k15 = *(k+15);
usr.bin/ssh/umac.c
454
k += 8;
usr.bin/ssh/umac.c
470
UINT32 *k = (UINT32 *)kp;
usr.bin/ssh/umac.c
481
k0 = *(k+0); k1 = *(k+1); k2 = *(k+2); k3 = *(k+3);
usr.bin/ssh/umac.c
482
k4 = *(k+4); k5 = *(k+5); k6 = *(k+6); k7 = *(k+7);
usr.bin/ssh/umac.c
488
k8 = *(k+8); k9 = *(k+9); k10 = *(k+10); k11 = *(k+11);
usr.bin/ssh/umac.c
489
k12 = *(k+12); k13 = *(k+13); k14 = *(k+14); k15 = *(k+15);
usr.bin/ssh/umac.c
490
k16 = *(k+16); k17 = *(k+17); k18 = *(k+18); k19 = *(k+19);
usr.bin/ssh/umac.c
517
k += 8;
usr.bin/systat/malloc.c
284
int i, j, k, mib[4];
usr.bin/systat/malloc.c
312
for (k = 0; k < MAX_BUCKETS; k++, j <<= 1)
usr.bin/systat/malloc.c
313
ti->buckets[k] = (ti->stats.ks_size & j) ? '|' : '.';
usr.bin/systat/malloc.c
36
void showtype(int k);
usr.bin/systat/malloc.c
363
showbucket(int k)
usr.bin/systat/malloc.c
365
struct kmembuckets *kp = buckets + k;
usr.bin/systat/malloc.c
367
if (k < 0 || k >= num_buckets)
usr.bin/systat/malloc.c
37
void showbucket(int k);
usr.bin/systat/malloc.c
370
print_fld_size(FLD_BUCKET_SIZE, bucket_sizes[k]);
usr.bin/systat/malloc.c
382
showtype(int k)
usr.bin/systat/malloc.c
384
struct type_info *t = types + k;
usr.bin/systat/malloc.c
386
if (k < 0 || k >= num_types)
usr.bin/systat/pigs.c
156
int i, k;
usr.bin/systat/pigs.c
201
for (k = 0; k < nproc + 1; k++) {
usr.bin/systat/pigs.c
202
int j = pb_indices[k];
usr.bin/systat/pigs.c
254
showpigs(int k)
usr.bin/systat/pigs.c
263
value = pctdouble(procbase[k].p_pctcpu) * 100;
usr.bin/systat/pigs.c
265
kp = &procbase[k];
usr.bin/systat/pigs.c
58
void showpigs(int k);
usr.bin/systat/pool.c
402
showpool(int k)
usr.bin/systat/pool.c
404
struct pool_info *p = pools + k;
usr.bin/systat/pool.c
406
if (k < 0 || k >= num_pools)
usr.bin/systat/pool.c
46
void showpool(int k);
usr.bin/telnet/utilities.c
471
int j, k;
usr.bin/telnet/utilities.c
514
j = k = i;
usr.bin/telnet/utilities.c
524
pointer[k++] = pointer[j++];
usr.bin/telnet/utilities.c
526
printsub(0, &pointer[i], k - i);
usr.bin/tic/tic.c
1354
int j, k;
usr.bin/tic/tic.c
1360
for (k = 0; k < j; ++k) {
usr.bin/tic/tic.c
1361
if (!strcmp(list[j], list[k])) {
usr.bin/tic/tic.c
1362
char *value = _nc_tic_expand(list[k], TRUE, 0);
usr.bin/tic/tic.c
1599
int k;
usr.bin/tic/tic.c
1603
for (k = 0, kk = -1, test = 100; k < 5; ++k) {
usr.bin/tic/tic.c
1604
if (list[k] > last &&
usr.bin/tic/tic.c
1605
list[k] < test) {
usr.bin/tic/tic.c
1606
test = list[k];
usr.bin/tic/tic.c
1607
kk = k;
usr.bin/tic/tic.c
2246
int k;
usr.bin/tic/tic.c
2259
for (k = 1; k <= NUM_PARM; k++) {
usr.bin/tic/tic.c
2260
numbers[k] = count;
usr.bin/tic/tic.c
2264
strings[k] = next;
usr.bin/tic/tic.c
2758
unsigned j, k;
usr.bin/tic/tic.c
2771
for (k = j + 1; given[k].keycode; k++) {
usr.bin/tic/tic.c
2772
const char *b = given[k].value;
usr.bin/tic/tic.c
2776
if (check[k])
usr.bin/tic/tic.c
2781
check[k] = 1;
usr.bin/tic/tic.c
2790
show_fkey_name(given + k);
usr.bin/tic/tic.c
2794
show_fkey_name(given + k);
usr.bin/tic/tic.c
2835
for (k = 0; table[k].xcurses; ++k) {
usr.bin/tic/tic.c
2836
const char *test = table[k].xcurses;
usr.bin/tic/tic.c
2844
(table[k].shifted
usr.bin/tic/tic.c
2845
? table[k].shifted
usr.bin/tmux/colour.c
1178
double c, m, y, k = 0;
usr.bin/tmux/colour.c
1192
else if ((sscanf(p, "cmyk:%lf/%lf/%lf/%lf", &c, &m, &y, &k) == 4 ||
usr.bin/tmux/colour.c
1195
y >= 0 && y <= 1 && k >= 0 && k <= 1) {
usr.bin/tmux/colour.c
1197
(1 - c) * (1 - k) * 255,
usr.bin/tmux/colour.c
1198
(1 - m) * (1 - k) * 255,
usr.bin/tmux/colour.c
1199
(1 - y) * (1 - k) * 255);
usr.bin/tmux/tmux.h
156
#define KEYC_IS_TYPE(k, t) (((k) & KEYC_MASK_TYPE) == KEYC_SHIFT_TYPE(t))
usr.bin/tmux/window-tree.c
815
u_int cx = s->cx, cy = s->cy, i, j, k;
usr.bin/tmux/window-tree.c
858
for (k = 0; k < count[j]; k++) {
usr.bin/tmux/window-tree.c
861
expanded = format_expand(ft, lines[j][k]);
usr.bin/tput/tput.c
239
int k;
usr.bin/tput/tput.c
254
for (k = 1; (k < argc) && (k <= NUM_PARM); k++) {
usr.bin/tput/tput.c
256
strings[k] = argv[k];
usr.bin/tput/tput.c
257
numbers[k] = strtol(argv[k], &tmp, 0);
usr.bin/tput/tput.c
259
numbers[k] = 0;
usr.bin/tput/tput.c
261
for (k = argc; k <= NUM_PARM; k++) {
usr.bin/tput/tput.c
262
numbers[k] = 0;
usr.bin/tput/tput.c
263
strings[k] = 0;
usr.bin/tsort/tsort.c
104
char k[1]; /* Name of this node. */
usr.bin/tsort/tsort.c
155
offsetof(struct node, k), NULL, hash_calloc, hash_free, entry_alloc };
usr.bin/tsort/tsort.c
253
printf("%s (%u/%u): ", n->k, n->order, n->refs);
usr.bin/tsort/tsort.c
256
printf("%s(%u/%u) ", l->node->k, l->node->order, l->node->refs);
usr.bin/tsort/tsort.c
388
a->k, name);
usr.bin/tsort/tsort.c
428
warnx("node %s absent from hints file", h->t[i]->k);
usr.bin/tsort/tsort.c
698
printf("%s(%u) ", n->k, n->mark);
usr.bin/tsort/tsort.c
760
warnx("%s", c->t[i]->k);
usr.bin/tsort/tsort.c
945
printf("%s\n", n->k);
usr.bin/vi/common/key.c
304
KEYLIST k, *kp;
usr.bin/vi/common/key.c
306
k.ch = ch;
usr.bin/vi/common/key.c
307
kp = bsearch(&k, keylist, nkeylist, sizeof(keylist[0]), v_key_cmp);
usr.bin/yacc/closure.c
101
k = 0;
usr.bin/yacc/closure.c
104
if (cword & (1 << k))
usr.bin/yacc/closure.c
150
unsigned int k, cword = 0;
usr.bin/yacc/closure.c
163
k = BITS_PER_WORD;
usr.bin/yacc/closure.c
164
for (j = start_symbol; j < nsyms; k++, j++) {
usr.bin/yacc/closure.c
165
if (k >= BITS_PER_WORD) {
usr.bin/yacc/closure.c
167
k = 0;
usr.bin/yacc/closure.c
170
if (cword & (1 << k)) {
usr.bin/yacc/closure.c
63
unsigned int k, word;
usr.bin/yacc/closure.c
72
k = BITS_PER_WORD;
usr.bin/yacc/closure.c
73
for (j = 0; j < nvars; k++, j++) {
usr.bin/yacc/closure.c
74
if (k >= BITS_PER_WORD) {
usr.bin/yacc/closure.c
76
k = 0;
usr.bin/yacc/closure.c
79
if (word & (1 << k))
usr.bin/yacc/closure.c
90
unsigned int k, cword = 0;
usr.bin/yacc/closure.c
97
k = BITS_PER_WORD;
usr.bin/yacc/closure.c
98
for (j = 0; j <= nrules; k++, j++) {
usr.bin/yacc/closure.c
99
if (k >= BITS_PER_WORD) {
usr.bin/yacc/lalr.c
173
int i, j, k;
usr.bin/yacc/lalr.c
178
k = 0;
usr.bin/yacc/lalr.c
180
lookaheads[i] = k;
usr.bin/yacc/lalr.c
183
k += rp->nreds;
usr.bin/yacc/lalr.c
185
lookaheads[nstates] = k;
usr.bin/yacc/lalr.c
187
LA = NEW2(k * tokensetsize, unsigned);
usr.bin/yacc/lalr.c
188
LAruleno = NEW2(k, short);
usr.bin/yacc/lalr.c
189
lookback = NEW2(k, shorts *);
usr.bin/yacc/lalr.c
191
k = 0;
usr.bin/yacc/lalr.c
196
LAruleno[k] = rp->rules[j];
usr.bin/yacc/lalr.c
197
k++;
usr.bin/yacc/lalr.c
207
int i, k, symbol;
usr.bin/yacc/lalr.c
229
k = 0;
usr.bin/yacc/lalr.c
231
temp_map[i] = k;
usr.bin/yacc/lalr.c
232
k += goto_map[i];
usr.bin/yacc/lalr.c
252
k = temp_map[symbol]++;
usr.bin/yacc/lalr.c
253
from_state[k] = state1;
usr.bin/yacc/lalr.c
254
to_state[k] = state2;
usr.bin/yacc/lalr.c
290
int i, j, k;
usr.bin/yacc/lalr.c
309
k = sp->nshifts;
usr.bin/yacc/lalr.c
311
for (j = 0; j < k; j++) {
usr.bin/yacc/lalr.c
318
for (; j < k; j++) {
usr.bin/yacc/lalr.c
352
int i, j, k;
usr.bin/yacc/lalr.c
377
k = sp->nshifts;
usr.bin/yacc/lalr.c
379
for (j = 0; j < k; j++) {
usr.bin/yacc/lalr.c
428
int i, k, found;
usr.bin/yacc/lalr.c
432
k = lookaheads[stateno + 1];
usr.bin/yacc/lalr.c
434
while (!found && i < k) {
usr.bin/yacc/lalr.c
454
int i, k;
usr.bin/yacc/lalr.c
470
k = nedges[i];
usr.bin/yacc/lalr.c
471
if (k > 0) {
usr.bin/yacc/lalr.c
472
sp = NEW2(k + 1, short);
usr.bin/yacc/lalr.c
475
sp[k] = -1;
usr.bin/yacc/lr0.c
399
int i, k, lhs;
usr.bin/yacc/lr0.c
405
k = 0;
usr.bin/yacc/lr0.c
407
derives[lhs] = rules + k;
usr.bin/yacc/lr0.c
410
rules[k] = i;
usr.bin/yacc/lr0.c
411
k++;
usr.bin/yacc/lr0.c
414
rules[k] = -1;
usr.bin/yacc/lr0.c
415
k++;
usr.bin/yacc/mkpar.c
102
int i, k;
usr.bin/yacc/mkpar.c
110
k = tto_state[i];
usr.bin/yacc/mkpar.c
111
symbol = accessing_symbol[k];
usr.bin/yacc/mkpar.c
116
temp->number = k;
usr.bin/yacc/output.c
348
int i, j, k;
usr.bin/yacc/output.c
352
k = default_goto(start_symbol + 1);
usr.bin/yacc/output.c
354
"\t{%40d,", symbol_prefix, k);
usr.bin/yacc/output.c
355
save_column(start_symbol + 1, k);
usr.bin/yacc/output.c
367
k = default_goto(i);
usr.bin/yacc/output.c
368
fprintf(output_file, "%5d,", k);
usr.bin/yacc/output.c
369
save_column(i, k);
usr.bin/yacc/output.c
456
int k;
usr.bin/yacc/output.c
476
for (k = nentries - 1; k > j; k--)
usr.bin/yacc/output.c
477
order[k + 1] = order[k];
usr.bin/yacc/output.c
548
int i, j, k, t, w, match, prev;
usr.bin/yacc/output.c
563
for (k = 0; match && k < t; k++) {
usr.bin/yacc/output.c
564
if (tos[j][k] != tos[i][k] ||
usr.bin/yacc/output.c
565
froms[j][k] != froms[i][k])
usr.bin/yacc/output.c
581
int i, j, k, l;
usr.bin/yacc/output.c
594
for (k = 1; k < t; ++k)
usr.bin/yacc/output.c
595
if (lowzero - from[k] > j)
usr.bin/yacc/output.c
596
j = lowzero - from[k];
usr.bin/yacc/output.c
601
for (k = 0; ok && k < t; k++) {
usr.bin/yacc/output.c
602
loc = j + from[k];
usr.bin/yacc/output.c
627
for (k = 0; ok && k < vector; k++) {
usr.bin/yacc/output.c
628
if (pos[k] == j)
usr.bin/yacc/output.c
632
for (k = 0; k < t; k++) {
usr.bin/yacc/output.c
633
loc = j + from[k];
usr.bin/yacc/output.c
634
table[loc] = to[k];
usr.bin/yacc/output.c
635
check[loc] = from[k];
usr.bin/yacc/output.c
873
int i, j, k, max;
usr.bin/yacc/output.c
910
k = 7;
usr.bin/yacc/output.c
912
++k;
usr.bin/yacc/output.c
914
k += 2;
usr.bin/yacc/output.c
916
++k;
usr.bin/yacc/output.c
919
j += k;
usr.bin/yacc/output.c
924
j = k;
usr.bin/yacc/output.c
950
k = 5;
usr.bin/yacc/output.c
952
++k;
usr.bin/yacc/output.c
954
k += 2;
usr.bin/yacc/output.c
956
++k;
usr.bin/yacc/output.c
959
j += k;
usr.bin/yacc/output.c
964
j = k;
usr.bin/yacc/output.c
981
k = strlen(s) + 3;
usr.bin/yacc/output.c
982
j += k;
usr.bin/yacc/output.c
987
j = k;
usr.bin/yacc/reader.c
1036
int c, k;
usr.bin/yacc/reader.c
1049
switch (k = keyword()) {
usr.bin/yacc/reader.c
1069
declare_tokens(k);
usr.bin/yacc/reader.c
1073
declare_expect(k);
usr.bin/yacc/reader.c
1630
int i, j, k, n;
usr.bin/yacc/reader.c
1676
k = start_symbol + 2;
usr.bin/yacc/reader.c
1679
v[i]->index = k;
usr.bin/yacc/reader.c
1680
++k;
usr.bin/yacc/reader.c
1683
k = 1;
usr.bin/yacc/reader.c
1686
v[i]->value = k;
usr.bin/yacc/reader.c
1687
++k;
usr.bin/yacc/reader.c
1691
k = 0;
usr.bin/yacc/reader.c
1695
for (j = k++; j > 0 && symbol_value[j - 1] > n; --j)
usr.bin/yacc/reader.c
1708
while (j < k && n == symbol_value[j]) {
usr.bin/yacc/reader.c
1709
while (++j < k && n == symbol_value[j])
usr.bin/yacc/reader.c
1733
k = v[i]->index;
usr.bin/yacc/reader.c
1734
symbol_name[k] = v[i]->name;
usr.bin/yacc/reader.c
1735
symbol_value[k] = v[i]->value;
usr.bin/yacc/reader.c
1736
symbol_prec[k] = v[i]->prec;
usr.bin/yacc/reader.c
1737
symbol_assoc[k] = v[i]->assoc;
usr.bin/yacc/reader.c
1808
int i, j, k;
usr.bin/yacc/reader.c
1815
k = 1;
usr.bin/yacc/reader.c
1830
while (ritem[k] >= 0) {
usr.bin/yacc/reader.c
1831
fprintf(f, " %s", symbol_name[ritem[k]]);
usr.bin/yacc/reader.c
1832
++k;
usr.bin/yacc/reader.c
1834
++k;
usr.bin/yacc/symtab.c
55
int c, k;
usr.bin/yacc/symtab.c
59
k = *s;
usr.bin/yacc/symtab.c
61
k = (31 * k + c) & (TABLE_SIZE - 1);
usr.bin/yacc/symtab.c
63
return (k);
usr.bin/yacc/verbose.c
186
int k;
usr.bin/yacc/verbose.c
193
k = statep->nitems;
usr.bin/yacc/verbose.c
195
for (i = 0; i < k; i++) {
usr.bin/yacc/verbose.c
221
int i, j, k, nnulls;
usr.bin/yacc/verbose.c
237
for (k = nnulls - 1; k > j; --k)
usr.bin/yacc/verbose.c
238
null_rules[k] = null_rules[k - 1];
usr.bin/yacc/verbose.c
303
int k, anyreds;
usr.bin/yacc/verbose.c
319
k = p->number - 2;
usr.bin/yacc/verbose.c
322
symbol_name[p->symbol], k);
usr.bin/yacc/verbose.c
335
int i, k;
usr.bin/yacc/verbose.c
344
k = tto_state[i];
usr.bin/yacc/verbose.c
345
as = accessing_symbol[k];
usr.bin/yacc/verbose.c
348
symbol_name[as], k);
usr.sbin/acme-client/parse.y
1044
struct keyfile *k;
usr.sbin/acme-client/parse.y
1046
LIST_FOREACH(k, &c->used_key_list, entry) {
usr.sbin/acme-client/parse.y
1047
if (strncmp(k->name, s, PATH_MAX) == 0) {
usr.sbin/acme-client/parse.y
1052
if ((k = calloc(1, sizeof(struct keyfile))) == NULL)
usr.sbin/acme-client/parse.y
1054
LIST_INSERT_HEAD(&c->used_key_list, k, entry);
usr.sbin/acme-client/parse.y
1056
k->name = s;
usr.sbin/acme-client/parse.y
1057
return k;
usr.sbin/acme-client/parse.y
499
kw_cmp(const void *k, const void *e)
usr.sbin/acme-client/parse.y
501
return strcmp(k, ((const struct keywords *)e)->k_name);
usr.sbin/acme-client/revokeproc.c
292
k = 0;
usr.sbin/acme-client/revokeproc.c
294
if (j == k)
usr.sbin/acme-client/revokeproc.c
296
k++;
usr.sbin/acme-client/revokeproc.c
91
int rc = 0, cc, sanidx, len, j, k;
usr.sbin/amd/amd/host_ops.c
219
int j, k;
usr.sbin/amd/amd/host_ops.c
324
for (j = k = 0; j < n_export; j++) {
usr.sbin/amd/amd/host_ops.c
326
if (j > k && ep[k] && strcmp(ep[j]->ex_dir, ep[k]->ex_dir) == 0) {
usr.sbin/amd/amd/host_ops.c
332
k = j;
usr.sbin/amd/amd/info_ndbm.c
53
datum k, v;
usr.sbin/amd/amd/info_ndbm.c
55
k.dptr = key;
usr.sbin/amd/amd/info_ndbm.c
56
k.dsize = strlen(key) + 1;
usr.sbin/amd/amd/info_ndbm.c
57
v = dbm_fetch(db, k);
usr.sbin/amd/amd/mapc.c
288
kv *k;
usr.sbin/amd/amd/mapc.c
293
k = m->kvhash[kvhash_of(key)];
usr.sbin/amd/amd/mapc.c
298
while (k && !FSTREQ(k->key, key))
usr.sbin/amd/amd/mapc.c
299
k = k->next;
usr.sbin/amd/amd/mapc.c
301
if (k) {
usr.sbin/amd/amd/mapc.c
302
free(k->val);
usr.sbin/amd/amd/mapc.c
303
k->val = val;
usr.sbin/amd/amd/mapc.c
460
kv *k = m->kvhash[i];
usr.sbin/amd/amd/mapc.c
461
while (k) {
usr.sbin/amd/amd/mapc.c
462
kv *n = k->next;
usr.sbin/amd/amd/mapc.c
463
free(k->key);
usr.sbin/amd/amd/mapc.c
464
free(k->val);
usr.sbin/amd/amd/mapc.c
465
free(k);
usr.sbin/amd/amd/mapc.c
466
k = n;
usr.sbin/amd/amd/mapc.c
535
kv *k = 0;
usr.sbin/amd/amd/mapc.c
562
k = m->kvhash[kvhash_of(key)];
usr.sbin/amd/amd/mapc.c
567
while (k && !FSTREQ(k->key, key)) k = k->next;
usr.sbin/amd/amd/mapc.c
580
k = m->kvhash[i];
usr.sbin/amd/amd/mapc.c
581
while (k) {
usr.sbin/amd/amd/mapc.c
582
if (regexec((regex_t *)k->key, key,
usr.sbin/amd/amd/mapc.c
585
k = k->next;
usr.sbin/amd/amd/mapc.c
587
if (k)
usr.sbin/amd/amd/mapc.c
595
if (k) {
usr.sbin/amd/amd/mapc.c
596
if (k->val)
usr.sbin/amd/amd/mapc.c
597
*pval = strdup(k->val);
usr.sbin/amd/amd/mapc.c
751
kv *k = m->kvhash[i];
usr.sbin/amd/amd/mapc.c
752
while (k) {
usr.sbin/amd/amd/mapc.c
753
(*fn)(k->key, arg);
usr.sbin/amd/amd/mapc.c
754
k = k->next;
usr.sbin/bgpd/kroute.c
2383
struct kroute *k;
usr.sbin/bgpd/kroute.c
2400
k = kn->kroute;
usr.sbin/bgpd/kroute.c
2401
k->flags &= ~F_NEXTHOP;
usr.sbin/bgpd/parse.y
3571
kw_cmp(const void *k, const void *e)
usr.sbin/bgpd/parse.y
3573
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/bgpd/parse.y
5593
kw_casecmp(const void *k, const void *e)
usr.sbin/bgpd/parse.y
5595
return (strcasecmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/bpflogd/bpflogd.c
334
insns[0].k = bd->bd_snaplen;
usr.sbin/dhcpd/conflex.c
349
kw_cmp(const void *k, const void *e)
usr.sbin/dhcpd/conflex.c
351
return (strcasecmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/dhcpd/inet.c
111
for (k = i - 1; k >= 0; k--)
usr.sbin/dhcpd/inet.c
112
if (habuf[k]) {
usr.sbin/dhcpd/inet.c
90
int i, j, k;
usr.sbin/dvmrpd/kroute.c
120
if (!strcmp(ifname, kif->k.ifname)) {
usr.sbin/dvmrpd/kroute.c
122
&kif->k, sizeof(kif->k));
usr.sbin/dvmrpd/kroute.c
131
return (b->k.ifindex - a->k.ifindex);
usr.sbin/dvmrpd/kroute.c
140
s.k.ifindex = ifindex;
usr.sbin/dvmrpd/kroute.c
151
if (!strcmp(ifname, kif->k.ifname))
usr.sbin/dvmrpd/kroute.c
152
return (&kif->k);
usr.sbin/dvmrpd/kroute.c
238
kif->k.flags = flags;
usr.sbin/dvmrpd/kroute.c
239
kif->k.link_state = ifd->ifi_link_state;
usr.sbin/dvmrpd/kroute.c
240
kif->k.if_type = ifd->ifi_type;
usr.sbin/dvmrpd/kroute.c
241
kif->k.baudrate = ifd->ifi_baudrate;
usr.sbin/dvmrpd/kroute.c
244
LINK_STATE_IS_UP(ifd->ifi_link_state)) == kif->k.nh_reachable)
usr.sbin/dvmrpd/kroute.c
247
kif->k.nh_reachable = reachable;
usr.sbin/dvmrpd/kroute.c
248
main_imsg_compose_dvmrpe(IMSG_IFINFO, 0, &kif->k, sizeof(kif->k));
usr.sbin/dvmrpd/kroute.c
266
kif->k.ifindex = ifan->ifan_index;
usr.sbin/dvmrpd/kroute.c
267
strlcpy(kif->k.ifname, ifan->ifan_name, sizeof(kif->k.ifname));
usr.sbin/dvmrpd/kroute.c
346
kif->k.ifindex = ifm.ifm_index;
usr.sbin/dvmrpd/kroute.c
347
kif->k.flags = ifm.ifm_flags;
usr.sbin/dvmrpd/kroute.c
348
kif->k.link_state = ifm.ifm_data.ifi_link_state;
usr.sbin/dvmrpd/kroute.c
349
kif->k.if_type = ifm.ifm_data.ifi_type;
usr.sbin/dvmrpd/kroute.c
350
kif->k.baudrate = ifm.ifm_data.ifi_baudrate;
usr.sbin/dvmrpd/kroute.c
351
kif->k.mtu = ifm.ifm_data.ifi_mtu;
usr.sbin/dvmrpd/kroute.c
352
kif->k.nh_reachable = (kif->k.flags & IFF_UP) &&
usr.sbin/dvmrpd/kroute.c
357
if (sdl->sdl_nlen >= sizeof(kif->k.ifname))
usr.sbin/dvmrpd/kroute.c
358
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/dvmrpd/kroute.c
359
sizeof(kif->k.ifname) - 1);
usr.sbin/dvmrpd/kroute.c
361
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/dvmrpd/kroute.c
50
struct kif k;
usr.sbin/dvmrpd/parse.y
387
kw_cmp(const void *k, const void *e)
usr.sbin/dvmrpd/parse.y
389
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/eigrpctl/eigrpctl.c
670
struct kroute *k;
usr.sbin/eigrpctl/eigrpctl.c
677
k = imsg->data;
usr.sbin/eigrpctl/eigrpctl.c
679
if (res->family != AF_UNSPEC && res->family != k->af)
usr.sbin/eigrpctl/eigrpctl.c
682
if (k->flags & F_DOWN)
usr.sbin/eigrpctl/eigrpctl.c
687
if (!(k->flags & F_KERNEL))
usr.sbin/eigrpctl/eigrpctl.c
689
else if (k->flags & F_CONNECTED)
usr.sbin/eigrpctl/eigrpctl.c
691
else if (k->flags & F_STATIC)
usr.sbin/eigrpctl/eigrpctl.c
696
printf("%-5s", (k->flags & F_CTL_EXTERNAL) ? " EX" : "");
usr.sbin/eigrpctl/eigrpctl.c
697
printf("%4d ", k->priority);
usr.sbin/eigrpctl/eigrpctl.c
698
if (asprintf(&p, "%s/%u", log_addr(k->af, &k->prefix),
usr.sbin/eigrpctl/eigrpctl.c
699
k->prefixlen) == -1)
usr.sbin/eigrpctl/eigrpctl.c
706
if (eigrp_addrisset(k->af, &k->nexthop)) {
usr.sbin/eigrpctl/eigrpctl.c
707
switch (k->af) {
usr.sbin/eigrpctl/eigrpctl.c
709
printf("%s", log_addr(k->af, &k->nexthop));
usr.sbin/eigrpctl/eigrpctl.c
712
printf("%s", log_in6addr_scope(&k->nexthop.v6,
usr.sbin/eigrpctl/eigrpctl.c
713
k->ifindex));
usr.sbin/eigrpctl/eigrpctl.c
719
} else if (k->flags & F_CONNECTED)
usr.sbin/eigrpctl/eigrpctl.c
720
printf("link#%u", k->ifindex);
usr.sbin/eigrpctl/eigrpctl.c
788
struct kif *k;
usr.sbin/eigrpctl/eigrpctl.c
795
k = imsg->data;
usr.sbin/eigrpctl/eigrpctl.c
796
printf("%-15s", k->ifname);
usr.sbin/eigrpctl/eigrpctl.c
797
printf("%-15s", k->flags & IFF_UP ? "UP" : "");
usr.sbin/eigrpctl/eigrpctl.c
798
ifms_type = get_ifms_type(k->if_type);
usr.sbin/eigrpctl/eigrpctl.c
802
printf("%s", get_linkstate(k->if_type, k->link_state));
usr.sbin/eigrpctl/eigrpctl.c
804
if (k->link_state != LINK_STATE_DOWN && k->baudrate > 0) {
usr.sbin/eigrpctl/eigrpctl.c
806
print_baudrate(k->baudrate);
usr.sbin/eigrpd/kroute.c
1000
eigrp_addrcmp(ka->a.af, &ka->a.addr, &k.addr) ||
usr.sbin/eigrpd/kroute.c
1001
eigrp_addrcmp(ka->a.af, &ka->a.dstbrd, &k.dstbrd))
usr.sbin/eigrpd/kroute.c
1025
strlcpy(kif->k.ifname, ifan->ifan_name,
usr.sbin/eigrpd/kroute.c
1026
sizeof(kif->k.ifname));
usr.sbin/eigrpd/kroute.c
195
main_imsg_compose_eigrpe(IMSG_IFINFO, 0, &kif->k,
usr.sbin/eigrpd/kroute.c
365
if (ifname == NULL || !strcmp(ifname, kif->k.ifname)) {
usr.sbin/eigrpd/kroute.c
367
pid, &kif->k, sizeof(kif->k));
usr.sbin/eigrpd/kroute.c
650
return (b->k.ifindex - a->k.ifindex);
usr.sbin/eigrpd/kroute.c
660
s.k.ifindex = ifindex;
usr.sbin/eigrpd/kroute.c
671
if (!strcmp(ifname, kif->k.ifname))
usr.sbin/eigrpd/kroute.c
672
return (&kif->k);
usr.sbin/eigrpd/kroute.c
685
kif->k.ifindex = ifindex;
usr.sbin/eigrpd/kroute.c
700
log_warnx("%s failed for interface %s", __func__, kif->k.ifname);
usr.sbin/eigrpd/kroute.c
730
kif->k.nh_reachable = (flags & IFF_UP) &&
usr.sbin/eigrpd/kroute.c
734
kif->k.flags = flags;
usr.sbin/eigrpd/kroute.c
735
kif->k.link_state = ifd->ifi_link_state;
usr.sbin/eigrpd/kroute.c
736
kif->k.if_type = ifd->ifi_type;
usr.sbin/eigrpd/kroute.c
737
kif->k.baudrate = ifd->ifi_baudrate;
usr.sbin/eigrpd/kroute.c
738
kif->k.mtu = ifd->ifi_mtu;
usr.sbin/eigrpd/kroute.c
739
kif->k.rdomain = ifd->ifi_rdomain;
usr.sbin/eigrpd/kroute.c
742
if (sdl->sdl_nlen >= sizeof(kif->k.ifname))
usr.sbin/eigrpd/kroute.c
743
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/eigrpd/kroute.c
744
sizeof(kif->k.ifname) - 1);
usr.sbin/eigrpd/kroute.c
746
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/eigrpd/kroute.c
751
return (&kif->k);
usr.sbin/eigrpd/kroute.c
762
return (kif->k.nh_reachable);
usr.sbin/eigrpd/kroute.c
78
struct kif k;
usr.sbin/eigrpd/kroute.c
945
struct kaddr k;
usr.sbin/eigrpd/kroute.c
956
memset(&k, 0, sizeof(k));
usr.sbin/eigrpd/kroute.c
957
k.af = ifa->sa_family;
usr.sbin/eigrpd/kroute.c
968
k.addr.v4 = ifa4->sin_addr;
usr.sbin/eigrpd/kroute.c
970
k.prefixlen = mask2prefixlen(mask4->sin_addr.s_addr);
usr.sbin/eigrpd/kroute.c
972
k.dstbrd.v4 = brd4->sin_addr;
usr.sbin/eigrpd/kroute.c
985
k.addr.v6 = ifa6->sin6_addr;
usr.sbin/eigrpd/kroute.c
987
k.prefixlen = mask2prefixlen6(mask6);
usr.sbin/eigrpd/kroute.c
989
k.dstbrd.v6 = brd6->sin6_addr;
usr.sbin/eigrpd/kroute.c
998
if (ka->a.af != k.af ||
usr.sbin/eigrpd/kroute.c
999
ka->a.prefixlen != k.prefixlen ||
usr.sbin/eigrpd/parse.y
604
kw_cmp(const void *k, const void *e)
usr.sbin/eigrpd/parse.y
606
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/httpd/parse.y
1590
kw_cmp(const void *k, const void *e)
usr.sbin/httpd/parse.y
1592
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ifstated/parse.y
381
kw_cmp(const void *k, const void *e)
usr.sbin/ifstated/parse.y
383
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/iscsictl/parse.y
363
kw_cmp(const void *k, const void *e)
usr.sbin/iscsictl/parse.y
365
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/iscsid/connection.c
301
struct kvp *k;
usr.sbin/iscsid/connection.c
307
for (k = kvp; k->key; k++) {
usr.sbin/iscsid/connection.c
308
log_debug("conn_parse_kvp: %s = %s", k->key, k->value);
usr.sbin/iscsid/connection.c
310
SET_NUM(k, s, MaxBurstLength, 512, 16777215);
usr.sbin/iscsid/connection.c
311
SET_NUM(k, s, FirstBurstLength, 512, 16777215);
usr.sbin/iscsid/connection.c
312
SET_NUM(k, s, DefaultTime2Wait, 0, 3600);
usr.sbin/iscsid/connection.c
313
SET_NUM(k, s, DefaultTime2Retain, 0, 3600);
usr.sbin/iscsid/connection.c
314
SET_NUM(k, s, MaxOutstandingR2T, 1, 65535);
usr.sbin/iscsid/connection.c
315
SET_NUM(k, s, TargetPortalGroupTag, 0, 65535);
usr.sbin/iscsid/connection.c
316
SET_NUM(k, s, MaxConnections, 1, 65535);
usr.sbin/iscsid/connection.c
317
SET_BOOL(k, s, InitialR2T);
usr.sbin/iscsid/connection.c
318
SET_BOOL(k, s, ImmediateData);
usr.sbin/iscsid/connection.c
319
SET_BOOL(k, s, DataPDUInOrder);
usr.sbin/iscsid/connection.c
320
SET_BOOL(k, s, DataSequenceInOrder);
usr.sbin/iscsid/connection.c
321
SET_NUM(k, s, ErrorRecoveryLevel, 0, 2);
usr.sbin/iscsid/connection.c
322
SET_NUM(k, c, MaxRecvDataSegmentLength, 512, 16777215);
usr.sbin/iscsid/connection.c
323
SET_DIGEST(k, c, HeaderDigest);
usr.sbin/iscsid/connection.c
324
SET_DIGEST(k, c, DataDigest);
usr.sbin/iscsid/connection.c
338
#define GET_BOOL_P(dst, req, k, src, f) \
usr.sbin/iscsid/connection.c
340
if (f == 0 && !strcmp(req, #k)) { \
usr.sbin/iscsid/connection.c
341
(dst)->key = #k; \
usr.sbin/iscsid/connection.c
342
(dst)->value = ((src)->mine.k) ? "Yes" : "No"; \
usr.sbin/iscsid/connection.c
347
#define GET_DIGEST_P(dst, req, k, src, f) \
usr.sbin/iscsid/connection.c
349
if (f == 0 && !strcmp(req, #k)) { \
usr.sbin/iscsid/connection.c
350
(dst)->key = #k; \
usr.sbin/iscsid/connection.c
352
((src)->mine.k == DIGEST_NONE) ? "None" : "CRC32C,None";\
usr.sbin/iscsid/connection.c
357
#define GET_NUM_P(dst, req, k, src, f, e) \
usr.sbin/iscsid/connection.c
359
if (f == 0 && !strcmp(req, #k)) { \
usr.sbin/iscsid/connection.c
360
(dst)->key = #k; \
usr.sbin/iscsid/connection.c
361
if (asprintf(&((dst)->value), "%u", (src)->mine.k) == -1)\
usr.sbin/iscsid/connection.c
369
#define GET_STR_C(dst, req, k, src, f) \
usr.sbin/iscsid/connection.c
371
if (f == 0 && !strcmp(req, #k)) { \
usr.sbin/iscsid/connection.c
372
(dst)->key = #k; \
usr.sbin/iscsid/connection.c
373
(dst)->value = (src)->config.k; \
usr.sbin/iscsid/connection.c
378
#define GET_STYPE_C(dst, req, k, src, f) \
usr.sbin/iscsid/connection.c
380
if (f == 0 && !strcmp(req, #k)) { \
usr.sbin/iscsid/connection.c
381
(dst)->key = #k; \
usr.sbin/iscsid/connection.c
382
(dst)->value = ((src)->config.k == SESSION_TYPE_DISCOVERY)\
usr.sbin/iscsid/initiator.c
318
#define MINE_NOT_DEFAULT(c, k) ((c)->mine.k != iscsi_conn_defaults.k)
usr.sbin/iscsid/initiator.c
548
struct kvp *kvp, *k;
usr.sbin/iscsid/initiator.c
568
for (k = kvp; k->key; k++) {
usr.sbin/iscsid/initiator.c
569
log_debug("%s\t=>\t%s", k->key, k->value);
usr.sbin/iscsid/pdu.c
111
if (!(k = calloc(nkvp + 1, sizeof(*k))))
usr.sbin/iscsid/pdu.c
118
free(k);
usr.sbin/iscsid/pdu.c
122
k[i].key = buf;
usr.sbin/iscsid/pdu.c
123
k[i].value = eq;
usr.sbin/iscsid/pdu.c
126
return k;
usr.sbin/iscsid/pdu.c
56
text_to_pdu(struct kvp *k, struct pdu *p)
usr.sbin/iscsid/pdu.c
62
if (k == NULL)
usr.sbin/iscsid/pdu.c
66
while(k[nk].key) {
usr.sbin/iscsid/pdu.c
67
len += 2 + strlen(k[nk].key) + strlen(k[nk].value);
usr.sbin/iscsid/pdu.c
76
while(k[nk].key) {
usr.sbin/iscsid/pdu.c
77
n = snprintf(s, rem, "%s=%s", k[nk].key, k[nk].value);
usr.sbin/iscsid/pdu.c
93
struct kvp *k;
usr.sbin/iscsid/util.c
196
struct kvp *k;
usr.sbin/iscsid/util.c
200
for (k = kvp; k->key; k++) {
usr.sbin/iscsid/util.c
201
if (k->flags & KVP_KEY_ALLOCED)
usr.sbin/iscsid/util.c
202
free(k->key);
usr.sbin/iscsid/util.c
203
if (k->flags & KVP_VALUE_ALLOCED)
usr.sbin/iscsid/util.c
204
free(k->value);
usr.sbin/ldapd/btree.c
219
#define INDXSIZE(k) (NODESIZE + ((k) == NULL ? 0 : (k)->size))
usr.sbin/ldapd/btree.c
220
#define LEAFSIZE(k, d) (NODESIZE + (k)->size + (d)->size)
usr.sbin/ldapd/parse.y
431
kw_cmp(const void *k, const void *e)
usr.sbin/ldapd/parse.y
433
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ldapd/syntax.c
97
syntax_cmp(const void *k, const void *e)
usr.sbin/ldapd/syntax.c
99
return (strcmp(k, ((const struct syntax *)e)->oid));
usr.sbin/ldomctl/parse.y
382
kw_cmp(const void *k, const void *e)
usr.sbin/ldomctl/parse.y
384
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ldpctl/ldpctl.c
479
struct kroute *k;
usr.sbin/ldpctl/ldpctl.c
487
k = imsg->data;
usr.sbin/ldpctl/ldpctl.c
489
if (res->family != AF_UNSPEC && res->family != k->af)
usr.sbin/ldpctl/ldpctl.c
492
if (k->flags & F_CONNECTED)
usr.sbin/ldpctl/ldpctl.c
494
else if (k->flags & F_STATIC)
usr.sbin/ldpctl/ldpctl.c
499
printf(" %3d ", k->priority);
usr.sbin/ldpctl/ldpctl.c
500
if (asprintf(&p, "%s/%u", log_addr(k->af, &k->prefix),
usr.sbin/ldpctl/ldpctl.c
501
k->prefixlen) == -1)
usr.sbin/ldpctl/ldpctl.c
508
if (ldp_addrisset(k->af, &k->nexthop)) {
usr.sbin/ldpctl/ldpctl.c
509
switch (k->af) {
usr.sbin/ldpctl/ldpctl.c
511
printf("%-18s", inet_ntoa(k->nexthop.v4));
usr.sbin/ldpctl/ldpctl.c
514
nexthop = log_in6addr_scope(&k->nexthop.v6,
usr.sbin/ldpctl/ldpctl.c
515
k->ifindex);
usr.sbin/ldpctl/ldpctl.c
524
} else if (k->flags & F_CONNECTED)
usr.sbin/ldpctl/ldpctl.c
525
printf("link#%-13u", k->ifindex);
usr.sbin/ldpctl/ldpctl.c
527
printf("%-18s", log_label(k->local_label));
usr.sbin/ldpctl/ldpctl.c
528
printf("%s", log_label(k->remote_label));
usr.sbin/ldpctl/ldpctl.c
551
struct kif *k;
usr.sbin/ldpctl/ldpctl.c
556
k = imsg->data;
usr.sbin/ldpctl/ldpctl.c
557
printf("%-15s", k->ifname);
usr.sbin/ldpctl/ldpctl.c
558
printf("%-15s", k->flags & IFF_UP ? "UP" : "");
usr.sbin/ldpctl/ldpctl.c
559
ifms_type = get_ifms_type(k->if_type);
usr.sbin/ldpctl/ldpctl.c
563
printf("%s", get_linkstate(k->if_type, k->link_state));
usr.sbin/ldpctl/ldpctl.c
565
if (k->link_state != LINK_STATE_DOWN && k->baudrate > 0) {
usr.sbin/ldpctl/ldpctl.c
567
print_baudrate(k->baudrate);
usr.sbin/ldpd/kroute.c
1072
struct kaddr k;
usr.sbin/ldpd/kroute.c
1083
memset(&k, 0, sizeof(k));
usr.sbin/ldpd/kroute.c
1084
k.af = ifa->sa_family;
usr.sbin/ldpd/kroute.c
1095
k.addr.v4 = ifa4->sin_addr;
usr.sbin/ldpd/kroute.c
1097
k.prefixlen = mask2prefixlen(mask4->sin_addr.s_addr);
usr.sbin/ldpd/kroute.c
1099
k.dstbrd.v4 = brd4->sin_addr;
usr.sbin/ldpd/kroute.c
1112
k.addr.v6 = ifa6->sin6_addr;
usr.sbin/ldpd/kroute.c
1114
k.prefixlen = mask2prefixlen6(mask6);
usr.sbin/ldpd/kroute.c
1116
k.dstbrd.v6 = brd6->sin6_addr;
usr.sbin/ldpd/kroute.c
1125
if (ka->a.af != k.af ||
usr.sbin/ldpd/kroute.c
1126
ka->a.prefixlen != k.prefixlen ||
usr.sbin/ldpd/kroute.c
1127
ldp_addrcmp(ka->a.af, &ka->a.addr, &k.addr))
usr.sbin/ldpd/kroute.c
1150
strlcpy(kif->k.ifname, ifan->ifan_name,
usr.sbin/ldpd/kroute.c
1151
sizeof(kif->k.ifname));
usr.sbin/ldpd/kroute.c
1781
return (kmpw_install(kif->k.ifname, kpw));
usr.sbin/ldpd/kroute.c
1797
log_warnx("%s: %s is not set", __func__, kif->k.ifname);
usr.sbin/ldpd/kroute.c
1803
return (kmpw_uninstall(kif->k.ifname));
usr.sbin/ldpd/kroute.c
217
if (kif->k.rdomain != kr_state.rdomain)
usr.sbin/ldpd/kroute.c
220
if (ifname && strcmp(kif->k.ifname, ifname) != 0)
usr.sbin/ldpd/kroute.c
356
kmpw_install(kif->k.ifname, kif->kpw);
usr.sbin/ldpd/kroute.c
398
kmpw_uninstall(kif->k.ifname);
usr.sbin/ldpd/kroute.c
503
if (ifname == NULL || !strcmp(ifname, kif->k.ifname)) {
usr.sbin/ldpd/kroute.c
505
pid, &kif->k, sizeof(kif->k));
usr.sbin/ldpd/kroute.c
787
return (b->k.ifindex - a->k.ifindex);
usr.sbin/ldpd/kroute.c
797
s.k.ifindex = ifindex;
usr.sbin/ldpd/kroute.c
808
if (!strcmp(ifname, kif->k.ifname))
usr.sbin/ldpd/kroute.c
809
return (&kif->k);
usr.sbin/ldpd/kroute.c
81
struct kif k;
usr.sbin/ldpd/kroute.c
822
kif->k.ifindex = ifindex;
usr.sbin/ldpd/kroute.c
871
*link_old = (kif->k.flags & IFF_UP) &&
usr.sbin/ldpd/kroute.c
872
LINK_STATE_IS_UP(kif->k.link_state);
usr.sbin/ldpd/kroute.c
874
kif->k.flags = flags;
usr.sbin/ldpd/kroute.c
875
kif->k.link_state = ifd->ifi_link_state;
usr.sbin/ldpd/kroute.c
877
memcpy(kif->k.mac, LLADDR(sdl), sizeof(kif->k.mac));
usr.sbin/ldpd/kroute.c
878
kif->k.if_type = ifd->ifi_type;
usr.sbin/ldpd/kroute.c
879
kif->k.baudrate = ifd->ifi_baudrate;
usr.sbin/ldpd/kroute.c
880
kif->k.mtu = ifd->ifi_mtu;
usr.sbin/ldpd/kroute.c
881
kif->k.rdomain = ifd->ifi_rdomain;
usr.sbin/ldpd/kroute.c
884
if (sdl->sdl_nlen >= sizeof(kif->k.ifname))
usr.sbin/ldpd/kroute.c
885
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ldpd/kroute.c
886
sizeof(kif->k.ifname) - 1);
usr.sbin/ldpd/kroute.c
888
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ldpd/kroute.c
980
link_new = (kif->k.flags & IFF_UP) &&
usr.sbin/ldpd/kroute.c
981
LINK_STATE_IS_UP(kif->k.link_state);
usr.sbin/ldpd/kroute.c
986
main_imsg_compose_ldpe(IMSG_IFSTATUS, 0, &kif->k, sizeof(struct kif));
usr.sbin/ldpd/parse.y
903
kw_cmp(const void *k, const void *e)
usr.sbin/ldpd/parse.y
905
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/lpd/parse.y
249
kw_cmp(const void *k, const void *e)
usr.sbin/lpd/parse.y
251
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/memconfig/memconfig.c
156
int nd, i, j, k, ch, showall = 0;
usr.sbin/memconfig/memconfig.c
186
for (k = 0; attrnames[k].name != NULL; k++)
usr.sbin/memconfig/memconfig.c
187
if (((1<<j) & mrd[i].mr_flags) & attrnames[k].val) {
usr.sbin/memconfig/memconfig.c
188
printf("%s ", attrnames[k].name);
usr.sbin/memconfig/memconfig.c
191
if (attrnames[k].name == NULL)
usr.sbin/mopd/common/pf.c
132
insns[1].k = protocol;
usr.sbin/mopd/common/pf.c
133
insns[3].k = protocol;
usr.sbin/mtree/misc.c
78
KEY *k, tmp;
usr.sbin/mtree/misc.c
82
k = (KEY *)bsearch(&tmp, keylist, sizeof(keylist) / sizeof(KEY),
usr.sbin/mtree/misc.c
84
if (k == NULL)
usr.sbin/mtree/misc.c
88
*needvaluep = k->flags & NEEDVALUE ? 1 : 0;
usr.sbin/mtree/misc.c
89
return (k->val);
usr.sbin/netgroup_mkdb/netgroup_mkdb.c
591
ng_write(DB *odb, DB *idb, int k)
usr.sbin/netgroup_mkdb/netgroup_mkdb.c
606
str_prepend(&skey, e->n_name, k);
usr.sbin/netgroup_mkdb/netgroup_mkdb.c
645
ng_rwrite(DB *odb, DB *idb, int k)
usr.sbin/netgroup_mkdb/netgroup_mkdb.c
659
str_prepend(&skey, (char *) key.data, k);
usr.sbin/npppd/common/hash.c
104
hash_lookup(hash_table *htbl, const void *k)
usr.sbin/npppd/common/hash.c
109
if (htbl == NULL || k == NULL)
usr.sbin/npppd/common/hash.c
111
c = (htbl->hash) (k, (int)htbl->size);
usr.sbin/npppd/common/hash.c
113
if (htbl->cmp(w->key, k) == 0)
usr.sbin/npppd/common/hash.c
122
hash_insert(hash_table *htbl, const void *k, void *i)
usr.sbin/npppd/common/hash.c
127
if (htbl == NULL || k == NULL)
usr.sbin/npppd/common/hash.c
134
c = (htbl->hash) (k, (int)htbl->size);
usr.sbin/npppd/common/hash.c
137
n->key = k;
usr.sbin/npppd/common/hash.c
149
hash_delete(hash_table *htbl, const void *k, int memfree)
usr.sbin/npppd/common/hash.c
154
if (htbl == NULL || k == NULL)
usr.sbin/npppd/common/hash.c
157
i = (htbl->hash) (k, (int)htbl->size);
usr.sbin/npppd/common/hash.c
160
if (htbl->cmp(w->key, k) == 0) {
usr.sbin/npppd/npppd/parse.y
1064
kw_cmp(const void *k, const void *e)
usr.sbin/npppd/npppd/parse.y
1066
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/npppd/pppoe/pppoed.c
306
insns[10].k = ETHER_FIRST_INT(_this->ether_addr);
usr.sbin/npppd/pppoe/pppoed.c
307
insns[12].k = ETHER_LAST_SHORT(_this->ether_addr);
usr.sbin/nsd/edns.c
205
const uint8_t *k, uint8_t *out, const size_t outlen);
usr.sbin/nsd/lookup3.c
109
#define rot(x,k) (((x)<<(k)) | ((x)>>(32-(k))))
usr.sbin/nsd/lookup3.c
215
const uint32_t *k, /* the key, an array of uint32_t values */
usr.sbin/nsd/lookup3.c
227
a += k[0];
usr.sbin/nsd/lookup3.c
228
b += k[1];
usr.sbin/nsd/lookup3.c
229
c += k[2];
usr.sbin/nsd/lookup3.c
232
k += 3;
usr.sbin/nsd/lookup3.c
238
case 3 : c+=k[2];
usr.sbin/nsd/lookup3.c
240
case 2 : b+=k[1];
usr.sbin/nsd/lookup3.c
242
case 1 : a+=k[0];
usr.sbin/nsd/lookup3.c
263
const uint32_t *k, /* the key, an array of uint32_t values */
usr.sbin/nsd/lookup3.c
277
a += k[0];
usr.sbin/nsd/lookup3.c
278
b += k[1];
usr.sbin/nsd/lookup3.c
279
c += k[2];
usr.sbin/nsd/lookup3.c
282
k += 3;
usr.sbin/nsd/lookup3.c
288
case 3 : c+=k[2];
usr.sbin/nsd/lookup3.c
289
case 2 : b+=k[1];
usr.sbin/nsd/lookup3.c
290
case 1 : a+=k[0];
usr.sbin/nsd/lookup3.c
338
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/nsd/lookup3.c
346
a += k[0];
usr.sbin/nsd/lookup3.c
347
b += k[1];
usr.sbin/nsd/lookup3.c
348
c += k[2];
usr.sbin/nsd/lookup3.c
351
k += 3;
usr.sbin/nsd/lookup3.c
368
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
369
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
370
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
371
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
372
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
373
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
374
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
375
case 5 : b+=k[1]&0xff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
376
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
377
case 3 : a+=k[0]&0xffffff; break;
usr.sbin/nsd/lookup3.c
378
case 2 : a+=k[0]&0xffff; break;
usr.sbin/nsd/lookup3.c
379
case 1 : a+=k[0]&0xff; break;
usr.sbin/nsd/lookup3.c
385
k8 = (const uint8_t *)k;
usr.sbin/nsd/lookup3.c
388
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
392
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
396
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
406
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
usr.sbin/nsd/lookup3.c
412
a += k[0] + (((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
413
b += k[2] + (((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
414
c += k[4] + (((uint32_t)k[5])<<16);
usr.sbin/nsd/lookup3.c
417
k += 6;
usr.sbin/nsd/lookup3.c
421
k8 = (const uint8_t *)k;
usr.sbin/nsd/lookup3.c
424
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
usr.sbin/nsd/lookup3.c
425
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
426
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
429
case 10: c+=k[4];
usr.sbin/nsd/lookup3.c
430
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
431
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
434
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
435
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
438
case 6 : b+=k[2];
usr.sbin/nsd/lookup3.c
439
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
442
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
445
case 2 : a+=k[0];
usr.sbin/nsd/lookup3.c
453
const uint8_t *k = (const uint8_t *)key;
usr.sbin/nsd/lookup3.c
458
a += k[0];
usr.sbin/nsd/lookup3.c
459
a += ((uint32_t)k[1])<<8;
usr.sbin/nsd/lookup3.c
460
a += ((uint32_t)k[2])<<16;
usr.sbin/nsd/lookup3.c
461
a += ((uint32_t)k[3])<<24;
usr.sbin/nsd/lookup3.c
462
b += k[4];
usr.sbin/nsd/lookup3.c
463
b += ((uint32_t)k[5])<<8;
usr.sbin/nsd/lookup3.c
464
b += ((uint32_t)k[6])<<16;
usr.sbin/nsd/lookup3.c
465
b += ((uint32_t)k[7])<<24;
usr.sbin/nsd/lookup3.c
466
c += k[8];
usr.sbin/nsd/lookup3.c
467
c += ((uint32_t)k[9])<<8;
usr.sbin/nsd/lookup3.c
468
c += ((uint32_t)k[10])<<16;
usr.sbin/nsd/lookup3.c
469
c += ((uint32_t)k[11])<<24;
usr.sbin/nsd/lookup3.c
472
k += 12;
usr.sbin/nsd/lookup3.c
478
case 12: c+=((uint32_t)k[11])<<24;
usr.sbin/nsd/lookup3.c
480
case 11: c+=((uint32_t)k[10])<<16;
usr.sbin/nsd/lookup3.c
482
case 10: c+=((uint32_t)k[9])<<8;
usr.sbin/nsd/lookup3.c
484
case 9 : c+=k[8];
usr.sbin/nsd/lookup3.c
486
case 8 : b+=((uint32_t)k[7])<<24;
usr.sbin/nsd/lookup3.c
488
case 7 : b+=((uint32_t)k[6])<<16;
usr.sbin/nsd/lookup3.c
490
case 6 : b+=((uint32_t)k[5])<<8;
usr.sbin/nsd/lookup3.c
492
case 5 : b+=k[4];
usr.sbin/nsd/lookup3.c
494
case 4 : a+=((uint32_t)k[3])<<24;
usr.sbin/nsd/lookup3.c
496
case 3 : a+=((uint32_t)k[2])<<16;
usr.sbin/nsd/lookup3.c
498
case 2 : a+=((uint32_t)k[1])<<8;
usr.sbin/nsd/lookup3.c
500
case 1 : a+=k[0];
usr.sbin/nsd/lookup3.c
537
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/nsd/lookup3.c
545
a += k[0];
usr.sbin/nsd/lookup3.c
546
b += k[1];
usr.sbin/nsd/lookup3.c
547
c += k[2];
usr.sbin/nsd/lookup3.c
550
k += 3;
usr.sbin/nsd/lookup3.c
567
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
568
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
569
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
570
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
571
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
572
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
573
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
574
case 5 : b+=k[1]&0xff; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
575
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
576
case 3 : a+=k[0]&0xffffff; break;
usr.sbin/nsd/lookup3.c
577
case 2 : a+=k[0]&0xffff; break;
usr.sbin/nsd/lookup3.c
578
case 1 : a+=k[0]&0xff; break;
usr.sbin/nsd/lookup3.c
584
k8 = (const uint8_t *)k;
usr.sbin/nsd/lookup3.c
587
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
591
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
595
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
605
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
usr.sbin/nsd/lookup3.c
611
a += k[0] + (((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
612
b += k[2] + (((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
613
c += k[4] + (((uint32_t)k[5])<<16);
usr.sbin/nsd/lookup3.c
616
k += 6;
usr.sbin/nsd/lookup3.c
620
k8 = (const uint8_t *)k;
usr.sbin/nsd/lookup3.c
623
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
usr.sbin/nsd/lookup3.c
624
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
625
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
628
case 10: c+=k[4];
usr.sbin/nsd/lookup3.c
629
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
630
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
633
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/nsd/lookup3.c
634
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
637
case 6 : b+=k[2];
usr.sbin/nsd/lookup3.c
638
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
641
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/nsd/lookup3.c
644
case 2 : a+=k[0];
usr.sbin/nsd/lookup3.c
652
const uint8_t *k = (const uint8_t *)key;
usr.sbin/nsd/lookup3.c
657
a += k[0];
usr.sbin/nsd/lookup3.c
658
a += ((uint32_t)k[1])<<8;
usr.sbin/nsd/lookup3.c
659
a += ((uint32_t)k[2])<<16;
usr.sbin/nsd/lookup3.c
660
a += ((uint32_t)k[3])<<24;
usr.sbin/nsd/lookup3.c
661
b += k[4];
usr.sbin/nsd/lookup3.c
662
b += ((uint32_t)k[5])<<8;
usr.sbin/nsd/lookup3.c
663
b += ((uint32_t)k[6])<<16;
usr.sbin/nsd/lookup3.c
664
b += ((uint32_t)k[7])<<24;
usr.sbin/nsd/lookup3.c
665
c += k[8];
usr.sbin/nsd/lookup3.c
666
c += ((uint32_t)k[9])<<8;
usr.sbin/nsd/lookup3.c
667
c += ((uint32_t)k[10])<<16;
usr.sbin/nsd/lookup3.c
668
c += ((uint32_t)k[11])<<24;
usr.sbin/nsd/lookup3.c
671
k += 12;
usr.sbin/nsd/lookup3.c
677
case 12: c+=((uint32_t)k[11])<<24;
usr.sbin/nsd/lookup3.c
678
case 11: c+=((uint32_t)k[10])<<16;
usr.sbin/nsd/lookup3.c
679
case 10: c+=((uint32_t)k[9])<<8;
usr.sbin/nsd/lookup3.c
680
case 9 : c+=k[8];
usr.sbin/nsd/lookup3.c
681
case 8 : b+=((uint32_t)k[7])<<24;
usr.sbin/nsd/lookup3.c
682
case 7 : b+=((uint32_t)k[6])<<16;
usr.sbin/nsd/lookup3.c
683
case 6 : b+=((uint32_t)k[5])<<8;
usr.sbin/nsd/lookup3.c
684
case 5 : b+=k[4];
usr.sbin/nsd/lookup3.c
685
case 4 : a+=((uint32_t)k[3])<<24;
usr.sbin/nsd/lookup3.c
686
case 3 : a+=((uint32_t)k[2])<<16;
usr.sbin/nsd/lookup3.c
687
case 2 : a+=((uint32_t)k[1])<<8;
usr.sbin/nsd/lookup3.c
688
case 1 : a+=k[0];
usr.sbin/nsd/lookup3.c
718
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/nsd/lookup3.c
726
a += k[0];
usr.sbin/nsd/lookup3.c
727
b += k[1];
usr.sbin/nsd/lookup3.c
728
c += k[2];
usr.sbin/nsd/lookup3.c
731
k += 3;
usr.sbin/nsd/lookup3.c
748
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
749
case 11: c+=k[2]&0xffffff00; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
750
case 10: c+=k[2]&0xffff0000; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
751
case 9 : c+=k[2]&0xff000000; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
752
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
753
case 7 : b+=k[1]&0xffffff00; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
754
case 6 : b+=k[1]&0xffff0000; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
755
case 5 : b+=k[1]&0xff000000; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
756
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
757
case 3 : a+=k[0]&0xffffff00; break;
usr.sbin/nsd/lookup3.c
758
case 2 : a+=k[0]&0xffff0000; break;
usr.sbin/nsd/lookup3.c
759
case 1 : a+=k[0]&0xff000000; break;
usr.sbin/nsd/lookup3.c
765
k8 = (const uint8_t *)k;
usr.sbin/nsd/lookup3.c
768
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
772
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/nsd/lookup3.c
776
case 4 : a+=k[0]; break;
usr.sbin/nsd/lookup3.c
786
const uint8_t *k = (const uint8_t *)key;
usr.sbin/nsd/lookup3.c
791
a += ((uint32_t)k[0])<<24;
usr.sbin/nsd/lookup3.c
792
a += ((uint32_t)k[1])<<16;
usr.sbin/nsd/lookup3.c
793
a += ((uint32_t)k[2])<<8;
usr.sbin/nsd/lookup3.c
794
a += ((uint32_t)k[3]);
usr.sbin/nsd/lookup3.c
795
b += ((uint32_t)k[4])<<24;
usr.sbin/nsd/lookup3.c
796
b += ((uint32_t)k[5])<<16;
usr.sbin/nsd/lookup3.c
797
b += ((uint32_t)k[6])<<8;
usr.sbin/nsd/lookup3.c
798
b += ((uint32_t)k[7]);
usr.sbin/nsd/lookup3.c
799
c += ((uint32_t)k[8])<<24;
usr.sbin/nsd/lookup3.c
800
c += ((uint32_t)k[9])<<16;
usr.sbin/nsd/lookup3.c
801
c += ((uint32_t)k[10])<<8;
usr.sbin/nsd/lookup3.c
802
c += ((uint32_t)k[11]);
usr.sbin/nsd/lookup3.c
805
k += 12;
usr.sbin/nsd/lookup3.c
811
case 12: c+=k[11];
usr.sbin/nsd/lookup3.c
812
case 11: c+=((uint32_t)k[10])<<8;
usr.sbin/nsd/lookup3.c
813
case 10: c+=((uint32_t)k[9])<<16;
usr.sbin/nsd/lookup3.c
814
case 9 : c+=((uint32_t)k[8])<<24;
usr.sbin/nsd/lookup3.c
815
case 8 : b+=k[7];
usr.sbin/nsd/lookup3.c
816
case 7 : b+=((uint32_t)k[6])<<8;
usr.sbin/nsd/lookup3.c
817
case 6 : b+=((uint32_t)k[5])<<16;
usr.sbin/nsd/lookup3.c
818
case 5 : b+=((uint32_t)k[4])<<24;
usr.sbin/nsd/lookup3.c
819
case 4 : a+=k[3];
usr.sbin/nsd/lookup3.c
820
case 3 : a+=((uint32_t)k[2])<<8;
usr.sbin/nsd/lookup3.c
821
case 2 : a+=((uint32_t)k[1])<<16;
usr.sbin/nsd/lookup3.c
822
case 1 : a+=((uint32_t)k[0])<<24;
usr.sbin/nsd/lookup3.c
862
uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;
usr.sbin/nsd/lookup3.c
881
for (k=0; k<MAXPAIR; k+=2)
usr.sbin/nsd/lookup3.c
887
a[i] ^= (k<<j);
usr.sbin/nsd/lookup3.c
888
a[i] ^= (k>>(8-j));
usr.sbin/nsd/lookup3.c
890
b[i] ^= ((k+1)<<j);
usr.sbin/nsd/lookup3.c
891
b[i] ^= ((k+1)>>(8-j));
usr.sbin/nsd/lookup3.c
906
if (k>z) z=k;
usr.sbin/nsd/lookup3.c
907
if (k==MAXPAIR)
usr.sbin/nsd/lookup3.h
53
uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);
usr.sbin/nsd/lookup3.h
62
uint32_t hashlittle(const void *k, size_t length, uint32_t initval);
usr.sbin/nsd/nsd-checkconf.c
285
config_print_zone(nsd_options_type* opt, const char* k, int s, const char *o,
usr.sbin/nsd/nsd-checkconf.c
290
if (k) {
usr.sbin/nsd/nsd-checkconf.c
292
key_options_type* key = key_options_find(opt, k);
usr.sbin/nsd/nsd-checkconf.c
301
printf("Could not find key %s\n", k);
usr.sbin/nsd/options.c
1910
struct key_options* k = key_options_find(opt, name);
usr.sbin/nsd/options.c
1911
if(!k) return;
usr.sbin/nsd/options.c
1913
if(k->name)
usr.sbin/nsd/options.c
1914
region_recycle(opt->region, k->name, strlen(k->name)+1);
usr.sbin/nsd/options.c
1915
if(k->algorithm)
usr.sbin/nsd/options.c
1916
region_recycle(opt->region, k->algorithm, strlen(k->algorithm)+1);
usr.sbin/nsd/options.c
1917
if(k->secret) {
usr.sbin/nsd/options.c
1918
memset(k->secret, 0xdd, strlen(k->secret)); /* wipe secret! */
usr.sbin/nsd/options.c
1919
region_recycle(opt->region, k->secret, strlen(k->secret)+1);
usr.sbin/nsd/options.c
1921
if(k->tsig_key) {
usr.sbin/nsd/options.c
1922
tsig_del_key(k->tsig_key);
usr.sbin/nsd/options.c
1923
if(k->tsig_key->name)
usr.sbin/nsd/options.c
1924
region_recycle(opt->region, (void*)k->tsig_key->name,
usr.sbin/nsd/options.c
1925
dname_total_size(k->tsig_key->name));
usr.sbin/nsd/options.c
1926
key_options_desetup(opt->region, k);
usr.sbin/nsd/options.c
1927
region_recycle(opt->region, k->tsig_key, sizeof(tsig_key_type));
usr.sbin/nsd/options.c
1929
region_recycle(opt->region, k, sizeof(struct key_options));
usr.sbin/nsd/radtree.c
1047
void radname_d2r(uint8_t* k, radstrlen_type* len, const uint8_t* dname,
usr.sbin/nsd/radtree.c
1070
assert(k && dname);
usr.sbin/nsd/radtree.c
1103
cpy_d2r(k, labstart[lab]+1, kpos);
usr.sbin/nsd/radtree.c
1107
k[kpos++]=0;
usr.sbin/nsd/radtree.c
1110
cpy_d2r(k+kpos, labstart[lab]+1, *labstart[lab]);
usr.sbin/nsd/radtree.c
1119
void radname_r2d(uint8_t* k, radstrlen_type len, uint8_t* dname, size_t* dlen)
usr.sbin/nsd/radtree.c
1126
assert(k && dname);
usr.sbin/nsd/radtree.c
1139
labstart[lab]=&k[kpos];
usr.sbin/nsd/radtree.c
1141
while(kpos < len && k[kpos] != 0) {
usr.sbin/nsd/radtree.c
1148
assert(k[kpos] == 0);
usr.sbin/nsd/radtree.c
139
static int radix_find_prefix_node(struct radtree* rt, uint8_t* k,
usr.sbin/nsd/radtree.c
152
byte = k[pos];
usr.sbin/nsd/radtree.c
166
if(memcmp(&k[pos], n->array[byte].str,
usr.sbin/nsd/radtree.c
264
radsel_str_create(struct region* region, struct radsel* r, uint8_t* k,
usr.sbin/nsd/radtree.c
270
memmove(r->str, k+pos, len-pos);
usr.sbin/nsd/radtree.c
341
radsel_split(struct region* region, struct radsel* r, uint8_t* k,
usr.sbin/nsd/radtree.c
344
uint8_t* addstr = k+pos;
usr.sbin/nsd/radtree.c
494
struct radnode* radix_insert(struct radtree* rt, uint8_t* k,
usr.sbin/nsd/radtree.c
506
if(!radix_find_prefix_node(rt, k, len, &n, &pos)) {
usr.sbin/nsd/radtree.c
519
if(!radnode_array_space(rt->region, n, k[0])) {
usr.sbin/nsd/radtree.c
530
if(!radsel_prefix_remainder(rt->region, 1, k, len,
usr.sbin/nsd/radtree.c
555
byte = k[pos];
usr.sbin/nsd/radtree.c
569
k, pos+1, len)) {
usr.sbin/nsd/radtree.c
585
k, pos+1, len)) {
usr.sbin/nsd/radtree.c
601
k, pos+1, len, add)) {
usr.sbin/nsd/radtree.c
824
struct radnode* radix_search(struct radtree* rt, uint8_t* k,
usr.sbin/nsd/radtree.c
833
byte = k[pos];
usr.sbin/nsd/radtree.c
844
if(memcmp(&k[pos], n->array[byte].str,
usr.sbin/nsd/radtree.c
863
int radix_find_less_equal(struct radtree* rt, uint8_t* k, radstrlen_type len,
usr.sbin/nsd/radtree.c
876
byte = k[pos];
usr.sbin/nsd/radtree.c
904
if( (memcmp(&k[pos], n->array[byte].str,
usr.sbin/nsd/radtree.c
922
if( (r=memcmp(&k[pos], n->array[byte].str,
usr.sbin/nsd/radtree.h
102
struct radnode* radix_insert(struct radtree* rt, uint8_t* k,
usr.sbin/nsd/radtree.h
120
struct radnode* radix_search(struct radtree* rt, uint8_t* k,
usr.sbin/nsd/radtree.h
133
int radix_find_less_equal(struct radtree* rt, uint8_t* k, radstrlen_type len,
usr.sbin/nsd/radtree.h
178
void radname_d2r(uint8_t* k, radstrlen_type* len, const uint8_t* dname,
usr.sbin/nsd/radtree.h
188
void radname_r2d(uint8_t* k, radstrlen_type len, uint8_t* dname, size_t* dlen);
usr.sbin/nsd/rbtree.h
64
#define RBTREE_WALK(rbtree, k, d) \
usr.sbin/nsd/rbtree.h
66
(rbtree)->_node != RBTREE_NULL && ((k) = (rbtree)->_node->key) && \
usr.sbin/nsd/remote.c
1621
static void add_key(xfrd_state_type* xfrd, struct key_options* k)
usr.sbin/nsd/remote.c
1623
key_options_add_modify(xfrd->nsd->options, k);
usr.sbin/nsd/remote.c
1625
k);
usr.sbin/nsd/remote.c
1633
struct key_options* k;
usr.sbin/nsd/remote.c
1635
k = (struct key_options*)rbtree_first(oldopt->keys);
usr.sbin/nsd/remote.c
1636
while((rbnode_type*)k != RBTREE_NULL) {
usr.sbin/nsd/remote.c
1638
(rbnode_type*)k);
usr.sbin/nsd/remote.c
1639
if(!key_options_find(newopt, k->name))
usr.sbin/nsd/remote.c
1640
remove_key(xfrd, k->name);
usr.sbin/nsd/remote.c
1641
k = next;
usr.sbin/nsd/remote.c
1644
RBTREE_FOR(k, struct key_options*, newopt->keys) {
usr.sbin/nsd/remote.c
1645
struct key_options* origk = key_options_find(oldopt, k->name);
usr.sbin/nsd/remote.c
1647
add_key(xfrd, k);
usr.sbin/nsd/remote.c
1648
else if(!key_options_equal(k, origk))
usr.sbin/nsd/remote.c
1649
add_key(xfrd, k);
usr.sbin/nsd/simdzone/src/haswell/simd.h
51
const __m256i k = _mm256_set1_epi8(key);
usr.sbin/nsd/simdzone/src/haswell/simd.h
52
const __m256i r = _mm256_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/haswell/simd.h
75
const __m128i k = _mm_set1_epi8(key);
usr.sbin/nsd/simdzone/src/haswell/simd.h
76
const __m128i r = _mm_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/haswell/simd.h
95
const __m256i k = _mm256_set1_epi8(key);
usr.sbin/nsd/simdzone/src/haswell/simd.h
97
const __m256i r0 = _mm256_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/haswell/simd.h
98
const __m256i r1 = _mm256_cmpeq_epi8(simd->chunks[1], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
104
const __m128i k = _mm_set1_epi8(key);
usr.sbin/nsd/simdzone/src/westmere/simd.h
106
const __m128i r0 = _mm_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
107
const __m128i r1 = _mm_cmpeq_epi8(simd->chunks[1], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
108
const __m128i r2 = _mm_cmpeq_epi8(simd->chunks[2], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
109
const __m128i r3 = _mm_cmpeq_epi8(simd->chunks[3], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
49
const __m128i k = _mm_set1_epi8(key);
usr.sbin/nsd/simdzone/src/westmere/simd.h
50
const __m128i r = _mm_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
84
const __m128i k = _mm_set1_epi8(key);
usr.sbin/nsd/simdzone/src/westmere/simd.h
85
const __m128i r0 = _mm_cmpeq_epi8(simd->chunks[0], k);
usr.sbin/nsd/simdzone/src/westmere/simd.h
86
const __m128i r1 = _mm_cmpeq_epi8(simd->chunks[1], k);
usr.sbin/nsd/siphash.c
78
int siphash(const uint8_t *in, const size_t inlen, const uint8_t *k,
usr.sbin/nsd/siphash.c
84
uint64_t k0 = U8TO64_LE(k);
usr.sbin/nsd/siphash.c
85
uint64_t k1 = U8TO64_LE(k + 8);
usr.sbin/nsd/xfrd-tcp.c
636
struct xfrd_tcp_pipeline_key k, *key=&k;
usr.sbin/ntpd/parse.y
525
kw_cmp(const void *k, const void *e)
usr.sbin/ntpd/parse.y
527
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ospf6ctl/ospf6ctl.c
1280
struct kroute *k;
usr.sbin/ospf6ctl/ospf6ctl.c
1287
k = imsg->data;
usr.sbin/ospf6ctl/ospf6ctl.c
1289
if (k->flags & F_DOWN)
usr.sbin/ospf6ctl/ospf6ctl.c
1294
if (!(k->flags & F_KERNEL))
usr.sbin/ospf6ctl/ospf6ctl.c
1296
else if (k->flags & F_CONNECTED)
usr.sbin/ospf6ctl/ospf6ctl.c
1298
else if (k->flags & F_STATIC)
usr.sbin/ospf6ctl/ospf6ctl.c
1304
printf("%4d ", k->priority);
usr.sbin/ospf6ctl/ospf6ctl.c
1305
if (asprintf(&p, "%s/%u", log_in6addr(&k->prefix),
usr.sbin/ospf6ctl/ospf6ctl.c
1306
k->prefixlen) == -1)
usr.sbin/ospf6ctl/ospf6ctl.c
1311
if (!IN6_IS_ADDR_UNSPECIFIED(&k->nexthop))
usr.sbin/ospf6ctl/ospf6ctl.c
1312
printf("%s", log_in6addr_scope(&k->nexthop, k->scope));
usr.sbin/ospf6ctl/ospf6ctl.c
1313
else if (k->flags & F_CONNECTED)
usr.sbin/ospf6ctl/ospf6ctl.c
1314
printf("link#%u", k->ifindex);
usr.sbin/ospf6d/parse.y
634
kw_cmp(const void *k, const void *e)
usr.sbin/ospf6d/parse.y
636
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ospfctl/ospfctl.c
258
struct kroute *k;
usr.sbin/ospfctl/ospfctl.c
299
k = imsg->data;
usr.sbin/ospfctl/ospfctl.c
300
output->fib(k);
usr.sbin/ospfctl/output.c
366
show_fib(struct kroute *k)
usr.sbin/ospfctl/output.c
370
if (k->flags & F_DOWN)
usr.sbin/ospfctl/output.c
375
if (!(k->flags & F_KERNEL))
usr.sbin/ospfctl/output.c
377
else if (k->flags & F_CONNECTED)
usr.sbin/ospfctl/output.c
379
else if (k->flags & F_STATIC)
usr.sbin/ospfctl/output.c
385
printf("%4d ", k->priority);
usr.sbin/ospfctl/output.c
386
if (asprintf(&p, "%s/%u", inet_ntoa(k->prefix), k->prefixlen) == -1)
usr.sbin/ospfctl/output.c
392
if (k->nexthop.s_addr)
usr.sbin/ospfctl/output.c
393
printf("%s", inet_ntoa(k->nexthop));
usr.sbin/ospfctl/output.c
394
else if (k->flags & F_CONNECTED)
usr.sbin/ospfctl/output.c
395
printf("link#%u", k->ifindex);
usr.sbin/ospfctl/output.c
401
show_fib_interface(struct kif *k)
usr.sbin/ospfctl/output.c
405
printf("%-15s", k->ifname);
usr.sbin/ospfctl/output.c
406
printf("%-15s", k->flags & IFF_UP ? "UP" : "");
usr.sbin/ospfctl/output.c
407
ifms_type = get_ifms_type(k->if_type);
usr.sbin/ospfctl/output.c
411
printf("%s", get_linkstate(k->if_type, k->link_state));
usr.sbin/ospfctl/output.c
413
if (k->link_state != LINK_STATE_DOWN && k->baudrate > 0) {
usr.sbin/ospfctl/output.c
415
printf("%s", print_baudrate(k->baudrate));
usr.sbin/ospfd/kroute.c
1169
strlcpy(kif->k.ifname, ifan->ifan_name, sizeof(kif->k.ifname));
usr.sbin/ospfd/kroute.c
518
if (ifname == NULL || !strcmp(ifname, kif->k.ifname)) {
usr.sbin/ospfd/kroute.c
520
pid, &kif->k, sizeof(kif->k));
usr.sbin/ospfd/kroute.c
69
struct kif k;
usr.sbin/ospfd/kroute.c
705
return (b->k.ifindex - a->k.ifindex);
usr.sbin/ospfd/kroute.c
843
s.k.ifindex = ifindex;
usr.sbin/ospfd/kroute.c
855
if (!strcmp(ifname, kif->k.ifname)) {
usr.sbin/ospfd/kroute.c
865
return (&kif->k);
usr.sbin/ospfd/kroute.c
879
kif->k.ifindex = ifindex;
usr.sbin/ospfd/kroute.c
924
kif->k.nh_reachable = (flags & IFF_UP) &&
usr.sbin/ospfd/kroute.c
928
kif->k.flags = flags;
usr.sbin/ospfd/kroute.c
929
kif->k.link_state = ifd->ifi_link_state;
usr.sbin/ospfd/kroute.c
930
kif->k.if_type = ifd->ifi_type;
usr.sbin/ospfd/kroute.c
931
kif->k.baudrate = ifd->ifi_baudrate;
usr.sbin/ospfd/kroute.c
932
kif->k.mtu = ifd->ifi_mtu;
usr.sbin/ospfd/kroute.c
933
kif->k.rdomain = ifd->ifi_rdomain;
usr.sbin/ospfd/kroute.c
936
if (sdl->sdl_nlen >= sizeof(kif->k.ifname))
usr.sbin/ospfd/kroute.c
937
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ospfd/kroute.c
938
sizeof(kif->k.ifname) - 1);
usr.sbin/ospfd/kroute.c
940
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ospfd/kroute.c
945
return (&kif->k);
usr.sbin/ospfd/kroute.c
958
return (kif->k.nh_reachable);
usr.sbin/ospfd/parse.y
815
kw_cmp(const void *k, const void *e)
usr.sbin/ospfd/parse.y
817
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/rad/parse.y
507
kw_cmp(const void *k, const void *e)
usr.sbin/rad/parse.y
509
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/radiusd/parse.y
592
kw_cmp(const void *k, const void *e)
usr.sbin/radiusd/parse.y
594
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/relayd/parse.y
2511
kw_cmp(const void *k, const void *e)
usr.sbin/relayd/parse.y
2513
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ripctl/ripctl.c
407
struct kroute *k;
usr.sbin/ripctl/ripctl.c
414
k = imsg->data;
usr.sbin/ripctl/ripctl.c
416
if (k->flags & F_DOWN)
usr.sbin/ripctl/ripctl.c
421
if (k->flags & F_RIPD_INSERTED)
usr.sbin/ripctl/ripctl.c
423
else if (k->flags & F_CONNECTED)
usr.sbin/ripctl/ripctl.c
425
else if (k->flags & F_STATIC)
usr.sbin/ripctl/ripctl.c
431
if (asprintf(&p, "%s/%u", inet_ntoa(k->prefix),
usr.sbin/ripctl/ripctl.c
432
mask2prefixlen(k->netmask.s_addr)) == -1)
usr.sbin/ripctl/ripctl.c
437
if (k->nexthop.s_addr)
usr.sbin/ripctl/ripctl.c
438
printf("%s", inet_ntoa(k->nexthop));
usr.sbin/ripctl/ripctl.c
439
else if (k->flags & F_CONNECTED)
usr.sbin/ripctl/ripctl.c
440
printf("link#%u", k->ifindex);
usr.sbin/ripctl/ripctl.c
464
struct kif *k;
usr.sbin/ripctl/ripctl.c
469
k = imsg->data;
usr.sbin/ripctl/ripctl.c
470
printf("%-15s", k->ifname);
usr.sbin/ripctl/ripctl.c
471
printf("%-15s", k->flags & IFF_UP ? "UP" : "");
usr.sbin/ripctl/ripctl.c
472
ifms_type = get_ifms_type(k->if_type);
usr.sbin/ripctl/ripctl.c
476
printf("%s", get_linkstate(k->if_type, k->link_state));
usr.sbin/ripctl/ripctl.c
478
if (k->link_state != LINK_STATE_DOWN && k->baudrate > 0) {
usr.sbin/ripctl/ripctl.c
480
print_baudrate(k->baudrate);
usr.sbin/ripd/kroute.c
1004
if (sdl->sdl_nlen >= sizeof(kif->k.ifname))
usr.sbin/ripd/kroute.c
1005
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ripd/kroute.c
1006
sizeof(kif->k.ifname) - 1);
usr.sbin/ripd/kroute.c
1008
memcpy(kif->k.ifname, sdl->sdl_data,
usr.sbin/ripd/kroute.c
328
if (ifname == NULL || !strcmp(ifname, kif->k.ifname)) {
usr.sbin/ripd/kroute.c
330
pid, &kif->k, sizeof(kif->k));
usr.sbin/ripd/kroute.c
409
return (b->k.ifindex - a->k.ifindex);
usr.sbin/ripd/kroute.c
496
s.k.ifindex = ifindex;
usr.sbin/ripd/kroute.c
507
if (!strcmp(ifname, kif->k.ifname))
usr.sbin/ripd/kroute.c
508
return (&kif->k);
usr.sbin/ripd/kroute.c
556
return (kif->k.nh_reachable);
usr.sbin/ripd/kroute.c
60
struct kif k;
usr.sbin/ripd/kroute.c
665
kif->k.flags = flags;
usr.sbin/ripd/kroute.c
666
kif->k.link_state = ifd->ifi_link_state;
usr.sbin/ripd/kroute.c
667
kif->k.if_type = ifd->ifi_type;
usr.sbin/ripd/kroute.c
668
kif->k.baudrate = ifd->ifi_baudrate;
usr.sbin/ripd/kroute.c
671
LINK_STATE_IS_UP(ifd->ifi_link_state)) == kif->k.nh_reachable)
usr.sbin/ripd/kroute.c
674
kif->k.nh_reachable = reachable;
usr.sbin/ripd/kroute.c
678
main_imsg_compose_ripe(IMSG_IFINFO, 0, &kif->k, sizeof(kif->k));
usr.sbin/ripd/kroute.c
707
kif->k.ifindex = ifan->ifan_index;
usr.sbin/ripd/kroute.c
708
strlcpy(kif->k.ifname, ifan->ifan_name, sizeof(kif->k.ifname));
usr.sbin/ripd/kroute.c
993
kif->k.ifindex = ifm.ifm_index;
usr.sbin/ripd/kroute.c
994
kif->k.flags = ifm.ifm_flags;
usr.sbin/ripd/kroute.c
995
kif->k.link_state = ifm.ifm_data.ifi_link_state;
usr.sbin/ripd/kroute.c
996
kif->k.if_type = ifm.ifm_data.ifi_type;
usr.sbin/ripd/kroute.c
997
kif->k.baudrate = ifm.ifm_data.ifi_baudrate;
usr.sbin/ripd/kroute.c
998
kif->k.mtu = ifm.ifm_data.ifi_mtu;
usr.sbin/ripd/kroute.c
999
kif->k.nh_reachable = (kif->k.flags & IFF_UP) &&
usr.sbin/ripd/parse.y
418
kw_cmp(const void *k, const void *e)
usr.sbin/ripd/parse.y
420
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/sasyncd/conf.y
278
const struct keyword *k;
usr.sbin/sasyncd/conf.y
280
k = bsearch(token, keywords, sizeof keywords / sizeof keywords[0],
usr.sbin/sasyncd/conf.y
283
return k ? k->value : STRING;
usr.sbin/smtpd/ca.c
102
const char *k;
usr.sbin/smtpd/ca.c
109
while (dict_iter(env->sc_pki_dict, &iter_dict, &k, (void **)&pki)) {
usr.sbin/smtpd/config.c
230
const char *k;
usr.sbin/smtpd/config.c
275
while (dict_iter(env->sc_pki_dict, &iter_dict, &k,
usr.sbin/smtpd/dict.c
102
key.key = k;
usr.sbin/smtpd/dict.c
110
dict_xget(struct dict *d, const char *k)
usr.sbin/smtpd/dict.c
114
key.key = k;
usr.sbin/smtpd/dict.c
116
fatalx("dict_xget(%p, %s)", d, k);
usr.sbin/smtpd/dict.c
122
dict_pop(struct dict *d, const char *k)
usr.sbin/smtpd/dict.c
127
key.key = k;
usr.sbin/smtpd/dict.c
140
dict_xpop(struct dict *d, const char *k)
usr.sbin/smtpd/dict.c
145
key.key = k;
usr.sbin/smtpd/dict.c
147
fatalx("dict_xpop(%p, %s)", d, k);
usr.sbin/smtpd/dict.c
175
dict_root(struct dict *d, const char **k, void **data)
usr.sbin/smtpd/dict.c
182
if (k)
usr.sbin/smtpd/dict.c
183
*k = entry->key;
usr.sbin/smtpd/dict.c
190
dict_iter(struct dict *d, void **hdl, const char **k, void **data)
usr.sbin/smtpd/dict.c
201
if (k)
usr.sbin/smtpd/dict.c
202
*k = curr->key;
usr.sbin/smtpd/dict.c
212
dict_iterfrom(struct dict *d, void **hdl, const char *kfrom, const char **k,
usr.sbin/smtpd/dict.c
234
if (k)
usr.sbin/smtpd/dict.c
235
*k = curr->key;
usr.sbin/smtpd/dict.c
39
dict_check(struct dict *d, const char *k)
usr.sbin/smtpd/dict.c
43
key.key = k;
usr.sbin/smtpd/dict.c
48
dict_alloc(const char *k, void *data)
usr.sbin/smtpd/dict.c
51
size_t s = strlen(k) + 1;
usr.sbin/smtpd/dict.c
59
memmove(t, k, s);
usr.sbin/smtpd/dict.c
65
dict_set(struct dict *d, const char *k, void *data)
usr.sbin/smtpd/dict.c
70
key.key = k;
usr.sbin/smtpd/dict.c
72
if ((entry = dict_alloc(k, data)) == NULL)
usr.sbin/smtpd/dict.c
86
dict_xset(struct dict *d, const char * k, void *data)
usr.sbin/smtpd/dict.c
90
if ((entry = dict_alloc(k, data)) == NULL)
usr.sbin/smtpd/dict.c
93
fatalx("dict_xset(%p, %s)", d, k);
usr.sbin/smtpd/dict.c
98
dict_get(struct dict *d, const char *k)
usr.sbin/smtpd/parse.y
2673
kw_cmp(const void *k, const void *e)
usr.sbin/smtpd/parse.y
2675
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/smtpd/smtpctl.c
92
void stat_increment(const char *k, size_t v)
usr.sbin/smtpd/smtpctl.c
96
void stat_decrement(const char *k, size_t v)
usr.sbin/smtpd/smtpd.c
1101
const char *k;
usr.sbin/smtpd/smtpd.c
1106
while (dict_iter(env->sc_pki_dict, &iter_dict, &k, (void **)&pki)) {
usr.sbin/smtpd/smtpd.c
1107
log_debug("info: loading pki information for %s", k);
usr.sbin/smtpd/smtpd.c
1119
while (dict_iter(env->sc_ca_dict, &iter_dict, &k, (void **)&sca)) {
usr.sbin/smtpd/smtpd.c
1120
log_debug("info: loading CA information for %s", k);
usr.sbin/smtpd/smtpd.c
1130
const char *k;
usr.sbin/smtpd/smtpd.c
1135
while (dict_iter(env->sc_pki_dict, &iter_dict, &k, (void **)&pki)) {
usr.sbin/smtpd/smtpd.c
1136
log_debug("info: loading pki keys for %s", k);
usr.sbin/smtpd/smtpd.c
1138
if (!ssl_load_keyfile(pki, pki->pki_key_file, k))
usr.sbin/smtpd/table_proc.c
220
table_proc_lookup(struct table *table, enum table_service s, const char *k, char **dst)
usr.sbin/smtpd/table_proc.c
231
if (k[strcspn(k, "\r\n")] != '\0')
usr.sbin/smtpd/table_proc.c
234
table_proc_send(table, req, s, k);
usr.sbin/smtpd/table_static.c
273
const char *k;
usr.sbin/smtpd/table_static.c
283
while (dict_iter(&priv->dict, &iter, &k, (void **)&v)) {
usr.sbin/smtpd/table_static.c
285
if (match(key, k)) {
usr.sbin/smtpd/table_static.c
291
if (strcmp(key, k) == 0) {
usr.sbin/smtpd/table_static.c
317
const char *k;
usr.sbin/smtpd/table_static.c
319
if (!dict_iter(&priv->dict, &priv->iter, &k, (void **)NULL)) {
usr.sbin/smtpd/table_static.c
321
if (!dict_iter(&priv->dict, &priv->iter, &k, (void **)NULL))
usr.sbin/smtpd/table_static.c
325
*dst = strdup(k);
usr.sbin/smtpd/tree.c
199
tree_iterfrom(struct tree *t, void **hdl, uint64_t k, uint64_t *id, void **data)
usr.sbin/smtpd/tree.c
204
if (k == 0)
usr.sbin/smtpd/tree.c
207
key.id = k;
usr.sbin/snmpd/parse.y
1276
kw_cmp(const void *k, const void *e)
usr.sbin/snmpd/parse.y
1278
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/tcpdump/addrtoname.c
297
u_int i, j, k;
usr.sbin/tcpdump/addrtoname.c
300
k = (ep[0] << 8) | ep[1];
usr.sbin/tcpdump/addrtoname.c
308
tp->e_addr2 == k)
usr.sbin/tcpdump/addrtoname.c
314
tp->e_addr2 = k;
usr.sbin/tcpdump/addrtoname.c
331
u_int i, j, k;
usr.sbin/tcpdump/addrtoname.c
334
k = (bs[0] << 8) | bs[1];
usr.sbin/tcpdump/addrtoname.c
338
k = (bs[0] << 8) | bs[1];
usr.sbin/tcpdump/addrtoname.c
342
i = j = k = 0;
usr.sbin/tcpdump/addrtoname.c
348
tp->e_addr2 == k &&
usr.sbin/tcpdump/addrtoname.c
356
tp->e_addr2 = k;
usr.sbin/tcpdump/addrtoname.c
374
u_int i, j, k;
usr.sbin/tcpdump/addrtoname.c
380
k = (ensap[0] << 8) | ensap[1];
usr.sbin/tcpdump/addrtoname.c
385
i = j = k = 0;
usr.sbin/tcpdump/addrtoname.c
391
tp->e_addr2 == k &&
usr.sbin/tcpdump/addrtoname.c
400
tp->e_addr2 = k;
usr.sbin/tcpdump/bpf_dump.c
46
insn->jt, insn->jf, insn->k);
usr.sbin/tcpdump/bpf_dump.c
53
insn->code, insn->jt, insn->jf, insn->k);
usr.sbin/tcpdump/print-ospf.c
195
int j, k;
usr.sbin/tcpdump/print-ospf.c
248
for (k = 0; k < (int) rlp->link_toscount; ++k, ++tosp) {
usr.sbin/tcpdump/print-ospf6.c
220
int k;
usr.sbin/tcpdump/print-ospf6.c
224
k = (lsapp->lsa_p_len + 31) / 32;
usr.sbin/tcpdump/print-ospf6.c
225
if (k * 4 > sizeof(struct in6_addr)) {
usr.sbin/tcpdump/print-ospf6.c
230
memcpy(&prefix, lsapp->lsa_p_prefix, k * 4);
usr.sbin/tcpdump/print-ospf6.c
235
return sizeof(*lsapp) - 4 + k * 4;
usr.sbin/tcpdump/print-ospf6.c
263
int j, k;
usr.sbin/tcpdump/print-ospf6.c
335
k = ospf6_print_lsaprefix(lsapp);
usr.sbin/tcpdump/print-ospf6.c
336
if (k < 0)
usr.sbin/tcpdump/print-ospf6.c
338
lsapp = (struct lsa_prefix *)(((u_char *)lsapp) + k);
usr.sbin/tcpdump/print-ospf6.c
425
k = ospf6_print_lsaprefix(lsapp);
usr.sbin/tcpdump/print-ospf6.c
426
if (k < 0)
usr.sbin/tcpdump/print-ospf6.c
428
lsapp = (struct lsa_prefix *)(((u_char *)lsapp) + k);
usr.sbin/tcpdump/print-ospf6.c
448
k = ospf6_print_lsaprefix(lsapp);
usr.sbin/tcpdump/print-ospf6.c
449
if (k < 0)
usr.sbin/tcpdump/print-ospf6.c
451
lsapp = (struct lsa_prefix *)(((u_char *)lsapp) + k);
usr.sbin/tcpdump/print-radius.c
174
u_int32_t k = ntohl((*(int *)data));
usr.sbin/tcpdump/print-radius.c
179
if(k < i) {
usr.sbin/tcpdump/print-radius.c
181
atp->values[k]);
usr.sbin/unbound/daemon/cachedump.c
103
if(!packed_rr_to_string(k, i, now, s, sizeof(s))) {
usr.sbin/unbound/daemon/cachedump.c
112
dump_rrset(struct config_strlist_head* txt, struct ub_packed_rrset_key* k,
usr.sbin/unbound/daemon/cachedump.c
117
if(!k || !d) return;
usr.sbin/unbound/daemon/cachedump.c
118
if(k->id == 0) return; /* deleted */
usr.sbin/unbound/daemon/cachedump.c
123
(k->rk.flags & PACKED_RRSET_NSEC_AT_APEX)?" nsec_apex":"",
usr.sbin/unbound/daemon/cachedump.c
129
dump_rrset_line(txt, k, now, i);
usr.sbin/unbound/daemon/cachedump.c
289
dump_msg_ref(struct config_strlist_head* txt, struct ub_packed_rrset_key* k)
usr.sbin/unbound/daemon/cachedump.c
292
nm = sldns_wire2str_dname(k->rk.dname, k->rk.dname_len);
usr.sbin/unbound/daemon/cachedump.c
293
tp = sldns_wire2str_type(ntohs(k->rk.type));
usr.sbin/unbound/daemon/cachedump.c
294
cl = sldns_wire2str_class(ntohs(k->rk.rrset_class));
usr.sbin/unbound/daemon/cachedump.c
302
spool_txt_printf(txt, "%s %s %s %d\n", nm, cl, tp, (int)k->rk.flags);
usr.sbin/unbound/daemon/cachedump.c
310
dump_msg(struct config_strlist_head* txt, struct query_info* k,
usr.sbin/unbound/daemon/cachedump.c
315
if(!k || !d) return;
usr.sbin/unbound/daemon/cachedump.c
318
nm = sldns_wire2str_dname(k->qname, k->qname_len);
usr.sbin/unbound/daemon/cachedump.c
319
tp = sldns_wire2str_type(k->qtype);
usr.sbin/unbound/daemon/cachedump.c
320
cl = sldns_wire2str_class(k->qclass);
usr.sbin/unbound/daemon/cachedump.c
359
struct query_info** k, struct reply_info** d)
usr.sbin/unbound/daemon/cachedump.c
373
*k = (struct query_info*)regional_alloc_init(region,
usr.sbin/unbound/daemon/cachedump.c
375
if(!*k)
usr.sbin/unbound/daemon/cachedump.c
377
(*k)->qname = regional_alloc_init(region,
usr.sbin/unbound/daemon/cachedump.c
378
(*k)->qname, (*k)->qname_len);
usr.sbin/unbound/daemon/cachedump.c
379
return (*k)->qname != NULL;
usr.sbin/unbound/daemon/cachedump.c
388
struct query_info* k;
usr.sbin/unbound/daemon/cachedump.c
394
if(!copy_msg(dump_info->worker->scratchpad, e, &k, &d)) {
usr.sbin/unbound/daemon/cachedump.c
402
dump_msg(txt, k, d, *dump_info->worker->env.now);
usr.sbin/unbound/daemon/cachedump.c
505
move_into_cache(struct ub_packed_rrset_key* k,
usr.sbin/unbound/daemon/cachedump.c
520
ak->rk = k->rk;
usr.sbin/unbound/daemon/cachedump.c
521
ak->entry.hash = rrset_key_hash(&k->rk);
usr.sbin/unbound/daemon/cachedump.c
522
ak->rk.dname = (uint8_t*)memdup(k->rk.dname, k->rk.dname_len);
usr.sbin/unbound/daemon/cachedump.c
712
struct ub_packed_rrset_key* k;
usr.sbin/unbound/daemon/cachedump.c
732
k = rrset_cache_lookup(worker->env.rrset_cache, qinfo.qname,
usr.sbin/unbound/daemon/cachedump.c
735
if(!k) {
usr.sbin/unbound/daemon/cachedump.c
742
*rrset = packed_rrset_copy_region(k, region, *worker->env.now);
usr.sbin/unbound/daemon/cachedump.c
743
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/daemon/cachedump.c
934
struct ub_packed_rrset_key* k = msg->rep->rrsets[i];
usr.sbin/unbound/daemon/cachedump.c
936
(struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/daemon/cachedump.c
943
dump_rrset(&txt, k, d, 0);
usr.sbin/unbound/daemon/cachedump.c
99
dump_rrset_line(struct config_strlist_head* txt, struct ub_packed_rrset_key* k,
usr.sbin/unbound/daemon/daemon.c
747
int i, n, k, temp;
usr.sbin/unbound/daemon/daemon.c
761
k = ub_random_max(daemon->rand, n+1); /* 0<= k<= n */
usr.sbin/unbound/daemon/daemon.c
762
temp = shufport[k];
usr.sbin/unbound/daemon/daemon.c
763
shufport[k] = shufport[n];
usr.sbin/unbound/daemon/remote.c
1937
struct msgreply_entry *k = (struct msgreply_entry*)e->key;
usr.sbin/unbound/daemon/remote.c
1940
if(!dname_subdomain_c(k->key.qname, inf->nm))
usr.sbin/unbound/daemon/remote.c
1944
addrtree_traverse(d->tree4, 0, *inf->worker->env.now, &k->key,
usr.sbin/unbound/daemon/remote.c
1948
addrtree_traverse(d->tree6, 1, *inf->worker->env.now, &k->key,
usr.sbin/unbound/daemon/remote.c
1958
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)e->key;
usr.sbin/unbound/daemon/remote.c
1961
k->id != 0 && /* not deleted */
usr.sbin/unbound/daemon/remote.c
1962
dname_subdomain_c(k->rk.dname, inf->nm)) {
usr.sbin/unbound/daemon/remote.c
1966
if(!packed_rr_to_string(k, i, *inf->worker->env.now,
usr.sbin/unbound/daemon/remote.c
1981
struct msgreply_entry* k = (struct msgreply_entry*)e->key;
usr.sbin/unbound/daemon/remote.c
1984
dname_subdomain_c(k->key.qname, inf->nm)) {
usr.sbin/unbound/daemon/remote.c
1987
sldns_wire2str_dname_buf(k->key.qname, k->key.qname_len,
usr.sbin/unbound/daemon/remote.c
1989
sldns_wire2str_type_buf(k->key.qtype, tp, sizeof(tp));
usr.sbin/unbound/daemon/remote.c
1990
sldns_wire2str_class_buf(k->key.qclass, cl, sizeof(cl));
usr.sbin/unbound/daemon/remote.c
2136
struct query_info k;
usr.sbin/unbound/daemon/remote.c
2141
k.qname = nm;
usr.sbin/unbound/daemon/remote.c
2142
k.qname_len = nmlen;
usr.sbin/unbound/daemon/remote.c
2143
k.qtype = t;
usr.sbin/unbound/daemon/remote.c
2144
k.qclass = c;
usr.sbin/unbound/daemon/remote.c
2145
k.local_alias = NULL;
usr.sbin/unbound/daemon/remote.c
2146
h = query_info_hash(&k, 0);
usr.sbin/unbound/daemon/remote.c
2147
slabhash_remove(worker->env.msg_cache, h, &k);
usr.sbin/unbound/daemon/remote.c
2150
h = query_info_hash(&k, BIT_CD);
usr.sbin/unbound/daemon/remote.c
2151
slabhash_remove(worker->env.msg_cache, h, &k);
usr.sbin/unbound/daemon/remote.c
2155
cachedb_msg_remove_qinfo(&worker->env, &k);
usr.sbin/unbound/daemon/remote.c
2248
struct infra_key* k = (struct infra_key*)e->key;
usr.sbin/unbound/daemon/remote.c
2249
if(sockaddr_cmp(&inf->addr, inf->addrlen, &k->addr, k->addrlen) == 0) {
usr.sbin/unbound/daemon/remote.c
2312
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)e->key;
usr.sbin/unbound/daemon/remote.c
2313
if(dname_subdomain_c(k->rk.dname, inf->name)) {
usr.sbin/unbound/daemon/remote.c
2329
struct msgreply_entry* k = (struct msgreply_entry*)e->key;
usr.sbin/unbound/daemon/remote.c
2330
if(dname_subdomain_c(k->key.qname, inf->name)) {
usr.sbin/unbound/daemon/remote.c
2340
cachedb_msg_remove_qinfo(&inf->worker->env, &k->key);
usr.sbin/unbound/daemon/remote.c
2351
struct key_entry_key* k = (struct key_entry_key*)e->key;
usr.sbin/unbound/daemon/remote.c
2352
if(dname_subdomain_c(k->name, inf->name)) {
usr.sbin/unbound/daemon/remote.c
2488
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)e->key;
usr.sbin/unbound/daemon/remote.c
2492
if((k->rk.flags & PACKED_RRSET_PARENT_SIDE) && d->count == 1 &&
usr.sbin/unbound/daemon/remote.c
3146
struct infra_key* k = (struct infra_key*)e->key;
usr.sbin/unbound/daemon/remote.c
3153
addr_to_str(&k->addr, k->addrlen, ip_str, sizeof(ip_str));
usr.sbin/unbound/daemon/remote.c
3154
dname_str(k->zonename, name);
usr.sbin/unbound/daemon/remote.c
3155
port = (int)ntohs(((struct sockaddr_in*)&k->addr)->sin_port);
usr.sbin/unbound/daemon/remote.c
3581
struct rate_key* k = (struct rate_key*)e->key;
usr.sbin/unbound/daemon/remote.c
3584
int lim = infra_find_ratelimit(a->infra, k->name, k->namelen);
usr.sbin/unbound/daemon/remote.c
3590
dname_str(k->name, buf);
usr.sbin/unbound/daemon/remote.c
3600
struct ip_rate_key* k = (struct ip_rate_key*)e->key;
usr.sbin/unbound/daemon/remote.c
3608
addr_to_str(&k->addr, k->addrlen, ip, sizeof(ip));
usr.sbin/unbound/dnscrypt/dnscrypt.c
1053
dnsc_shared_secrets_sizefunc(void *k, void* ATTR_UNUSED(d))
usr.sbin/unbound/dnscrypt/dnscrypt.c
1055
struct shared_secret_cache_key* ssk = (struct shared_secret_cache_key*)k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
1070
dnsc_shared_secrets_delkeyfunc(void *k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/dnscrypt/dnscrypt.c
1072
struct shared_secret_cache_key* ssk = (struct shared_secret_cache_key*)k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
1091
dnsc_nonces_sizefunc(void *k, void* ATTR_UNUSED(d))
usr.sbin/unbound/dnscrypt/dnscrypt.c
1093
struct nonce_cache_key* nk = (struct nonce_cache_key*)k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
1119
dnsc_nonces_delkeyfunc(void *k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/dnscrypt/dnscrypt.c
1121
struct nonce_cache_key* nk = (struct nonce_cache_key*)k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
114
struct shared_secret_cache_key* k =
usr.sbin/unbound/dnscrypt/dnscrypt.c
115
(struct shared_secret_cache_key*)calloc(1, sizeof(*k));
usr.sbin/unbound/dnscrypt/dnscrypt.c
117
if(!k || !d) {
usr.sbin/unbound/dnscrypt/dnscrypt.c
118
free(k);
usr.sbin/unbound/dnscrypt/dnscrypt.c
123
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/dnscrypt/dnscrypt.c
124
memcpy(k->key, key, DNSCRYPT_SHARED_SECRET_KEY_LENGTH);
usr.sbin/unbound/dnscrypt/dnscrypt.c
125
k->entry.hash = hash;
usr.sbin/unbound/dnscrypt/dnscrypt.c
126
k->entry.key = k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
127
k->entry.data = d;
usr.sbin/unbound/dnscrypt/dnscrypt.c
129
hash, &k->entry,
usr.sbin/unbound/dnscrypt/dnscrypt.c
185
struct nonce_cache_key* k =
usr.sbin/unbound/dnscrypt/dnscrypt.c
186
(struct nonce_cache_key*)calloc(1, sizeof(*k));
usr.sbin/unbound/dnscrypt/dnscrypt.c
187
if(!k) {
usr.sbin/unbound/dnscrypt/dnscrypt.c
188
free(k);
usr.sbin/unbound/dnscrypt/dnscrypt.c
191
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/dnscrypt/dnscrypt.c
192
memcpy(k->nonce, nonce, crypto_box_HALF_NONCEBYTES);
usr.sbin/unbound/dnscrypt/dnscrypt.c
193
memcpy(k->magic_query, magic_query, DNSCRYPT_MAGIC_HEADER_LEN);
usr.sbin/unbound/dnscrypt/dnscrypt.c
194
memcpy(k->client_publickey, pk, crypto_box_PUBLICKEYBYTES);
usr.sbin/unbound/dnscrypt/dnscrypt.c
195
k->entry.hash = hash;
usr.sbin/unbound/dnscrypt/dnscrypt.c
196
k->entry.key = k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
197
k->entry.data = NULL;
usr.sbin/unbound/dnscrypt/dnscrypt.c
199
hash, &k->entry,
usr.sbin/unbound/dnscrypt/dnscrypt.c
221
struct nonce_cache_key k;
usr.sbin/unbound/dnscrypt/dnscrypt.c
222
memset(&k, 0, sizeof(k));
usr.sbin/unbound/dnscrypt/dnscrypt.c
223
k.entry.hash = hash;
usr.sbin/unbound/dnscrypt/dnscrypt.c
224
memcpy(k.nonce, nonce, crypto_box_HALF_NONCEBYTES);
usr.sbin/unbound/dnscrypt/dnscrypt.c
225
memcpy(k.magic_query, magic_query, DNSCRYPT_MAGIC_HEADER_LEN);
usr.sbin/unbound/dnscrypt/dnscrypt.c
226
memcpy(k.client_publickey, pk, crypto_box_PUBLICKEYBYTES);
usr.sbin/unbound/dnscrypt/dnscrypt.c
228
return slabhash_lookup(cache, hash, &k, 0);
usr.sbin/unbound/dnscrypt/dnscrypt.h
137
size_t dnsc_shared_secrets_sizefunc(void *k, void *d);
usr.sbin/unbound/dnscrypt/dnscrypt.h
147
void dnsc_shared_secrets_delkeyfunc(void *k, void* arg);
usr.sbin/unbound/dnscrypt/dnscrypt.h
157
size_t dnsc_nonces_sizefunc(void *k, void *d);
usr.sbin/unbound/dnscrypt/dnscrypt.h
167
void dnsc_nonces_delkeyfunc(void *k, void* arg);
usr.sbin/unbound/edns-subnet/subnetmod.c
79
msg_cache_sizefunc(void *k, void *d)
usr.sbin/unbound/edns-subnet/subnetmod.c
81
struct msgreply_entry *q = (struct msgreply_entry*)k;
usr.sbin/unbound/edns-subnet/subnetmod.h
126
size_t msg_cache_sizefunc(void* k, void* d);
usr.sbin/unbound/iterator/iter_scrub.c
846
struct ub_packed_rrset_key* k;
usr.sbin/unbound/iterator/iter_scrub.c
851
k = alloc_special_obtain(env->alloc);
usr.sbin/unbound/iterator/iter_scrub.c
852
if(!k)
usr.sbin/unbound/iterator/iter_scrub.c
854
k->entry.data = NULL;
usr.sbin/unbound/iterator/iter_scrub.c
855
if(!parse_copy_decompress_rrset(pkt, msg, rrset, NULL, k)) {
usr.sbin/unbound/iterator/iter_scrub.c
856
alloc_special_release(env->alloc, k);
usr.sbin/unbound/iterator/iter_scrub.c
859
d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/iterator/iter_scrub.c
861
ref.key = k;
usr.sbin/unbound/iterator/iter_scrub.c
862
ref.id = k->id;
usr.sbin/unbound/services/authzone.c
164
get_rrset_ttl(struct ub_packed_rrset_key* k)
usr.sbin/unbound/services/authzone.c
167
k->entry.data;
usr.sbin/unbound/services/authzone.c
213
struct ub_packed_rrset_key* k = msg->rep->rrsets[i];
usr.sbin/unbound/services/authzone.c
214
if(ntohs(k->rk.type) == type && k->rk.dname_len == nmlen &&
usr.sbin/unbound/services/authzone.c
215
ntohs(k->rk.rrset_class) == dclass &&
usr.sbin/unbound/services/authzone.c
216
query_dname_compare(k->rk.dname, nm) == 0)
usr.sbin/unbound/services/cache/dns.c
1027
struct dns_msg* msg = rrset_msg(rrset, region, now, &k);
usr.sbin/unbound/services/cache/dns.c
1054
struct dns_msg* msg = rrset_msg(rrset, region, now, &k);
usr.sbin/unbound/services/cache/dns.c
1068
while(!dname_is_root(k.qname)) {
usr.sbin/unbound/services/cache/dns.c
1070
&& !dname_strict_subdomain_c(k.qname, dpname))
usr.sbin/unbound/services/cache/dns.c
1072
dname_remove_label(&k.qname, &k.qname_len);
usr.sbin/unbound/services/cache/dns.c
1073
h = query_info_hash(&k, flags);
usr.sbin/unbound/services/cache/dns.c
1074
e = slabhash_lookup(env->msg_cache, h, &k, 0);
usr.sbin/unbound/services/cache/dns.c
1075
if(!e && k.qtype != LDNS_RR_TYPE_A &&
usr.sbin/unbound/services/cache/dns.c
1077
k.qtype = LDNS_RR_TYPE_A;
usr.sbin/unbound/services/cache/dns.c
1078
h = query_info_hash(&k, flags);
usr.sbin/unbound/services/cache/dns.c
1079
e = slabhash_lookup(env->msg_cache, h, &k, 0);
usr.sbin/unbound/services/cache/dns.c
1088
&& (msg=tomsg(env, &k, data, region, now, 0, scratch))) {
usr.sbin/unbound/services/cache/dns.c
1099
k.qtype = qtype;
usr.sbin/unbound/services/cache/dns.c
151
struct query_info k;
usr.sbin/unbound/services/cache/dns.c
154
k.qname = qname;
usr.sbin/unbound/services/cache/dns.c
155
k.qname_len = qnamelen;
usr.sbin/unbound/services/cache/dns.c
156
k.qtype = qtype;
usr.sbin/unbound/services/cache/dns.c
157
k.qclass = qclass;
usr.sbin/unbound/services/cache/dns.c
158
k.local_alias = NULL;
usr.sbin/unbound/services/cache/dns.c
159
h = query_info_hash(&k, flags);
usr.sbin/unbound/services/cache/dns.c
160
slabhash_remove(env->msg_cache, h, &k);
usr.sbin/unbound/services/cache/dns.c
308
struct query_info k;
usr.sbin/unbound/services/cache/dns.c
311
k.qname = qname;
usr.sbin/unbound/services/cache/dns.c
312
k.qname_len = qnamelen;
usr.sbin/unbound/services/cache/dns.c
313
k.qtype = qtype;
usr.sbin/unbound/services/cache/dns.c
314
k.qclass = qclass;
usr.sbin/unbound/services/cache/dns.c
315
k.local_alias = NULL;
usr.sbin/unbound/services/cache/dns.c
316
h = query_info_hash(&k, flags);
usr.sbin/unbound/services/cache/dns.c
317
e = slabhash_lookup(env->msg_cache, h, &k, wr);
usr.sbin/unbound/services/cache/dns.c
950
struct query_info k;
usr.sbin/unbound/services/cache/dns.c
956
k.qname = qname;
usr.sbin/unbound/services/cache/dns.c
957
k.qname_len = qnamelen;
usr.sbin/unbound/services/cache/dns.c
958
k.qtype = qtype;
usr.sbin/unbound/services/cache/dns.c
959
k.qclass = qclass;
usr.sbin/unbound/services/cache/dns.c
960
k.local_alias = NULL;
usr.sbin/unbound/services/cache/dns.c
961
h = query_info_hash(&k, flags);
usr.sbin/unbound/services/cache/dns.c
962
e = slabhash_lookup(env->msg_cache, h, &k, 0);
usr.sbin/unbound/services/cache/dns.c
984
struct dns_msg* msg = synth_dname_msg(rrset, region, now, &k,
usr.sbin/unbound/services/cache/infra.c
1002
k->namelen = namelen;
usr.sbin/unbound/services/cache/infra.c
1003
k->name = memdup(name, namelen);
usr.sbin/unbound/services/cache/infra.c
1004
if(!k->name) {
usr.sbin/unbound/services/cache/infra.c
1005
free(k);
usr.sbin/unbound/services/cache/infra.c
1009
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/services/cache/infra.c
1010
k->entry.hash = h;
usr.sbin/unbound/services/cache/infra.c
1011
k->entry.key = k;
usr.sbin/unbound/services/cache/infra.c
1012
k->entry.data = d;
usr.sbin/unbound/services/cache/infra.c
1015
slabhash_insert(infra->domain_rates, h, &k->entry, d, NULL);
usr.sbin/unbound/services/cache/infra.c
1024
struct ip_rate_key* k = (struct ip_rate_key*)calloc(1, sizeof(*k));
usr.sbin/unbound/services/cache/infra.c
1026
if(!k || !d) {
usr.sbin/unbound/services/cache/infra.c
1027
free(k);
usr.sbin/unbound/services/cache/infra.c
1031
k->addr = *addr;
usr.sbin/unbound/services/cache/infra.c
1032
k->addrlen = addrlen;
usr.sbin/unbound/services/cache/infra.c
1033
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/services/cache/infra.c
1034
k->entry.hash = h;
usr.sbin/unbound/services/cache/infra.c
1035
k->entry.key = k;
usr.sbin/unbound/services/cache/infra.c
1036
k->entry.data = d;
usr.sbin/unbound/services/cache/infra.c
1040
slabhash_insert(infra->client_ip_rates, h, &k->entry, d, NULL);
usr.sbin/unbound/services/cache/infra.c
106
infra_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/services/cache/infra.c
108
struct infra_key* key = (struct infra_key*)k;
usr.sbin/unbound/services/cache/infra.c
124
rate_sizefunc(void* k, void* ATTR_UNUSED(d))
usr.sbin/unbound/services/cache/infra.c
126
struct rate_key* key = (struct rate_key*)k;
usr.sbin/unbound/services/cache/infra.c
145
rate_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/services/cache/infra.c
147
struct rate_key* key = (struct rate_key*)k;
usr.sbin/unbound/services/cache/infra.c
515
struct infra_key k;
usr.sbin/unbound/services/cache/infra.c
516
k.addrlen = addrlen;
usr.sbin/unbound/services/cache/infra.c
517
memcpy(&k.addr, addr, addrlen);
usr.sbin/unbound/services/cache/infra.c
518
k.namelen = namelen;
usr.sbin/unbound/services/cache/infra.c
519
k.zonename = name;
usr.sbin/unbound/services/cache/infra.c
520
k.entry.hash = hash_infra(addr, addrlen, name);
usr.sbin/unbound/services/cache/infra.c
521
k.entry.key = (void*)&k;
usr.sbin/unbound/services/cache/infra.c
522
k.entry.data = NULL;
usr.sbin/unbound/services/cache/infra.c
523
return slabhash_lookup(infra->hosts, k.entry.hash, &k, wr);
usr.sbin/unbound/services/cache/infra.c
82
infra_sizefunc(void* k, void* ATTR_UNUSED(d))
usr.sbin/unbound/services/cache/infra.c
84
struct infra_key* key = (struct infra_key*)k;
usr.sbin/unbound/services/cache/infra.c
940
size_t ip_rate_sizefunc(void* k, void* ATTR_UNUSED(d))
usr.sbin/unbound/services/cache/infra.c
942
struct ip_rate_key* key = (struct ip_rate_key*)k;
usr.sbin/unbound/services/cache/infra.c
955
void ip_rate_delkeyfunc(void* k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/services/cache/infra.c
957
struct ip_rate_key* key = (struct ip_rate_key*)k;
usr.sbin/unbound/services/cache/infra.c
995
struct rate_key* k = (struct rate_key*)calloc(1, sizeof(*k));
usr.sbin/unbound/services/cache/infra.c
997
if(!k || !d) {
usr.sbin/unbound/services/cache/infra.c
998
free(k);
usr.sbin/unbound/services/cache/infra.h
471
size_t infra_sizefunc(void* k, void* d);
usr.sbin/unbound/services/cache/infra.h
477
void infra_delkeyfunc(void* k, void* arg);
usr.sbin/unbound/services/cache/infra.h
483
size_t rate_sizefunc(void* k, void* d);
usr.sbin/unbound/services/cache/infra.h
489
void rate_delkeyfunc(void* k, void* arg);
usr.sbin/unbound/services/cache/infra.h
495
size_t ip_rate_sizefunc(void* k, void* d);
usr.sbin/unbound/services/cache/rrset.c
212
struct ub_packed_rrset_key* k = ref->key;
usr.sbin/unbound/services/cache/rrset.c
213
hashvalue_type h = k->entry.hash;
usr.sbin/unbound/services/cache/rrset.c
214
uint16_t rrset_type = ntohs(k->rk.type);
usr.sbin/unbound/services/cache/rrset.c
216
log_assert(ref->id != 0 && k->id != 0);
usr.sbin/unbound/services/cache/rrset.c
217
log_assert(k->rk.dname != NULL);
usr.sbin/unbound/services/cache/rrset.c
219
if((e=slabhash_lookup(&r->table, h, k, 0)) != 0) {
usr.sbin/unbound/services/cache/rrset.c
229
equal = rrsetdata_equal((struct packed_rrset_data*)k->entry.
usr.sbin/unbound/services/cache/rrset.c
231
if(!need_to_update_rrset(k->entry.data, e->data, timenow,
usr.sbin/unbound/services/cache/rrset.c
236
ub_packed_rrset_parsedelete(k, alloc);
usr.sbin/unbound/services/cache/rrset.c
250
slabhash_insert(&r->table, h, &k->entry, k->entry.data, alloc);
usr.sbin/unbound/services/cache/rrset.c
355
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)e->key;
usr.sbin/unbound/services/cache/rrset.c
359
(k->rk.flags & PACKED_RRSET_UPSTREAM_0TTL) &&
usr.sbin/unbound/services/cache/rrset.c
368
return k;
usr.sbin/unbound/services/outside_network.c
1733
size_t k;
usr.sbin/unbound/services/outside_network.c
1813
for(k=0; k<num_ports; k++) {
usr.sbin/unbound/services/outside_network.c
1932
int i, k;
usr.sbin/unbound/services/outside_network.c
1934
for(k=0; k<outnet->ip4_ifs[i].inuse; k++) {
usr.sbin/unbound/services/outside_network.c
1936
out[k];
usr.sbin/unbound/services/outside_network.c
1945
int i, k;
usr.sbin/unbound/services/outside_network.c
1947
for(k=0; k<outnet->ip6_ifs[i].inuse; k++) {
usr.sbin/unbound/services/outside_network.c
1949
out[k];
usr.sbin/unbound/services/outside_network.c
3965
int k;
usr.sbin/unbound/services/outside_network.c
3978
for(k=0; k<outnet->num_ip4; k++)
usr.sbin/unbound/services/outside_network.c
3979
s += if_get_mem(&outnet->ip4_ifs[k]);
usr.sbin/unbound/services/outside_network.c
3980
for(k=0; k<outnet->num_ip6; k++)
usr.sbin/unbound/services/outside_network.c
3981
s += if_get_mem(&outnet->ip6_ifs[k]);
usr.sbin/unbound/testcode/fake_event.c
720
struct query_info k;
usr.sbin/unbound/testcode/fake_event.c
727
k.qname = rr;
usr.sbin/unbound/testcode/fake_event.c
728
k.qname_len = dname_len;
usr.sbin/unbound/testcode/fake_event.c
729
k.qtype = sldns_wirerr_get_type(rr, rr_len, dname_len);
usr.sbin/unbound/testcode/fake_event.c
730
k.qclass = sldns_wirerr_get_class(rr, rr_len, dname_len);
usr.sbin/unbound/testcode/fake_event.c
731
k.local_alias = NULL;
usr.sbin/unbound/testcode/fake_event.c
732
h = query_info_hash(&k, 0);
usr.sbin/unbound/testcode/fake_event.c
733
slabhash_remove(runtime->daemon->env->msg_cache, h, &k);
usr.sbin/unbound/testcode/fake_event.c
744
struct query_info k;
usr.sbin/unbound/testcode/fake_event.c
752
k.qname = rr;
usr.sbin/unbound/testcode/fake_event.c
753
k.qname_len = dname_len;
usr.sbin/unbound/testcode/fake_event.c
754
k.qtype = sldns_wirerr_get_type(rr, rr_len, dname_len);
usr.sbin/unbound/testcode/fake_event.c
755
k.qclass = sldns_wirerr_get_class(rr, rr_len, dname_len);
usr.sbin/unbound/testcode/fake_event.c
756
k.local_alias = NULL;
usr.sbin/unbound/testcode/fake_event.c
757
h = query_info_hash(&k, 0);
usr.sbin/unbound/testcode/fake_event.c
759
e = slabhash_lookup(runtime->daemon->env->msg_cache, h, &k, 0);
usr.sbin/unbound/testcode/replay.c
646
struct replay_var k;
usr.sbin/unbound/testcode/replay.c
647
k.node.key = &k;
usr.sbin/unbound/testcode/replay.c
648
k.name = name;
usr.sbin/unbound/testcode/replay.c
649
return (struct replay_var*)rbtree_search(store, &k);
usr.sbin/unbound/testcode/signit.c
129
ldns_key* k;
usr.sbin/unbound/testcode/signit.c
141
s = ldns_key_new_frm_fp(&k, in);
usr.sbin/unbound/testcode/signit.c
146
ldns_key_set_expiration(k, set->expi);
usr.sbin/unbound/testcode/signit.c
147
ldns_key_set_inception(k, set->incep);
usr.sbin/unbound/testcode/signit.c
152
ldns_key_set_pubkey_owner(k, rdf);
usr.sbin/unbound/testcode/signit.c
153
ldns_key_set_flags(k, set->flags);
usr.sbin/unbound/testcode/signit.c
154
ldns_key_set_keytag(k, set->keytag);
usr.sbin/unbound/testcode/signit.c
155
b = ldns_key_list_push_key(keys, k);
usr.sbin/unbound/testcode/unitecs.c
138
static addrlen_t randomkey(addrkey_t **k, int maxlen)
usr.sbin/unbound/testcode/unitecs.c
143
*k = (addrkey_t *) malloc(bytes * sizeof(addrkey_t));
usr.sbin/unbound/testcode/unitecs.c
145
(*k)[byte] = (addrkey_t)(rand() & 0xFF);
usr.sbin/unbound/testcode/unitecs.c
162
addrkey_t *k;
usr.sbin/unbound/testcode/unitecs.c
174
l = randomkey(&k, 128);
usr.sbin/unbound/testcode/unitecs.c
176
addrtree_insert(t, k, l, 64, elem, timenow + 10, timenow, 0);
usr.sbin/unbound/testcode/unitecs.c
181
free(k);
usr.sbin/unbound/testcode/unitecs.c
190
l = randomkey(&k, 128);
usr.sbin/unbound/testcode/unitecs.c
192
addrtree_insert(t, k, l, 64, elem, i + 10, i, 0);
usr.sbin/unbound/testcode/unitecs.c
193
free(k);
usr.sbin/unbound/testcode/unitecs.c
202
l = randomkey(&k, 128);
usr.sbin/unbound/testcode/unitecs.c
204
addrtree_insert(t, k, l, 64, elem, i + 10, i, 0);
usr.sbin/unbound/testcode/unitecs.c
206
free(k);
usr.sbin/unbound/testcode/unitinfra.c
101
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/testcode/unitinfra.c
126
struct infra_key* k;
usr.sbin/unbound/testcode/unitinfra.c
162
unit_assert( (d=infra_lookup_host(slab, &one, onelen, zone, zonelen, 0, now, &k)) );
usr.sbin/unbound/testcode/unitinfra.c
167
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/testcode/unitinfra.c
172
unit_assert( (d=infra_lookup_host(slab, &one, onelen, zone, zonelen, 0, now, &k)) );
usr.sbin/unbound/testcode/unitinfra.c
175
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/testcode/unitinfra.c
51
size_t zonelen, int wr, time_t now, struct infra_key** k)
usr.sbin/unbound/testcode/unitinfra.c
62
*k = (struct infra_key*)e->key;
usr.sbin/unbound/testcode/unitinfra.c
73
struct infra_key* k;
usr.sbin/unbound/testcode/unitinfra.c
97
unit_assert( (d=infra_lookup_host(slab, &one, onelen, zone, zonelen, 0, *now, &k)) );
usr.sbin/unbound/testcode/unitlruhash.c
101
bin.overflow_list = &k->entry;
usr.sbin/unbound/testcode/unitlruhash.c
105
unit_assert( bin_find_entry(table, &bin, myhash(13), k, NULL) == NULL );
usr.sbin/unbound/testcode/unitlruhash.c
108
unit_assert( k->entry.hash == k2->entry.hash );
usr.sbin/unbound/testcode/unitlruhash.c
112
unit_assert( bin_find_entry(table, &bin, h, k, NULL) == &k->entry );
usr.sbin/unbound/testcode/unitlruhash.c
116
bin_overflow_remove(&bin, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
118
unit_assert( bin_find_entry(table, &bin, h, k, NULL) == NULL );
usr.sbin/unbound/testcode/unitlruhash.c
123
unit_assert( k->entry.hash == k4->entry.hash );
usr.sbin/unbound/testcode/unitlruhash.c
124
k4->entry.overflow_next = &k->entry;
usr.sbin/unbound/testcode/unitlruhash.c
130
unit_assert( bin_find_entry(table, &bin, myhash(13), k, NULL) == NULL );
usr.sbin/unbound/testcode/unitlruhash.c
133
unit_assert( k->entry.hash == k2->entry.hash );
usr.sbin/unbound/testcode/unitlruhash.c
137
unit_assert( bin_find_entry(table, &bin, h, k, NULL) == &k->entry );
usr.sbin/unbound/testcode/unitlruhash.c
149
bin_overflow_remove(&bin, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
151
unit_assert( bin_find_entry(table, &bin, h, k, NULL) == NULL );
usr.sbin/unbound/testcode/unitlruhash.c
154
delkey(k);
usr.sbin/unbound/testcode/unitlruhash.c
164
testkey_type* k = newkey(12);
usr.sbin/unbound/testcode/unitlruhash.c
169
lru_remove(table, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
173
lru_front(table, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
174
unit_assert( table->lru_start == &k->entry &&
usr.sbin/unbound/testcode/unitlruhash.c
175
table->lru_end == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
177
lru_remove(table, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
181
lru_front(table, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
182
unit_assert( table->lru_start == &k->entry &&
usr.sbin/unbound/testcode/unitlruhash.c
183
table->lru_end == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
186
table->lru_end == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
189
unit_assert( table->lru_start == &k->entry &&
usr.sbin/unbound/testcode/unitlruhash.c
190
table->lru_end == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
193
table->lru_end == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
195
lru_remove(table, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
203
delkey(k);
usr.sbin/unbound/testcode/unitlruhash.c
211
testkey_type* k = newkey(12);
usr.sbin/unbound/testcode/unitlruhash.c
216
k->entry.data = d;
usr.sbin/unbound/testcode/unitlruhash.c
219
lruhash_insert(table, myhash(12), &k->entry, d, NULL);
usr.sbin/unbound/testcode/unitlruhash.c
222
unit_assert( lruhash_lookup(table, myhash(12), k, 0) == &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
223
lock_rw_unlock( &k->entry.lock );
usr.sbin/unbound/testcode/unitlruhash.c
226
lruhash_remove(table, myhash(12), k);
usr.sbin/unbound/testcode/unitlruhash.c
53
static void delkey(struct slabhash_testkey* k) {
usr.sbin/unbound/testcode/unitlruhash.c
54
lock_rw_destroy(&k->entry.lock); free(k);}
usr.sbin/unbound/testcode/unitlruhash.c
62
testkey_type* k = (testkey_type*)calloc(1, sizeof(testkey_type));
usr.sbin/unbound/testcode/unitlruhash.c
63
if(!k) fatal_exit("out of memory");
usr.sbin/unbound/testcode/unitlruhash.c
64
k->id = id;
usr.sbin/unbound/testcode/unitlruhash.c
65
k->entry.hash = myhash(id);
usr.sbin/unbound/testcode/unitlruhash.c
66
k->entry.key = k;
usr.sbin/unbound/testcode/unitlruhash.c
67
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/testcode/unitlruhash.c
68
return k;
usr.sbin/unbound/testcode/unitlruhash.c
83
testkey_type* k = newkey(12);
usr.sbin/unbound/testcode/unitlruhash.c
94
bin_overflow_remove(&bin, &k->entry);
usr.sbin/unbound/testcode/unitlruhash.c
97
unit_assert( bin_find_entry(table, &bin, h, k, NULL) == NULL );
usr.sbin/unbound/testcode/unitslabhash.c
100
slabhash_remove(table, myhash(12), k);
usr.sbin/unbound/testcode/unitslabhash.c
52
static void delkey(struct slabhash_testkey* k) {
usr.sbin/unbound/testcode/unitslabhash.c
53
lock_rw_destroy(&k->entry.lock); free(k);}
usr.sbin/unbound/testcode/unitslabhash.c
64
testkey_type* k = (testkey_type*)calloc(1, sizeof(testkey_type));
usr.sbin/unbound/testcode/unitslabhash.c
65
if(!k) fatal_exit("out of memory");
usr.sbin/unbound/testcode/unitslabhash.c
66
k->id = id;
usr.sbin/unbound/testcode/unitslabhash.c
67
k->entry.hash = myhash(id);
usr.sbin/unbound/testcode/unitslabhash.c
68
k->entry.key = k;
usr.sbin/unbound/testcode/unitslabhash.c
69
lock_rw_init(&k->entry.lock);
usr.sbin/unbound/testcode/unitslabhash.c
70
return k;
usr.sbin/unbound/testcode/unitslabhash.c
85
testkey_type* k = newkey(12);
usr.sbin/unbound/testcode/unitslabhash.c
90
k->entry.data = d;
usr.sbin/unbound/testcode/unitslabhash.c
93
slabhash_insert(table, myhash(12), &k->entry, d, NULL);
usr.sbin/unbound/testcode/unitslabhash.c
96
unit_assert( slabhash_lookup(table, myhash(12), k, 0) == &k->entry);
usr.sbin/unbound/testcode/unitslabhash.c
97
lock_rw_unlock( &k->entry.lock );
usr.sbin/unbound/util/data/msgreply.c
718
msgreply_sizefunc(void* k, void* d)
usr.sbin/unbound/util/data/msgreply.c
720
struct msgreply_entry* q = (struct msgreply_entry*)k;
usr.sbin/unbound/util/data/msgreply.c
731
query_entry_delete(void *k, void* ATTR_UNUSED(arg))
usr.sbin/unbound/util/data/msgreply.c
733
struct msgreply_entry* q = (struct msgreply_entry*)k;
usr.sbin/unbound/util/data/msgreply.h
373
size_t msgreply_sizefunc(void* k, void* d);
usr.sbin/unbound/util/data/packed_rrset.c
130
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)key;
usr.sbin/unbound/util/data/packed_rrset.c
132
k->id = 0;
usr.sbin/unbound/util/data/packed_rrset.c
133
free(k->rk.dname);
usr.sbin/unbound/util/data/packed_rrset.c
134
k->rk.dname = NULL;
usr.sbin/unbound/util/data/packed_rrset.c
135
alloc_special_release(a, k);
usr.sbin/unbound/util/data/packed_rrset.c
72
struct ub_packed_rrset_key* k = (struct ub_packed_rrset_key*)key;
usr.sbin/unbound/util/data/packed_rrset.c
74
size_t s = sizeof(struct ub_packed_rrset_key) + k->rk.dname_len;
usr.sbin/unbound/util/data/packed_rrset.c
75
s += packed_rrset_sizeof(d) + lock_get_mem(&k->entry.lock);
usr.sbin/unbound/util/data/packed_rrset.h
285
struct packed_rrset_key* k;
usr.sbin/unbound/util/siphash.c
90
int siphash(const uint8_t *in, const size_t inlen, const uint8_t *k,
usr.sbin/unbound/util/siphash.c
97
uint64_t k0 = U8TO64_LE(k);
usr.sbin/unbound/util/siphash.c
98
uint64_t k1 = U8TO64_LE(k + 8);
usr.sbin/unbound/util/siphash.h
41
int siphash(const uint8_t *in, const size_t inlen, const uint8_t *k,
usr.sbin/unbound/util/storage/lookup3.c
1013
uint32_t c[HASHSTATE], d[HASHSTATE], i=0, j=0, k, l, m=0, z;
usr.sbin/unbound/util/storage/lookup3.c
1032
for (k=0; k<MAXPAIR; k+=2)
usr.sbin/unbound/util/storage/lookup3.c
1038
a[i] ^= (k<<j);
usr.sbin/unbound/util/storage/lookup3.c
1039
a[i] ^= (k>>(8-j));
usr.sbin/unbound/util/storage/lookup3.c
1041
b[i] ^= ((k+1)<<j);
usr.sbin/unbound/util/storage/lookup3.c
1042
b[i] ^= ((k+1)>>(8-j));
usr.sbin/unbound/util/storage/lookup3.c
1057
if (k>z) z=k;
usr.sbin/unbound/util/storage/lookup3.c
1058
if (k==MAXPAIR)
usr.sbin/unbound/util/storage/lookup3.c
118
#define rot(x,k) (((x)<<(k)) | ((x)>>(32-(k))))
usr.sbin/unbound/util/storage/lookup3.c
233
const uint32_t *k, /* the key, an array of uint32_t values */
usr.sbin/unbound/util/storage/lookup3.c
245
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
246
b += k[1];
usr.sbin/unbound/util/storage/lookup3.c
247
c += k[2];
usr.sbin/unbound/util/storage/lookup3.c
250
k += 3;
usr.sbin/unbound/util/storage/lookup3.c
256
case 3 : c+=k[2];
usr.sbin/unbound/util/storage/lookup3.c
259
case 2 : b+=k[1];
usr.sbin/unbound/util/storage/lookup3.c
262
case 1 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
285
const uint32_t *k, /* the key, an array of uint32_t values */
usr.sbin/unbound/util/storage/lookup3.c
299
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
300
b += k[1];
usr.sbin/unbound/util/storage/lookup3.c
301
c += k[2];
usr.sbin/unbound/util/storage/lookup3.c
304
k += 3;
usr.sbin/unbound/util/storage/lookup3.c
310
case 3 : c+=k[2];
usr.sbin/unbound/util/storage/lookup3.c
313
case 2 : b+=k[1];
usr.sbin/unbound/util/storage/lookup3.c
316
case 1 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
366
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/unbound/util/storage/lookup3.c
374
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
375
b += k[1];
usr.sbin/unbound/util/storage/lookup3.c
376
c += k[2];
usr.sbin/unbound/util/storage/lookup3.c
379
k += 3;
usr.sbin/unbound/util/storage/lookup3.c
396
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
397
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
398
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
399
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
400
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
401
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
402
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
403
case 5 : b+=k[1]&0xff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
404
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
405
case 3 : a+=k[0]&0xffffff; break;
usr.sbin/unbound/util/storage/lookup3.c
406
case 2 : a+=k[0]&0xffff; break;
usr.sbin/unbound/util/storage/lookup3.c
407
case 1 : a+=k[0]&0xff; break;
usr.sbin/unbound/util/storage/lookup3.c
413
k8 = (const uint8_t *)k;
usr.sbin/unbound/util/storage/lookup3.c
416
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
426
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
436
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
450
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
usr.sbin/unbound/util/storage/lookup3.c
456
a += k[0] + (((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
457
b += k[2] + (((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
458
c += k[4] + (((uint32_t)k[5])<<16);
usr.sbin/unbound/util/storage/lookup3.c
461
k += 6;
usr.sbin/unbound/util/storage/lookup3.c
465
k8 = (const uint8_t *)k;
usr.sbin/unbound/util/storage/lookup3.c
468
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
usr.sbin/unbound/util/storage/lookup3.c
469
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
470
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
475
case 10: c+=k[4];
usr.sbin/unbound/util/storage/lookup3.c
476
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
477
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
482
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
483
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
488
case 6 : b+=k[2];
usr.sbin/unbound/util/storage/lookup3.c
489
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
494
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
499
case 2 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
507
const uint8_t *k = (const uint8_t *)key;
usr.sbin/unbound/util/storage/lookup3.c
512
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
513
a += ((uint32_t)k[1])<<8;
usr.sbin/unbound/util/storage/lookup3.c
514
a += ((uint32_t)k[2])<<16;
usr.sbin/unbound/util/storage/lookup3.c
515
a += ((uint32_t)k[3])<<24;
usr.sbin/unbound/util/storage/lookup3.c
516
b += k[4];
usr.sbin/unbound/util/storage/lookup3.c
517
b += ((uint32_t)k[5])<<8;
usr.sbin/unbound/util/storage/lookup3.c
518
b += ((uint32_t)k[6])<<16;
usr.sbin/unbound/util/storage/lookup3.c
519
b += ((uint32_t)k[7])<<24;
usr.sbin/unbound/util/storage/lookup3.c
520
c += k[8];
usr.sbin/unbound/util/storage/lookup3.c
521
c += ((uint32_t)k[9])<<8;
usr.sbin/unbound/util/storage/lookup3.c
522
c += ((uint32_t)k[10])<<16;
usr.sbin/unbound/util/storage/lookup3.c
523
c += ((uint32_t)k[11])<<24;
usr.sbin/unbound/util/storage/lookup3.c
526
k += 12;
usr.sbin/unbound/util/storage/lookup3.c
532
case 12: c+=((uint32_t)k[11])<<24;
usr.sbin/unbound/util/storage/lookup3.c
535
case 11: c+=((uint32_t)k[10])<<16;
usr.sbin/unbound/util/storage/lookup3.c
538
case 10: c+=((uint32_t)k[9])<<8;
usr.sbin/unbound/util/storage/lookup3.c
541
case 9 : c+=k[8];
usr.sbin/unbound/util/storage/lookup3.c
544
case 8 : b+=((uint32_t)k[7])<<24;
usr.sbin/unbound/util/storage/lookup3.c
547
case 7 : b+=((uint32_t)k[6])<<16;
usr.sbin/unbound/util/storage/lookup3.c
550
case 6 : b+=((uint32_t)k[5])<<8;
usr.sbin/unbound/util/storage/lookup3.c
553
case 5 : b+=k[4];
usr.sbin/unbound/util/storage/lookup3.c
556
case 4 : a+=((uint32_t)k[3])<<24;
usr.sbin/unbound/util/storage/lookup3.c
559
case 3 : a+=((uint32_t)k[2])<<16;
usr.sbin/unbound/util/storage/lookup3.c
562
case 2 : a+=((uint32_t)k[1])<<8;
usr.sbin/unbound/util/storage/lookup3.c
565
case 1 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
602
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/unbound/util/storage/lookup3.c
610
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
611
b += k[1];
usr.sbin/unbound/util/storage/lookup3.c
612
c += k[2];
usr.sbin/unbound/util/storage/lookup3.c
615
k += 3;
usr.sbin/unbound/util/storage/lookup3.c
632
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
633
case 11: c+=k[2]&0xffffff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
634
case 10: c+=k[2]&0xffff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
635
case 9 : c+=k[2]&0xff; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
636
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
637
case 7 : b+=k[1]&0xffffff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
638
case 6 : b+=k[1]&0xffff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
639
case 5 : b+=k[1]&0xff; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
640
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
641
case 3 : a+=k[0]&0xffffff; break;
usr.sbin/unbound/util/storage/lookup3.c
642
case 2 : a+=k[0]&0xffff; break;
usr.sbin/unbound/util/storage/lookup3.c
643
case 1 : a+=k[0]&0xff; break;
usr.sbin/unbound/util/storage/lookup3.c
649
k8 = (const uint8_t *)k;
usr.sbin/unbound/util/storage/lookup3.c
652
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
662
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
672
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
686
const uint16_t *k = (const uint16_t *)key; /* read 16-bit chunks */
usr.sbin/unbound/util/storage/lookup3.c
692
a += k[0] + (((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
693
b += k[2] + (((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
694
c += k[4] + (((uint32_t)k[5])<<16);
usr.sbin/unbound/util/storage/lookup3.c
697
k += 6;
usr.sbin/unbound/util/storage/lookup3.c
701
k8 = (const uint8_t *)k;
usr.sbin/unbound/util/storage/lookup3.c
704
case 12: c+=k[4]+(((uint32_t)k[5])<<16);
usr.sbin/unbound/util/storage/lookup3.c
705
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
706
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
711
case 10: c+=k[4];
usr.sbin/unbound/util/storage/lookup3.c
712
b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
713
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
718
case 8 : b+=k[2]+(((uint32_t)k[3])<<16);
usr.sbin/unbound/util/storage/lookup3.c
719
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
724
case 6 : b+=k[2];
usr.sbin/unbound/util/storage/lookup3.c
725
a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
730
case 4 : a+=k[0]+(((uint32_t)k[1])<<16);
usr.sbin/unbound/util/storage/lookup3.c
735
case 2 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
743
const uint8_t *k = (const uint8_t *)key;
usr.sbin/unbound/util/storage/lookup3.c
748
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
749
a += ((uint32_t)k[1])<<8;
usr.sbin/unbound/util/storage/lookup3.c
750
a += ((uint32_t)k[2])<<16;
usr.sbin/unbound/util/storage/lookup3.c
751
a += ((uint32_t)k[3])<<24;
usr.sbin/unbound/util/storage/lookup3.c
752
b += k[4];
usr.sbin/unbound/util/storage/lookup3.c
753
b += ((uint32_t)k[5])<<8;
usr.sbin/unbound/util/storage/lookup3.c
754
b += ((uint32_t)k[6])<<16;
usr.sbin/unbound/util/storage/lookup3.c
755
b += ((uint32_t)k[7])<<24;
usr.sbin/unbound/util/storage/lookup3.c
756
c += k[8];
usr.sbin/unbound/util/storage/lookup3.c
757
c += ((uint32_t)k[9])<<8;
usr.sbin/unbound/util/storage/lookup3.c
758
c += ((uint32_t)k[10])<<16;
usr.sbin/unbound/util/storage/lookup3.c
759
c += ((uint32_t)k[11])<<24;
usr.sbin/unbound/util/storage/lookup3.c
762
k += 12;
usr.sbin/unbound/util/storage/lookup3.c
768
case 12: c+=((uint32_t)k[11])<<24;
usr.sbin/unbound/util/storage/lookup3.c
771
case 11: c+=((uint32_t)k[10])<<16;
usr.sbin/unbound/util/storage/lookup3.c
774
case 10: c+=((uint32_t)k[9])<<8;
usr.sbin/unbound/util/storage/lookup3.c
777
case 9 : c+=k[8];
usr.sbin/unbound/util/storage/lookup3.c
780
case 8 : b+=((uint32_t)k[7])<<24;
usr.sbin/unbound/util/storage/lookup3.c
783
case 7 : b+=((uint32_t)k[6])<<16;
usr.sbin/unbound/util/storage/lookup3.c
786
case 6 : b+=((uint32_t)k[5])<<8;
usr.sbin/unbound/util/storage/lookup3.c
789
case 5 : b+=k[4];
usr.sbin/unbound/util/storage/lookup3.c
792
case 4 : a+=((uint32_t)k[3])<<24;
usr.sbin/unbound/util/storage/lookup3.c
795
case 3 : a+=((uint32_t)k[2])<<16;
usr.sbin/unbound/util/storage/lookup3.c
798
case 2 : a+=((uint32_t)k[1])<<8;
usr.sbin/unbound/util/storage/lookup3.c
801
case 1 : a+=k[0];
usr.sbin/unbound/util/storage/lookup3.c
831
const uint32_t *k = (const uint32_t *)key; /* read 32-bit chunks */
usr.sbin/unbound/util/storage/lookup3.c
839
a += k[0];
usr.sbin/unbound/util/storage/lookup3.c
840
b += k[1];
usr.sbin/unbound/util/storage/lookup3.c
841
c += k[2];
usr.sbin/unbound/util/storage/lookup3.c
844
k += 3;
usr.sbin/unbound/util/storage/lookup3.c
861
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
862
case 11: c+=k[2]&0xffffff00; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
863
case 10: c+=k[2]&0xffff0000; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
864
case 9 : c+=k[2]&0xff000000; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
865
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
866
case 7 : b+=k[1]&0xffffff00; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
867
case 6 : b+=k[1]&0xffff0000; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
868
case 5 : b+=k[1]&0xff000000; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
869
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
870
case 3 : a+=k[0]&0xffffff00; break;
usr.sbin/unbound/util/storage/lookup3.c
871
case 2 : a+=k[0]&0xffff0000; break;
usr.sbin/unbound/util/storage/lookup3.c
872
case 1 : a+=k[0]&0xff000000; break;
usr.sbin/unbound/util/storage/lookup3.c
878
k8 = (const uint8_t *)k;
usr.sbin/unbound/util/storage/lookup3.c
881
case 12: c+=k[2]; b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
891
case 8 : b+=k[1]; a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
901
case 4 : a+=k[0]; break;
usr.sbin/unbound/util/storage/lookup3.c
915
const uint8_t *k = (const uint8_t *)key;
usr.sbin/unbound/util/storage/lookup3.c
920
a += ((uint32_t)k[0])<<24;
usr.sbin/unbound/util/storage/lookup3.c
921
a += ((uint32_t)k[1])<<16;
usr.sbin/unbound/util/storage/lookup3.c
922
a += ((uint32_t)k[2])<<8;
usr.sbin/unbound/util/storage/lookup3.c
923
a += ((uint32_t)k[3]);
usr.sbin/unbound/util/storage/lookup3.c
924
b += ((uint32_t)k[4])<<24;
usr.sbin/unbound/util/storage/lookup3.c
925
b += ((uint32_t)k[5])<<16;
usr.sbin/unbound/util/storage/lookup3.c
926
b += ((uint32_t)k[6])<<8;
usr.sbin/unbound/util/storage/lookup3.c
927
b += ((uint32_t)k[7]);
usr.sbin/unbound/util/storage/lookup3.c
928
c += ((uint32_t)k[8])<<24;
usr.sbin/unbound/util/storage/lookup3.c
929
c += ((uint32_t)k[9])<<16;
usr.sbin/unbound/util/storage/lookup3.c
930
c += ((uint32_t)k[10])<<8;
usr.sbin/unbound/util/storage/lookup3.c
931
c += ((uint32_t)k[11]);
usr.sbin/unbound/util/storage/lookup3.c
934
k += 12;
usr.sbin/unbound/util/storage/lookup3.c
940
case 12: c+=k[11];
usr.sbin/unbound/util/storage/lookup3.c
943
case 11: c+=((uint32_t)k[10])<<8;
usr.sbin/unbound/util/storage/lookup3.c
946
case 10: c+=((uint32_t)k[9])<<16;
usr.sbin/unbound/util/storage/lookup3.c
949
case 9 : c+=((uint32_t)k[8])<<24;
usr.sbin/unbound/util/storage/lookup3.c
952
case 8 : b+=k[7];
usr.sbin/unbound/util/storage/lookup3.c
955
case 7 : b+=((uint32_t)k[6])<<8;
usr.sbin/unbound/util/storage/lookup3.c
958
case 6 : b+=((uint32_t)k[5])<<16;
usr.sbin/unbound/util/storage/lookup3.c
961
case 5 : b+=((uint32_t)k[4])<<24;
usr.sbin/unbound/util/storage/lookup3.c
964
case 4 : a+=k[3];
usr.sbin/unbound/util/storage/lookup3.c
967
case 3 : a+=((uint32_t)k[2])<<8;
usr.sbin/unbound/util/storage/lookup3.c
970
case 2 : a+=((uint32_t)k[1])<<16;
usr.sbin/unbound/util/storage/lookup3.c
973
case 1 : a+=((uint32_t)k[0])<<24;
usr.sbin/unbound/util/storage/lookup3.h
53
uint32_t hashword(const uint32_t *k, size_t length, uint32_t initval);
usr.sbin/unbound/util/storage/lookup3.h
62
uint32_t hashlittle(const void *k, size_t length, uint32_t initval);
usr.sbin/unbound/util/storage/slabhash.c
193
static void delkey(struct slabhash_testkey* k) {
usr.sbin/unbound/util/storage/slabhash.c
194
lock_rw_destroy(&k->entry.lock); free(k);}
usr.sbin/unbound/validator/autotrust.c
1472
key_ttl(struct ub_packed_rrset_key* k)
usr.sbin/unbound/validator/autotrust.c
1474
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/autotrust.c
635
struct ub_packed_rrset_key* k;
usr.sbin/unbound/validator/autotrust.c
638
k = (struct ub_packed_rrset_key*)calloc(1, sizeof(*k));
usr.sbin/unbound/validator/autotrust.c
639
if(!k)
usr.sbin/unbound/validator/autotrust.c
641
k->rk.type = htons(sldns_wirerr_get_type(rr, rr_len, dname_len));
usr.sbin/unbound/validator/autotrust.c
642
k->rk.rrset_class = htons(sldns_wirerr_get_class(rr, rr_len, dname_len));
usr.sbin/unbound/validator/autotrust.c
643
k->rk.dname_len = dname_len;
usr.sbin/unbound/validator/autotrust.c
644
k->rk.dname = memdup(rr, dname_len);
usr.sbin/unbound/validator/autotrust.c
645
if(!k->rk.dname) {
usr.sbin/unbound/validator/autotrust.c
646
free(k);
usr.sbin/unbound/validator/autotrust.c
649
return k;
usr.sbin/unbound/validator/val_anchor.c
1197
struct ta_key *k;
usr.sbin/unbound/validator/val_anchor.c
1206
for(k = ta->keylist; k; k = k->next) {
usr.sbin/unbound/validator/val_anchor.c
1207
s += sizeof(*k) + k->len;
usr.sbin/unbound/validator/val_anchor.c
263
struct ta_key* k;
usr.sbin/unbound/validator/val_anchor.c
264
for(k = ta->keylist; k; k = k->next) {
usr.sbin/unbound/validator/val_anchor.c
265
if(k->type == type && k->len == rdata_len &&
usr.sbin/unbound/validator/val_anchor.c
266
memcmp(k->data, rdata, rdata_len) == 0)
usr.sbin/unbound/validator/val_anchor.c
267
return k;
usr.sbin/unbound/validator/val_anchor.c
276
struct ta_key* k = (struct ta_key*)malloc(sizeof(*k));
usr.sbin/unbound/validator/val_anchor.c
277
if(!k)
usr.sbin/unbound/validator/val_anchor.c
279
memset(k, 0, sizeof(*k));
usr.sbin/unbound/validator/val_anchor.c
280
k->data = memdup(rdata, rdata_len);
usr.sbin/unbound/validator/val_anchor.c
281
if(!k->data) {
usr.sbin/unbound/validator/val_anchor.c
282
free(k);
usr.sbin/unbound/validator/val_anchor.c
285
k->len = rdata_len;
usr.sbin/unbound/validator/val_anchor.c
286
k->type = type;
usr.sbin/unbound/validator/val_anchor.c
287
return k;
usr.sbin/unbound/validator/val_anchor.c
307
struct ta_key* k;
usr.sbin/unbound/validator/val_anchor.c
333
k = anchor_new_ta_key(rdata, rdata_len, type);
usr.sbin/unbound/validator/val_anchor.c
334
if(!k) {
usr.sbin/unbound/validator/val_anchor.c
342
k->next = ta->keylist;
usr.sbin/unbound/validator/val_anchor.c
343
ta->keylist = k;
usr.sbin/unbound/validator/val_kcache.c
128
struct key_entry_key* k = key_cache_search(kcache, name,
usr.sbin/unbound/validator/val_kcache.c
130
if(k) {
usr.sbin/unbound/validator/val_kcache.c
133
k->entry.data;
usr.sbin/unbound/validator/val_kcache.c
137
key_entry_copy_toregion(k, region);
usr.sbin/unbound/validator/val_kcache.c
138
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/validator/val_kcache.c
141
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/validator/val_kcache.c
86
struct key_entry_key* k = key_entry_copy(kkey, copy_reason);
usr.sbin/unbound/validator/val_kcache.c
87
if(!k)
usr.sbin/unbound/validator/val_kcache.c
89
key_entry_hash(k);
usr.sbin/unbound/validator/val_kcache.c
90
slabhash_insert(kcache->slab, k->entry.hash, &k->entry,
usr.sbin/unbound/validator/val_kcache.c
91
k->entry.data, NULL);
usr.sbin/unbound/validator/val_kentry.c
261
struct key_entry_key** k, struct key_entry_data** d)
usr.sbin/unbound/validator/val_kentry.c
263
*k = regional_alloc(region, sizeof(**k));
usr.sbin/unbound/validator/val_kentry.c
264
if(!*k)
usr.sbin/unbound/validator/val_kentry.c
266
memset(*k, 0, sizeof(**k));
usr.sbin/unbound/validator/val_kentry.c
267
(*k)->entry.key = *k;
usr.sbin/unbound/validator/val_kentry.c
268
(*k)->name = regional_alloc_init(region, name, namelen);
usr.sbin/unbound/validator/val_kentry.c
269
if(!(*k)->name)
usr.sbin/unbound/validator/val_kentry.c
271
(*k)->namelen = namelen;
usr.sbin/unbound/validator/val_kentry.c
272
(*k)->key_class = dclass;
usr.sbin/unbound/validator/val_kentry.c
276
(*k)->entry.data = *d;
usr.sbin/unbound/validator/val_kentry.c
286
struct key_entry_key* k;
usr.sbin/unbound/validator/val_kentry.c
288
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
usr.sbin/unbound/validator/val_kentry.c
299
return k;
usr.sbin/unbound/validator/val_kentry.c
309
struct key_entry_key* k;
usr.sbin/unbound/validator/val_kentry.c
313
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
usr.sbin/unbound/validator/val_kentry.c
332
return k;
usr.sbin/unbound/validator/val_kentry.c
341
struct key_entry_key* k;
usr.sbin/unbound/validator/val_kentry.c
343
if(!key_entry_setup(region, name, namelen, dclass, &k, &d))
usr.sbin/unbound/validator/val_kentry.c
354
return k;
usr.sbin/unbound/validator/val_neg.c
1044
static int nsec3_no_type(struct ub_packed_rrset_key* k, uint16_t t)
usr.sbin/unbound/validator/val_neg.c
1046
int count = (int)((struct packed_rrset_data*)k->entry.data)->count;
usr.sbin/unbound/validator/val_neg.c
1049
if(nsec3_has_type(k, i, t))
usr.sbin/unbound/validator/val_neg.c
1076
struct ub_packed_rrset_key* r, *k = rrset_cache_lookup(rrset_cache,
usr.sbin/unbound/validator/val_neg.c
1079
if(!k) return NULL;
usr.sbin/unbound/validator/val_neg.c
1080
d = k->entry.data;
usr.sbin/unbound/validator/val_neg.c
1085
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/validator/val_neg.c
1090
(qtype == LDNS_RR_TYPE_NSEC && nsec_has_type(k, checktype)) ||
usr.sbin/unbound/validator/val_neg.c
1091
(qtype == LDNS_RR_TYPE_NSEC3 && !nsec3_no_type(k, checktype))
usr.sbin/unbound/validator/val_neg.c
1093
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/validator/val_neg.c
1097
r = packed_rrset_copy_region(k, region, now);
usr.sbin/unbound/validator/val_neg.c
1099
lock_rw_unlock(&k->entry.lock);
usr.sbin/unbound/validator/val_nsec.c
54
rrset_get_ttl(struct ub_packed_rrset_key* k)
usr.sbin/unbound/validator/val_nsec.c
56
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
100
rrset_get_sigcount(struct ub_packed_rrset_key* k)
usr.sbin/unbound/validator/val_sigcrypt.c
102
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
1056
insert_can_owner(sldns_buffer* buf, struct ub_packed_rrset_key* k,
usr.sbin/unbound/validator/val_sigcrypt.c
1060
int fqdn_labels = dname_signame_label_count(k->rk.dname);
usr.sbin/unbound/validator/val_sigcrypt.c
1064
sldns_buffer_write(buf, k->rk.dname, k->rk.dname_len);
usr.sbin/unbound/validator/val_sigcrypt.c
1066
*can_owner_len = k->rk.dname_len;
usr.sbin/unbound/validator/val_sigcrypt.c
1073
uint8_t* nm = k->rk.dname;
usr.sbin/unbound/validator/val_sigcrypt.c
1074
size_t len = k->rk.dname_len;
usr.sbin/unbound/validator/val_sigcrypt.c
113
rrset_get_sig_keytag(struct ub_packed_rrset_key* k, size_t sig_idx)
usr.sbin/unbound/validator/val_sigcrypt.c
116
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
1271
struct ub_packed_rrset_key* k, uint8_t* sig, size_t siglen,
usr.sbin/unbound/validator/val_sigcrypt.c
1275
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
1294
canonical_sort(k, d, *sortree, rrs);
usr.sbin/unbound/validator/val_sigcrypt.c
131
rrset_get_sig_algo(struct ub_packed_rrset_key* k, size_t sig_idx)
usr.sbin/unbound/validator/val_sigcrypt.c
1312
else insert_can_owner(buf, k, sig, &can_owner,
usr.sbin/unbound/validator/val_sigcrypt.c
1314
sldns_buffer_write(buf, &k->rk.type, 2);
usr.sbin/unbound/validator/val_sigcrypt.c
1315
sldns_buffer_write(buf, &k->rk.rrset_class, 2);
usr.sbin/unbound/validator/val_sigcrypt.c
1319
canonicalize_rdata(buf, k, d->rr_len[walk->rr_idx]);
usr.sbin/unbound/validator/val_sigcrypt.c
1326
if(ntohs(k->rk.type) == LDNS_RR_TYPE_NSEC &&
usr.sbin/unbound/validator/val_sigcrypt.c
1328
k->rk.dname = regional_alloc_init(qstate->region, can_owner,
usr.sbin/unbound/validator/val_sigcrypt.c
133
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
1330
if(!k->rk.dname)
usr.sbin/unbound/validator/val_sigcrypt.c
1332
k->rk.dname_len = can_owner_len;
usr.sbin/unbound/validator/val_sigcrypt.c
1341
struct ub_packed_rrset_key* k)
usr.sbin/unbound/validator/val_sigcrypt.c
1344
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
1361
canonical_sort(k, d, sortree, rrs);
usr.sbin/unbound/validator/val_sigcrypt.c
1377
sldns_buffer_write(buf, k->rk.dname, k->rk.dname_len);
usr.sbin/unbound/validator/val_sigcrypt.c
1379
can_owner_len = k->rk.dname_len;
usr.sbin/unbound/validator/val_sigcrypt.c
1381
sldns_buffer_write(buf, &k->rk.type, 2);
usr.sbin/unbound/validator/val_sigcrypt.c
1382
sldns_buffer_write(buf, &k->rk.rrset_class, 2);
usr.sbin/unbound/validator/val_sigcrypt.c
1386
canonicalize_rdata(buf, k, d->rr_len[walk->rr_idx]);
usr.sbin/unbound/validator/val_sigcrypt.c
142
rrset_get_rdata(struct ub_packed_rrset_key* k, size_t idx, uint8_t** rdata,
usr.sbin/unbound/validator/val_sigcrypt.c
145
struct packed_rrset_data* d = (struct packed_rrset_data*)k->entry.data;
usr.sbin/unbound/validator/val_sigcrypt.c
152
dnskey_get_flags(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
157
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
172
dnskey_get_protocol(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
176
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
183
dnskey_get_algo(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
187
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
195
dnskey_get_pubkey(struct ub_packed_rrset_key* k, size_t idx,
usr.sbin/unbound/validator/val_sigcrypt.c
200
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
211
ds_get_key_algo(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
215
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
222
ds_get_digest_algo(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
226
rrset_get_rdata(k, idx, &rdata, &len);
usr.sbin/unbound/validator/val_sigcrypt.c
255
ds_get_sigdata(struct ub_packed_rrset_key* k, size_t idx, uint8_t** digest,
usr.sbin/unbound/validator/val_sigcrypt.c
260
rrset_get_rdata(k, idx, &rdata, &rdlen);
usr.sbin/unbound/validator/val_sigcrypt.c
277
ds_digest_size_algo(struct ub_packed_rrset_key* k, size_t idx)
usr.sbin/unbound/validator/val_sigcrypt.c
279
return ds_digest_size_supported(ds_get_digest_algo(k, idx));
usr.sbin/unbound/validator/val_sigcrypt.h
235
int ds_get_key_algo(struct ub_packed_rrset_key* k, size_t idx);
usr.sbin/unbound/validator/val_sigcrypt.h
243
int dnskey_get_algo(struct ub_packed_rrset_key* k, size_t idx);
usr.sbin/unbound/validator/val_sigcrypt.h
251
uint16_t dnskey_get_flags(struct ub_packed_rrset_key* k, size_t idx);
usr.sbin/unbound/validator/val_sigcrypt.h
354
struct sldns_buffer* buf, struct ub_packed_rrset_key* k);
usr.sbin/unwindctl/unwindctl.c
221
k = i + j * column_offset;
usr.sbin/unwindctl/unwindctl.c
222
if (k >= info_cnt)
usr.sbin/unwindctl/unwindctl.c
225
cri = &info[k];
usr.sbin/unwindctl/unwindctl.c
226
printf("%d. %-15s %10s, ", k + 1,
usr.sbin/unwindctl/unwindctl.c
95
int i, j, k, n, verbose = 0;
usr.sbin/vmd/parse.y
814
kw_cmp(const void *k, const void *e)
usr.sbin/vmd/parse.y
816
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ypldap/ldapclient.c
425
size_t k;
usr.sbin/ypldap/ldapclient.c
448
for (k = 0; k >= 0 && ldap_attrs && k < ldap_attrs->len; k++) {
usr.sbin/ypldap/ldapclient.c
451
ldap_attrs->str[k].ostr_val,
usr.sbin/ypldap/ldapclient.c
454
if (k + 1 < ldap_attrs->len)
usr.sbin/ypldap/parse.y
517
kw_cmp(const void *k, const void *e)
usr.sbin/ypldap/parse.y
519
return (strcmp(k, ((const struct keywords *)e)->k_name));
usr.sbin/ypserv/makedbm/makedbm.c
166
char *p, *k, *v, *slash;
usr.sbin/ypserv/makedbm/makedbm.c
233
k = p; /* save start of key */
usr.sbin/ypserv/makedbm/makedbm.c
248
add_record(new_db, k, v, TRUE); /* save record */
usr.sbin/ypserv/mknetid/mknetid.c
170
char line[1024], *p, *k, *u, *g;
usr.sbin/ypserv/mknetid/mknetid.c
194
k = p; colon = 0;
usr.sbin/ypserv/mknetid/mknetid.c
195
while (*k != '\0') {
usr.sbin/ypserv/mknetid/mknetid.c
196
if (*k == ':')
usr.sbin/ypserv/mknetid/mknetid.c
198
k++;
usr.sbin/ypserv/mknetid/mknetid.c
202
k = p; /* save start of key */
usr.sbin/ypserv/mknetid/mknetid.c
207
if (strlen(k) == 1) {
usr.sbin/ypserv/mknetid/mknetid.c
208
if (*k == '+')
usr.sbin/ypserv/mknetid/mknetid.c
236
add_user(k, u, g);
usr.sbin/ypserv/mknetid/mknetid.c
257
char line[2048], *p, *k, *u, *g;
usr.sbin/ypserv/mknetid/mknetid.c
281
k = p; colon = 0;
usr.sbin/ypserv/mknetid/mknetid.c
282
while (*k != '\0') {
usr.sbin/ypserv/mknetid/mknetid.c
283
if (*k == ':')
usr.sbin/ypserv/mknetid/mknetid.c
285
k++;
usr.sbin/ypserv/mknetid/mknetid.c
289
k = p; /* save start of key */
usr.sbin/ypserv/mknetid/mknetid.c
294
if (strlen(k) == 1) {
usr.sbin/ypserv/mknetid/mknetid.c
295
if (*k == '+')
usr.sbin/ypserv/mknetid/mknetid.c
423
char line[1024], *p, *k, *u;
usr.sbin/ypserv/mknetid/mknetid.c
447
k = p; /* save start of key */
usr.sbin/ypserv/mknetid/mknetid.c
467
printf("%s %s\n", k, u);
usr.sbin/ypserv/ypserv/acl.c
136
char data_line[1024], *p, *k;
usr.sbin/ypserv/ypserv/acl.c
160
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
171
if (strcmp(k, "allow") == 0) {
usr.sbin/ypserv/ypserv/acl.c
176
if (strcmp(k, "deny") == 0) {
usr.sbin/ypserv/ypserv/acl.c
189
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
200
if (strcmp(k, "all") == 0)
usr.sbin/ypserv/ypserv/acl.c
203
if (strcmp(k, "host") == 0)
usr.sbin/ypserv/ypserv/acl.c
206
if (strcmp(k, "net") == 0)
usr.sbin/ypserv/ypserv/acl.c
230
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
242
if (*k >= '0' && *k <= '9') {
usr.sbin/ypserv/ypserv/acl.c
243
(void)inet_aton(k, &addr);
usr.sbin/ypserv/ypserv/acl.c
247
host = gethostbyname(k);
usr.sbin/ypserv/ypserv/acl.c
261
if (*k >= '0' && *k <= '9') {
usr.sbin/ypserv/ypserv/acl.c
262
(void)inet_aton(k, &addr);
usr.sbin/ypserv/ypserv/acl.c
294
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
305
if (strcmp(k, "netmask") == 0)
usr.sbin/ypserv/ypserv/acl.c
317
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
330
if (*k >= '0' && *k <= '9') {
usr.sbin/ypserv/ypserv/acl.c
331
(void)inet_aton(k, &mask);
usr.sbin/ypserv/ypserv/acl.c
387
state, k);
usr.sbin/ypserv/ypserv/acl.c
408
char data_line[1024], *p, *k;
usr.sbin/ypserv/ypserv/acl.c
435
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
452
if (*k >= '0' && *k <= '9') {
usr.sbin/ypserv/ypserv/acl.c
453
(void)inet_aton(k, &mask);
usr.sbin/ypserv/ypserv/acl.c
458
k = p; /* save start of verb */
usr.sbin/ypserv/ypserv/acl.c
474
if (*k >= '0' && *k <= '9') {
usr.sbin/ypserv/ypserv/acl.c
475
(void)inet_aton(k, &addr);
usr.sbin/ypserv/ypserv/acl.c
507
state, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
204
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
333
k.dptr = domain_key;
usr.sbin/ypserv/ypserv/ypserv_db.c
334
k.dsize = YP_INTERDOMAIN_LEN;
usr.sbin/ypserv/ypserv/ypserv_db.c
335
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
342
k.dptr = secure_key;
usr.sbin/ypserv/ypserv/ypserv_db.c
343
k.dsize = YP_SECURE_LEN;
usr.sbin/ypserv/ypserv/ypserv_db.c
344
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
447
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
459
k.dptr = key.keydat_val;
usr.sbin/ypserv/ypserv/ypserv_db.c
460
k.dsize = key.keydat_len;
usr.sbin/ypserv/ypserv/ypserv_db.c
462
if (yp_private(k, ypprivate)) {
usr.sbin/ypserv/ypserv/ypserv_db.c
467
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
494
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
501
k = ypdb_firstkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
503
while (yp_private(k, ypprivate))
usr.sbin/ypserv/ypserv/ypserv_db.c
504
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
506
if (k.dptr == NULL) {
usr.sbin/ypserv/ypserv/ypserv_db.c
509
res.key.keydat_val = k.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
510
res.key.keydat_len = k.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
511
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
529
datum k, v, n;
usr.sbin/ypserv/ypserv/ypserv_db.c
539
k.dptr = NULL;
usr.sbin/ypserv/ypserv/ypserv_db.c
540
k.dsize = 0;
usr.sbin/ypserv/ypserv/ypserv_db.c
545
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
547
k.dptr = NULL;
usr.sbin/ypserv/ypserv/ypserv_db.c
549
if (k.dptr != NULL) {
usr.sbin/ypserv/ypserv/ypserv_db.c
550
while (yp_private(k, ypprivate))
usr.sbin/ypserv/ypserv/ypserv_db.c
551
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
554
if (k.dptr == NULL) {
usr.sbin/ypserv/ypserv/ypserv_db.c
557
res.key.keydat_val = k.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
558
res.key.keydat_len = k.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
559
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
579
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
585
k.dptr = order_key;
usr.sbin/ypserv/ypserv/ypserv_db.c
586
k.dsize = YP_LAST_LEN;
usr.sbin/ypserv/ypserv/ypserv_db.c
588
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
608
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
614
k.dptr = master_key;
usr.sbin/ypserv/ypserv/ypserv_db.c
615
k.dsize = YP_MASTER_LEN;
usr.sbin/ypserv/ypserv/ypserv_db.c
617
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
635
datum k, v;
usr.sbin/ypserv/ypserv/ypserv_db.c
646
k = ypdb_firstkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
647
while (yp_private(k, FALSE))
usr.sbin/ypserv/ypserv/ypserv_db.c
648
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
651
if (k.dptr == NULL)
usr.sbin/ypserv/ypserv/ypserv_db.c
654
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypserv/ypserv_db.c
660
resp.ypresp_all_u.val.key.keydat_val = k.dptr;
usr.sbin/ypserv/ypserv/ypserv_db.c
661
resp.ypresp_all_u.val.key.keydat_len = k.dsize;
usr.sbin/ypserv/ypserv/ypserv_db.c
673
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypserv/ypserv_db.c
674
while (yp_private(k, FALSE))
usr.sbin/ypserv/ypserv/ypserv_db.c
675
k = ypdb_nextkey(db);
usr.sbin/ypserv/ypxfr/ypxfr.c
114
k.dptr = (char *)&order_key;
usr.sbin/ypserv/ypxfr/ypxfr.c
115
k.dsize = YP_LAST_LEN;
usr.sbin/ypserv/ypxfr/ypxfr.c
117
v = ypdb_fetch(db, k);
usr.sbin/ypserv/ypxfr/ypxfr.c
239
datum k, v;
usr.sbin/ypserv/ypxfr/ypxfr.c
243
k.dptr = keystr;
usr.sbin/ypserv/ypxfr/ypxfr.c
244
k.dsize = strlen(keystr);
usr.sbin/ypserv/ypxfr/ypxfr.c
247
k.dptr, k.dsize, &value, &vallen);
usr.sbin/ypserv/ypxfr/ypxfr.c
253
status = ypdb_store(db, k, v, YPDB_INSERT);
usr.sbin/ypserv/ypxfr/ypxfr.c
268
datum k, v;
usr.sbin/ypserv/ypxfr/ypxfr.c
272
k.dptr = keystr;
usr.sbin/ypserv/ypxfr/ypxfr.c
273
k.dsize = strlen(keystr);
usr.sbin/ypserv/ypxfr/ypxfr.c
276
k.dptr, k.dsize, &value, &vallen);
usr.sbin/ypserv/ypxfr/ypxfr.c
282
status = ypdb_store(db, k, v, YPDB_INSERT);
usr.sbin/ypserv/ypxfr/ypxfr.c
83
datum k, v;
usr.sbin/zic/zic.c
2096
int k;
usr.sbin/zic/zic.c
2118
k = -1;
usr.sbin/zic/zic.c
2133
if (k < 0 || jtime < ktime) {
usr.sbin/zic/zic.c
2134
k = j;
usr.sbin/zic/zic.c
2138
if (k < 0)
usr.sbin/zic/zic.c
2140
rp = &zp->z_rules[k];
