irq_type
unsigned int irq_type)
ring->fence_drv.irq_type = irq_type;
ring->fence_drv.irq_type);
ring->fence_drv.irq_type);
unsigned int irq_type, unsigned int hw_prio,
r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
unsigned irq_type;
unsigned irq_type);
unsigned int irq_type, unsigned int hw_prio,
unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
if (amdgpu_irq_enabled(adev, source, irq_type)) {
unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
if (amdgpu_irq_enabled(adev, source, irq_type)) {
unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
if (amdgpu_irq_enabled(adev, source, irq_type)) {
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
irq_type);
irq_type);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
irq_type);
irq_type);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + p;
irq_type);
irq_type);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
irq_type);
irq_type);
unsigned int irq_type;
irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned irq_type;
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
&adev->gfx.eop_irq, irq_type,
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
&adev->gfx.eop_irq, irq_type,
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
unsigned irq_type;
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
unsigned int irq_type;
irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
irq_type);
irq_type);
unsigned int irq_type;
irq_type = AMDGPU_SDMA_IRQ_INSTANCE0 + i;
irq_type);
irq_type);
int irq_type = amdgpu_display_crtc_idx_to_irq_type(
if (amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type))
if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type))
if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type))
if (amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type))
int irq_type =
amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
int irq_type;
irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
const enum irq_type dal_irq_type,
int irq_type;
irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1;
if (irq_type < adev->mode_info.num_hpd) {
if (amdgpu_irq_get(adev, &adev->hpd_irq, irq_type))
int irq_type;
irq_type = dc_link->irq_source_hpd - DC_IRQ_SOURCE_HPD1;
if (irq_type < adev->mode_info.num_hpd) {
if (amdgpu_irq_put(adev, &adev->hpd_irq, irq_type))
enum irq_type sc_irq_type;