intel_uncore_read_fw
val = intel_uncore_read_fw(__to_uncore(display), reg);
intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
err = wait_for(intel_uncore_read_fw(gt->uncore,
return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
upper = intel_uncore_read_fw(uncore, reg);
lower = intel_uncore_read_fw(uncore, reg);
upper = intel_uncore_read_fw(uncore, reg);
time_hw = intel_uncore_read_fw(uncore, reg);
if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
if (!(intel_uncore_read_fw(uncore,
lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
ack = intel_uncore_read_fw(uncore, reg);
intel_uncore_read_fw(uncore, reg));
freq = take_fw ? intel_uncore_read(uncore, r) : intel_uncore_read_fw(uncore, r);
intel_uncore_read_fw(uncore, wa->reg);
intel_uncore_read_fw(uncore, wa->reg);
intel_uncore_read_fw(uncore, wa->reg);
intel_uncore_read_fw(uncore, wa->reg),
intel_uncore_read_fw(gt->uncore, GEN6_RC_STATE),
intel_uncore_read_fw(gt->uncore, GEN6_RC_CONTROL),
if (wait_for(intel_uncore_read_fw(gt->uncore,
cycles_[i] = -intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI);
cycles_[i] += intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI);
dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0));
dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc;
intel_uncore_read_fw(uncore, DMA_CTRL));
intel_uncore_read_fw(uncore, offset);
intel_uncore_read_fw(uncore, offset);
if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50))
intel_uncore_read_fw(uncore, mmio->reg);
intel_uncore_read_fw(uncore, mmio->reg);
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
#define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
old = intel_uncore_read_fw(uncore, reg);
upper = intel_uncore_read_fw(uncore, upper_reg);
lower = intel_uncore_read_fw(uncore, lower_reg);
upper = intel_uncore_read_fw(uncore, upper_reg);
edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);