sys/dev/pci/drm/i915/display/g4x_dp.c

442

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_dp.c

457

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

404

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/g4x_hdmi.c

423

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

255

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_crt.c

284

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_crt.c

296

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_crt.c

341

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);

sys/dev/pci/drm/i915/display/intel_display.c

1540

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1589

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

1768

intel_set_pch_fifo_underrun_reporting(display, pipe, false);

sys/dev/pci/drm/i915/display/intel_display.c

1787

intel_set_pch_fifo_underrun_reporting(display, pipe, true);

sys/dev/pci/drm/i915/display/intel_display.c

6580

intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);

sys/dev/pci/drm/i915/display/intel_fifo_underrun.c

399

if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,

sys/dev/pci/drm/i915/display/intel_fifo_underrun.h

19

bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,

sys/dev/pci/drm/i915/display/intel_sdvo.c

1865

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);

sys/dev/pci/drm/i915/display/intel_sdvo.c

1876

intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);