sys/dev/pci/drm/i915/gt/uc/intel_guc.c

270

offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;

sys/dev/pci/drm/i915/gt/uc/intel_guc.c

286

u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

1065

return intel_guc_ggtt_offset(guc, guc->ads_vma) +

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

485

addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

564

addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

648

addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

730

ads_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

884

addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;

sys/dev/pci/drm/i915/gt/uc/intel_guc_ads.c

930

base = intel_guc_ggtt_offset(guc, guc->ads_vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

283

CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size);

sys/dev/pci/drm/i915/gt/uc/intel_guc_ct.c

343

base = intel_guc_ggtt_offset(guc, ct->vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_fw.c

84

intel_guc_ggtt_offset(guc, guc_fw->rsa_data));

sys/dev/pci/drm/i915/gt/uc/intel_guc_hwconfig.c

87

ggtt_offset = intel_guc_ggtt_offset(guc, vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

195

u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_slpc.c

350

u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);

sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c

2569

u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool_v69) +

sys/dev/pci/drm/i915/gt/uc/intel_huc.c

565

ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));