integrated_info
kfree(bp->base.integrated_info);
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
static struct integrated_info *bios_parser_create_integrated_info(
struct integrated_info *info;
info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
if (bp->base.integrated_info) {
DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
bp->base.integrated_info->gpuclk_ss_percentage;
bp->base.integrated_info->gpuclk_ss_type;
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
struct integrated_info *info)
static struct integrated_info *bios_parser_create_integrated_info(
struct integrated_info *info;
info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
kfree(bp->base.integrated_info);
if (bp->integrated_info)
clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (bp->integrated_info)
if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
if (bp->integrated_info)
clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
ctx->dc_bios->integrated_info) {
rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
if (ctx->dc_bios->integrated_info) {
ctx->dc_bios->integrated_info,
struct integrated_info *bios_info,
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
ctx->dc_bios->integrated_info,
struct integrated_info *integrated_info;
struct integrated_info info = { { { 0 } } };
if (bp->integrated_info)
info = *bp->integrated_info;
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
struct integrated_info *integrated_info =
pipe_ctx->stream->ctx->dc_bios->integrated_info;
if (integrated_info == NULL)
if (integrated_info->gpu_cap_info & 0x20) {
settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
integrated_info->dp0_ext_hdmi_reg_settings,
sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
integrated_info->dp0_ext_hdmi_6g_reg_settings,
sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
integrated_info->dp1_ext_hdmi_reg_settings,
sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
integrated_info->dp1_ext_hdmi_6g_reg_settings,
sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
integrated_info->dp2_ext_hdmi_reg_settings,
sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
integrated_info->dp2_ext_hdmi_6g_reg_settings,
sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
integrated_info->dp3_ext_hdmi_reg_settings,
sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
integrated_info->dp3_ext_hdmi_6g_reg_settings,
sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
if (bios->integrated_info) {
&bios->integrated_info->ext_disp_conn_info.path[i];
(bios->integrated_info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
((bios->integrated_info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
if (link->ctx->dc_bios->integrated_info)
link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;