intel_dkl_phy_write
intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);