intel_dkl_phy_rmw
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,