intel_dkl_phy_read
if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
ret = poll_timeout_us(val = intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)),
intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));