intel_de_read_fw
dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));
reg = intel_de_read_fw(display, DSPSURF(display, i9xx_plane));
reg = intel_de_read_fw(display, DSPADDR(display, i9xx_plane));
dsparb = intel_de_read_fw(display, DSPARB(display));
dsparb2 = intel_de_read_fw(display, DSPARB2);
dsparb = intel_de_read_fw(display, DSPARB(display));
dsparb2 = intel_de_read_fw(display, DSPARB2);
dsparb3 = intel_de_read_fw(display, DSPARB3);
dsparb2 = intel_de_read_fw(display, DSPARB2);
intel_de_read_fw(display, DSPARB(display));
intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));
u32 val = intel_de_read_fw(display,
ldw = intel_de_read_fw(display,
udw = intel_de_read_fw(display,
u32 ldw = intel_de_read_fw(display,
u32 udw = intel_de_read_fw(display,
lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));
lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));
lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));
u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));
u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));
u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));
u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));
u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));
u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));
val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));
u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));
tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));
return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset,
intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset);
tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id));
intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));
intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));
ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
val = intel_de_read_fw(display, GMBUS3(display));
*val = intel_de_read_fw(display, SBI_DATA);
scan_prev_time = intel_de_read_fw(display,
scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
scan_post_time = intel_de_read_fw(display,
position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
temp = intel_de_read_fw(display,
position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;