intel_de_posting_read
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, DP_A);
intel_de_posting_read(display, DP_A);
intel_de_posting_read(display, DP_A);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, intel_hdmi->hdmi_reg);
intel_de_posting_read(display, IPS_CTL);
intel_de_posting_read(display, FW_BLC_SELF_VLV);
intel_de_posting_read(display, FW_BLC_SELF);
intel_de_posting_read(display, DSPFW3(display));
intel_de_posting_read(display, FW_BLC_SELF);
intel_de_posting_read(display, INSTPM);
intel_de_posting_read(display, DSPFW1(display));
intel_de_posting_read(display, DSPFW1(display));
intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
intel_de_posting_read(display, BLC_PWM_PCH_CTL1);
intel_de_posting_read(display, BLC_PWM_CPU_CTL2);
intel_de_posting_read(display, BLC_PWM_PCH_CTL1);
intel_de_posting_read(display, BLC_PWM_CTL);
intel_de_posting_read(display, BLC_PWM_CTL2);
intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe));
intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller));
intel_de_posting_read(display, DPLL_CTRL1);
intel_de_posting_read(display, CDCLK_CTL);
intel_de_posting_read(display, CDCLK_CTL);
intel_de_posting_read(display, crt->adpa_reg);
intel_de_posting_read(display,
intel_de_posting_read(display, crt->adpa_reg);
intel_de_posting_read(display, DDI_BUF_CTL(port));
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_posting_read(display, DDI_BUF_CTL(port));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, TRANSCONF(display, pipe));
intel_de_posting_read(display, TRANSCONF(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DEIMR);
intel_de_posting_read(display, GEN8_DE_PORT_IMR);
intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe));
intel_de_posting_read(display, SDEIMR);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, D_COMP_BDW);
intel_de_posting_read(display, LCPLL_CTL);
intel_de_posting_read(display, LCPLL_CTL);
intel_de_posting_read(display, LCPLL_CTL);
intel_de_posting_read(display, DKL_REG_MMIO(reg));
intel_de_posting_read(display, DC_STATE_DEBUG);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL_MD(display, pipe));
intel_de_posting_read(display, DPLL_MD(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL(display, pipe));
intel_de_posting_read(display, DPLL_CTRL1);
intel_de_posting_read(display, regs[id].cfgcr1);
intel_de_posting_read(display, regs[id].cfgcr2);
intel_de_posting_read(display, regs[id].ctl);
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
intel_de_posting_read(display, cfgcr1_reg);
intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
intel_de_posting_read(display, PCH_DPLL(id));
intel_de_posting_read(display, PCH_DPLL(id));
intel_de_posting_read(display, PCH_DPLL(id));
intel_de_posting_read(display, WRPLL_CTL(id));
intel_de_posting_read(display, SPLL_CTL);
intel_de_posting_read(display, WRPLL_CTL(id));
intel_de_posting_read(display, SPLL_CTL);
intel_de_posting_read(display, DVO(port));
intel_de_posting_read(display, DVO(port));
intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, FDI_TX_CTL(pipe));
intel_de_posting_read(display, FDI_RX_CTL(pipe));
intel_de_posting_read(display, FDI_TX_CTL(pipe));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, SOUTH_CHICKEN1);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, FDI_RX_CTL(pipe));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, FDI_TX_CTL(pipe));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, FDI_TX_CTL(pipe));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, FDI_RX_CTL(pipe));
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
intel_de_posting_read(display, FDI_RX_CTL(PIPE_A));
intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
intel_de_posting_read(display, DP_TP_CTL(PORT_E));
intel_de_posting_read(display, FDI_RX_MISC(PIPE_A));
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, GEN7_ERR_INT);
intel_de_posting_read(display, SERR_INT);
intel_de_posting_read(display, bus->gpio_reg);
intel_de_posting_read(display, bus->gpio_reg);
intel_de_posting_read(display, bus->gpio_reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, VIDEO_DIP_CTL);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, ctl_reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, reg);
intel_de_posting_read(display, PICAINTERRUPT_IMR);
intel_de_posting_read(display, GEN11_DE_HPD_IMR);
intel_de_posting_read(display, lvds_encoder->reg);
intel_de_posting_read(display, lvds_encoder->reg);
intel_de_posting_read(display, PCH_DREF_CONTROL);
intel_de_posting_read(display, PCH_DREF_CONTROL);
intel_de_posting_read(display, PCH_DREF_CONTROL);
intel_de_posting_read(display, PCH_DREF_CONTROL);
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe));
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_on_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, intel_dp->output_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, pp_ctrl_reg);
intel_de_posting_read(display, intel_sdvo->sdvo_reg);
intel_de_posting_read(display, intel_sdvo->sdvo_reg);
intel_de_posting_read(display, GEN3_SDVOB);
intel_de_posting_read(display, GEN3_SDVOC);
intel_de_posting_read(display, TV_DAC);
intel_de_posting_read(display, TV_CTL);
intel_de_posting_read(display, vga_reg);
intel_de_posting_read(display, port_ctrl);
intel_de_posting_read(display, port_ctrl);
intel_de_posting_read(display, BXT_DSI_PLL_CTL);