imask
m = imask(bits - 1);
m = imask(bits);
u_int32_t imask(u_int8_t);
struct sockaddr_in sin, imask;
memset(&imask, 0, sizeof(imask));
imask.sin_family = AF_INET;
imask.sin_len = sizeof(sin);
args.ex_mask = (struct sockaddr *)&imask;
args.ex_masklen = sizeof (imask);
imask.sin_addr.s_addr = grp->gr_ptr.gt_net.nt_mask;
imask.sin_addr.s_addr = inet_addr("255.0.0.0");
imask.sin_addr.s_addr = inet_addr("255.255.0.0");
imask.sin_addr.s_addr = inet_addr("255.255.255.0");
grp->gr_ptr.gt_net.nt_mask = imask.sin_addr.s_addr;
u_int64_t imask;
imask = REGVAL64(PYXIS_INT_MASK);
imask |= (1UL << irq);
imask &= ~(1UL << irq);
REGVAL64(PYXIS_INT_MASK) = imask;
u_int64_t imask;
imask = IUNMASK(ci, nlevel);
if (ci->ci_ipending & imask) {
uint32_t imask;
imask = MMCHS_STAT_BRR | MMCHS_STAT_BWR | MMCHS_STAT_BGE |
imask |= MMCHS_STAT_BADA | MMCHS_STAT_CERR | MMCHS_STAT_DEB |
HWRITE4(sc, MMCHS_IE, imask);
HWRITE4(sc, MMCHS_ISE, imask);
uint32_t fclk, iclk, fmask, imask, mbit;
imask = prcm_imask_mask[reg];
if (imask & mbit) { /* dont access the register if bit isn't present */
elroy_write32(&r->imask, htole32(0xffffffff << 30));
u_int32_t imask; /* 0x308 */
imask[level + 1] |= imask[level];
imask[pri] |= (1 << irq);
mask = imask[pri] ^ imask[pri - 1];
imask[pri] |= (1 << irq);
volatile u_long imask[NIPL] = {
bit = ffs(imask[(int)iv->pri]);
imask[(int)iv->pri] |= (1 << bit);
extern volatile u_long imask[NIPL];
extern int imask[]; /* Bitmasks telling what interrupts are blocked. */
#define IMASK(level) imask[IPL(level)]
int imask[NIPL]; /* Bitmask telling what interrupts are blocked. */
imask[level] = irqs | unusedirqs;
imask[level + 1] |= imask[level];
iunmask[irq] = ~imask[irq];
#define BONITO_DIRECT_MASK(imask) ((imask) & ((1L << BONITO_NDIRECT) - 1))
#define BONITO_ISA_MASK(imask) ((imask) >> BONITO_NDIRECT)
loongson3_prop_imask(uint32_t *imask)
imask[IPL_NONE] = 0;
imask[IPL_NET] |= imask[IPL_BIO];
imask[IPL_TTY] |= imask[IPL_NET];
imask[IPL_VM] |= imask[IPL_TTY];
imask[IPL_CLOCK] |= imask[IPL_VM];
imask[IPL_HIGH] |= imask[IPL_CLOCK];
imask[IPL_IPI] |= imask[IPL_HIGH];
u_int32_t imask;
imask = SDHC_INT_STATUS_CC | SDHC_INT_STATUS_TC |
imask |= SDHC_INT_STATUS_CTOE | SDHC_INT_STATUS_CCE |
HWRITE4(sc, SDHC_INT_STATUS_EN, imask);
HWRITE4(sc, SDHC_INT_SIGNAL_EN, imask);
uint32_t imask;
imask = MMC_READ(sc, SXIMMC_IMASK);
imask &= ~SXIMMC_INT_SDIO_INT;
MMC_WRITE(sc, SXIMMC_IMASK, imask);
uint32_t imask;
imask = MMC_READ(sc, SXIMMC_IMASK);
imask |= SXIMMC_INT_SDIO_INT;
imask &= ~SXIMMC_INT_SDIO_INT;
MMC_WRITE(sc, SXIMMC_IMASK, imask);
uint32_t imask;
imask = MMC_READ(sc, SXIMMC_IMASK);
imask |= SXIMMC_INT_SDIO_INT;
MMC_WRITE(sc, SXIMMC_IMASK, imask);
AR_WRITE(sc, AR_IMR, sc->imask);
sc->imask =
sc->imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
sc->imask |= AR_IMR_MIB;
AR_WRITE(sc, AR_IMR, sc->imask);
sc->imask |= AR_IMR_SWBA;
sc->imask |= AR_IMR_BMISS;
uint32_t imask;
uint32_t imask = 0;
imask = 0xffffffff;
imask = RTWN_92C_INT_ENABLE;
rtwn_write_4(sc, R92C_HIMR, imask);
uint32_t imask = 0;
imask |= (1 << sc->sc_queues[i].q_tx.tx_irq);
imask |= (1 << sc->sc_queues[i].q_rx.rx_irq);
imask |= (1 << sc->sc_linkstat_irq);
AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask);
u_int32_t imask; /* interrupt mask */
u_int16_t imask;
imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION |
HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask);
HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask);
u_int8_t imask;
imask = sdmmc_io_read_1(sf0, SD_IO_CCCR_INT_ENABLE);
imask |= 1 << sf->number;
sdmmc_io_write_1(sf0, SD_IO_CCCR_INT_ENABLE, imask);
u_int8_t imask;
imask = sdmmc_io_read_1(sf0, SD_IO_CCCR_INT_ENABLE);
imask &= ~(1 << sf->number);
sdmmc_io_write_1(sf0, SD_IO_CCCR_INT_ENABLE, imask);
uint32_t reg, imask;
imask = htobe32(AR_IMR_SWBA);
imask = htobe32(AR_IMR_BMISS);
&imask, sizeof(imask), NULL);