Symbol: indirect
sys/arch/sparc64/dev/sbus.c
396
sbus_attach_common(struct sbus_softc *sc, int node, int indirect)
sys/arch/sparc64/dev/sbus.c
405
sbt = sbus_alloc_bustag(sc, indirect);
sys/arch/sparc64/dev/sbus.c
765
sbus_alloc_bustag(struct sbus_softc *sc, int indirect)
sys/arch/sparc64/dev/sbus.c
775
if (indirect)
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
43
#define WREG32_SOC15_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
45
if (!indirect) { \
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
53
indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
71
#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
82
indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
sys/dev/pci/drm/amd/amdgpu/amdgpu_jpeg.h
96
#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
143
#define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
145
if (!indirect) { \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
195
#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \
sys/dev/pci/drm/amd/amdgpu/amdgpu_vcn.h
197
if (!indirect) { \
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
356
int inst_idx, uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
367
WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
371
data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
421
static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
444
if (indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
448
jpeg_engine_4_0_5_dpg_clock_gating_mode(adev, inst_idx, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
452
adev->gfx.config.gb_addr_config, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
455
JPEG_SYS_INT_EN__DJRBC_MASK, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
458
WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regUVD_NO_OP_INTERNAL_OFFSET, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v4_0_5.c
460
if (indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
304
int inst_idx, uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
317
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
318
ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
322
ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
324
WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
328
WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
341
static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
353
if (indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
357
jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
360
if (indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
362
adev->gfx.config.gb_addr_config, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
368
if (indirect)
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
370
JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
375
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/jpeg_v5_0_0.c
377
ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
439
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
447
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
450
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
453
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
455
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
458
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
460
UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
462
UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
468
lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
471
upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
475
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
478
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
480
UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
483
UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
486
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
489
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
492
upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
494
UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
497
UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
499
UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
501
UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
504
UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
509
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
512
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
514
UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
516
UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
521
lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
524
upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
526
UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
529
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
533
UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
650
uint8_t sram_sel, uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
683
UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
687
UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
691
UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
695
UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
853
static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
869
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
873
vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
880
UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
884
UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
896
UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
900
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
907
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
914
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
920
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
922
vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
925
UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
927
UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
931
UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
936
0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
941
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_0.c
943
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1002
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1005
static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1023
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1027
vcn_v2_5_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1034
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1038
VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1050
VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1054
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1061
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1068
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1074
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1076
vcn_v2_5_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1079
VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1081
VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1085
VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1087
vcn_v2_6_enable_ras(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1091
VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1096
VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1101
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1103
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
651
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
660
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
663
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
666
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
668
VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
671
VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
673
VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
675
VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
681
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
684
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
688
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
691
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
693
VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
696
VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
699
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
702
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
705
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
707
VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
710
VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
712
VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
714
VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
717
VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
722
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
725
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
727
VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
729
VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
734
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
737
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
739
VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
742
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
746
VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
866
uint8_t sram_sel, uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
900
VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
904
VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
908
VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
912
VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
977
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
992
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
997
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1028
static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1046
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1050
vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1057
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1061
VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1073
VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1077
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1084
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1091
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1097
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1099
vcn_v3_0_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1102
VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1104
VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1108
VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1112
VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1117
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1122
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1126
VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
1128
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
573
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
582
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
585
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
588
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
590
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
593
VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
595
VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
597
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
603
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
606
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
610
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
613
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
615
VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
618
VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
621
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
624
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
627
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
629
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
632
VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
634
VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
636
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
639
VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
644
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
647
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
649
VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
651
VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
656
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
659
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
661
VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
664
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
668
UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
910
uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
944
VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
948
VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
952
VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v3_0.c
956
VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1014
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1018
vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1024
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1028
VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1040
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1044
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1051
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1058
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1064
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1066
vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1071
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1076
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1078
vcn_v4_0_enable_ras(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1083
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
1086
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
510
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
521
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
524
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
527
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
529
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
532
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
534
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
536
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
542
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
545
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
549
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
552
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
554
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
557
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
560
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
563
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
566
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
568
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
571
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
573
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
575
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
578
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
583
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
586
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
588
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
590
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
595
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
598
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
600
VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
603
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
608
adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
856
uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
889
VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
893
VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
897
VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
901
VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
965
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
980
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
985
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0.c
996
static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2107
int inst_idx, bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2120
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2125
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
2130
tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
529
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
541
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
545
inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
549
inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
551
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
554
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
556
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
558
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
564
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
567
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
571
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
574
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
576
VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
579
VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
582
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
585
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
588
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
590
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
593
VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
595
VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
597
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
600
VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
606
AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
610
AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
612
VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
614
VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
619
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
622
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
624
VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
627
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
631
VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
633
VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
741
uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
768
VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
772
VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
776
VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
780
VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
844
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
864
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
875
vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
883
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
887
VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
899
VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
903
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
910
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
917
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
923
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
925
vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
930
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
935
VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
937
vcn_v4_0_3_enable_ras(adev, inst_idx, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
942
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
944
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_3.c
99
int inst_idx, bool indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
461
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
473
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
477
0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
481
0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
483
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
486
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
488
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
490
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
496
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
499
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
503
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
506
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
508
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
511
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
514
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
517
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
520
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
522
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
525
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
527
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
529
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
533
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
539
0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
543
0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
545
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
547
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
552
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
555
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
557
VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
560
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
565
adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
794
uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
827
VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
831
VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
835
VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
839
VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
911
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
929
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
934
vcn_v4_0_5_disable_clock_gating_dpg_mode(vinst, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
940
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
944
VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
956
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
960
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
967
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
974
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
980
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
982
vcn_v4_0_5_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
987
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
992
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
997
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v4_0_5.c
999
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
425
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
437
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
440
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
443
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
445
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
448
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
450
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
452
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
458
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
461
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
465
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
468
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
470
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
473
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
476
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
479
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
482
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
484
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
487
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
489
VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
491
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
494
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
499
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
502
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
504
VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
506
VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
511
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
514
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
516
VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
519
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
524
adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
668
uint8_t indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
695
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
714
if (indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
721
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
725
VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
737
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
739
vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
744
VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
749
VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
754
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_0.c
756
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
485
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
497
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
501
inst_idx].tmr_mc_addr_lo), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
505
inst_idx].tmr_mc_addr_hi), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
507
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
510
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
512
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
514
VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
520
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
523
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
527
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
530
if (!indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
532
VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
535
VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
538
if (!indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
541
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
544
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
546
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
549
VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
551
VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
553
VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
556
VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
562
AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
566
AMDGPU_VCN_STACK_SIZE), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
568
VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
570
VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
575
lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
578
upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
580
VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
583
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
587
VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
667
bool indirect)
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
689
if (indirect) {
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
701
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
705
VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
717
VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
719
vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
724
VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
729
VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
734
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
sys/dev/pci/drm/amd/amdgpu/vcn_v5_0_1.c
736
if (indirect) {
sys/kern/subr_autoconf.c
137
if (m->indirect)
sys/kern/subr_autoconf.c
163
if (m->indirect && m->match) {
sys/kern/subr_autoconf.c
170
if (m->indirect)
sys/kern/subr_autoconf.c
197
m.indirect = parent && (parent->dv_cfdata->cf_driver->cd_mode & CD_INDIRECT);
sys/kern/subr_autoconf.c
229
if (m.indirect)
sys/kern/subr_autoconf.c
255
int indirect;
sys/kern/subr_autoconf.c
257
indirect = parent && (parent->dv_cfdata->cf_driver->cd_mode & CD_INDIRECT);
sys/kern/subr_autoconf.c
272
match = indirect?
sys/kern/subr_autoconf.c
295
m.indirect = 0;
sys/kern/subr_autoconf.c
75
int indirect, pri;
usr.bin/awk/proto.h
170
extern Cell *indirect(Node **, int);