sys/arch/amd64/amd64/db_disasm.c

102

int i_mode; /* addressing modes */

sys/arch/amd64/amd64/db_disasm.c

1132

int i_mode;

sys/arch/amd64/amd64/db_disasm.c

1256

i_mode = ip->i_mode;

sys/arch/amd64/amd64/db_disasm.c

1263

i_mode = ip->i_mode;

sys/arch/amd64/amd64/db_disasm.c

1271

i_mode = ip->i_mode;

sys/arch/amd64/amd64/db_disasm.c

1275

if ((i_mode & 0xFF) == MEx) {

sys/arch/amd64/amd64/db_disasm.c

1277

i_mode = op1(E);

sys/arch/amd64/amd64/db_disasm.c

1280

if (f_rm(regmodrm, 0) > (i_mode >> 8))

sys/arch/amd64/amd64/db_disasm.c

1290

i_mode = 0;

sys/arch/amd64/amd64/db_disasm.c

1329

for (first = 1; i_mode != 0; i_mode >>= 8, first = 0) {

sys/arch/amd64/amd64/db_disasm.c

1333

switch (i_mode & 0xFF) {

sys/arch/i386/i386/db_disasm.c

103

int i_mode; /* addressing modes */

sys/arch/i386/i386/db_disasm.c

1098

int i_mode;

sys/arch/i386/i386/db_disasm.c

1185

i_mode = ip->i_mode;

sys/arch/i386/i386/db_disasm.c

1192

i_mode = ip->i_mode;

sys/arch/i386/i386/db_disasm.c

1200

i_mode = ip->i_mode;

sys/arch/i386/i386/db_disasm.c

1204

if ((i_mode & 0xFF) == MEx) {

sys/arch/i386/i386/db_disasm.c

1206

i_mode = op1(E);

sys/arch/i386/i386/db_disasm.c

1209

if (f_rm(regmodrm) > (i_mode >> 8))

sys/arch/i386/i386/db_disasm.c

1219

i_mode = 0;

sys/arch/i386/i386/db_disasm.c

1246

i_mode != 0;

sys/arch/i386/i386/db_disasm.c

1247

i_mode >>= 8, first = 0) {

sys/arch/i386/i386/db_disasm.c

1251

switch (i_mode & 0xFF) {

sys/dev/ic/if_wi.c

2961

if (txpower->i_mode == IEEE80211_TXPOWER_MODE_AUTO) {

sys/dev/ic/if_wi.c

3035

txpower->i_mode = IEEE80211_TXPOWER_MODE_FIXED;

sys/dev/ic/if_wi.c

3037

txpower->i_mode = IEEE80211_TXPOWER_MODE_AUTO;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

972

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

977

CM_3DLUT_CONFIG_STATUS, &i_mode,

sys/dev/pci/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

980

switch (i_mode) {

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1238

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1245

CM_3DLUT_MODE_CURRENT, &i_mode);

sys/dev/pci/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1247

switch (i_mode) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

932

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

937

MPC_RMU_3DLUT_MODE_CURRENT, &i_mode);

sys/dev/pci/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

942

switch (i_mode) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

759

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

764

MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode);

sys/dev/pci/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

769

switch (i_mode) {

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

72

uint32_t i_mode, i_enable_10bits, lut_size;

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

77

MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode);

sys/dev/pci/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

82

switch (i_mode) {

sys/net80211/ieee80211_ioctl.h

206

int i_mode; /* auto, manual */