Symbol: hwsp_offset
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
431
return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
447
*cs++ = hwsp_offset(rq);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
659
return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
680
hwsp_offset(rq),
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
701
hwsp_offset(rq),
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
847
hwsp_offset(rq),
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2029
tl ? tl->hwsp_offset : 0,
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
2313
tl->hwsp_offset);
sys/dev/pci/drm/i915/gt/intel_timeline.c
208
tl->hwsp_offset =
sys/dev/pci/drm/i915/gt/intel_timeline.c
210
offset_in_page(tl->hwsp_offset);
sys/dev/pci/drm/i915/gt/intel_timeline.c
212
tl->fence_context, tl->hwsp_offset);
sys/dev/pci/drm/i915/gt/intel_timeline.c
311
u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES);
sys/dev/pci/drm/i915/gt/intel_timeline.c
317
tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs;
sys/dev/pci/drm/i915/gt/intel_timeline.c
61
u32 ofs = offset_in_page(timeline->hwsp_offset);
sys/dev/pci/drm/i915/gt/intel_timeline.c
86
timeline->hwsp_offset = offset;
sys/dev/pci/drm/i915/gt/intel_timeline.c
97
timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;
sys/dev/pci/drm/i915/gt/intel_timeline.c
99
GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
sys/dev/pci/drm/i915/gt/intel_timeline.h
83
u32 *hwsp_offset);
sys/dev/pci/drm/i915/gt/intel_timeline_types.h
49
u32 hwsp_offset;
sys/dev/pci/drm/i915/gt/selftest_rc6.c
179
*cs++ = ce->timeline->hwsp_offset + 8;
sys/dev/pci/drm/i915/gt/selftest_timeline.c
1396
tl->hwsp_offset, *tl->hwsp_seqno);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
39
return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES;
sys/dev/pci/drm/i915/gt/selftest_timeline.c
509
err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
586
n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
658
n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
718
seqno[0], tl->hwsp_offset);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
720
err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
735
seqno[1], tl->hwsp_offset);
sys/dev/pci/drm/i915/gt/selftest_timeline.c
737
err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5805
i915_request_active_timeline(rq)->hwsp_offset,
sys/dev/pci/drm/i915/gt/uc/intel_guc_submission.c
5881
i915_request_active_timeline(rq)->hwsp_offset,
sys/dev/pci/drm/i915/i915_request.c
1232
u32 hwsp_offset;
sys/dev/pci/drm/i915/i915_request.c
1240
err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
sys/dev/pci/drm/i915/i915_request.c
1266
*cs++ = hwsp_offset;
sys/dev/pci/drm/i915/i915_request.h
701
page_mask_bits(i915_request_active_timeline(rq)->hwsp_offset);
sys/dev/pci/drm/i915/selftests/i915_request.c
2017
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2092
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2163
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2266
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2357
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2451
const u32 offset = hwsp_offset(ce, sema);
sys/dev/pci/drm/i915/selftests/i915_request.c
2571
const u32 offset = hwsp_offset(ce, sema);