hweight8
return hweight8(sc->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
switch (hweight8(count)) {
if (check_dprx && hweight8(tunnel_reg_max_dprx_lane_count(regs)) != 1) {
int num_active_planes = hweight8(active_planes);
int num_active_planes = hweight8(active_planes);
num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
hweight8(old_cdclk_state->active_pipes);
num_active_pipes = hweight8(new_cdclk_state->active_pipes);
update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
hweight8(old_cdclk_state->active_pipes);
num_active_pipes = hweight8(new_cdclk_state->active_pipes);
bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
hweight8(new_cdclk_state->active_pipes);
hweight8(lane_mask) != 1))
if (hweight8(dp128b132b_pipe_mask) > 1 ||
if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
return hweight8(crtc_state->joiner_pipes) >= 2;
return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
#define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
if (hweight8(intel_dsi->ports) == 1)
if (hweight8(md->ccs.planar_aux_planes) == 2)
drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
ones += hweight8(ksv[i]);
hweight8(crtc_state->nv12_planes));
if (hweight8(old_active_planes) == hweight8(new_active_planes))
u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
if (hweight8(active_planes) == 3) {
} else if (hweight8(active_planes) == 2) {
if (hweight8(active_planes) == 2) {
if (hweight8(active_planes) == 2) {
int num_active = hweight8(dbuf_state->active_pipes);
return hweight8(dbuf_state->enabled_slices);
return hweight8(dbuf_state->active_pipes);
hweight8(DISPLAY_INFO(display)->dbuf.slice_mask);
unsigned int hw_s = hweight8(device->slice_mask);
unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
total += hweight8(sseu->subslice_mask.hsw[i]);
hweight8(eu_disabled_mask);
!IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1;
RUNTIME_INFO(i915)->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
n_disabled = hweight8(eu_disabled_mask);
sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
hweight8(subslice_mask),
slices = hweight8(req_sseu->slice_mask);
subslices = hweight8(req_sseu->subslice_mask);
subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
hweight8(sseu->slice_mask), sseu->slice_mask);
s, hweight8(ss_mask), ss_mask);
s, hweight8(ss_mask), ss_mask);
s, hweight8(sseu->subslice_mask.hsw[s]));
sseu->eu_total -= hweight8(subslice_7eu);
hweight8(sseu->slice_mask));
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
hweight8(gt->info.sseu.slice_mask));
~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
for (i = 0; i < hweight8(mphy->antenna_mask); i++) {