Symbol: i915_reg_t
sys/dev/pci/drm/i915/display/g4x_dp.c
1285
i915_reg_t output_reg, enum port port)
sys/dev/pci/drm/i915/display/g4x_dp.c
277
i915_reg_t dp_reg, enum port port,
sys/dev/pci/drm/i915/display/g4x_dp.h
23
i915_reg_t dp_reg, enum port port,
sys/dev/pci/drm/i915/display/g4x_dp.h
26
i915_reg_t output_reg, enum port port);
sys/dev/pci/drm/i915/display/g4x_dp.h
33
i915_reg_t dp_reg, int port,
sys/dev/pci/drm/i915/display/g4x_dp.h
39
i915_reg_t output_reg, int port)
sys/dev/pci/drm/i915/display/g4x_hdmi.c
670
i915_reg_t hdmi_reg, enum port port)
sys/dev/pci/drm/i915/display/g4x_hdmi.h
20
i915_reg_t hdmi_reg, enum port port);
sys/dev/pci/drm/i915/display/g4x_hdmi.h
25
i915_reg_t hdmi_reg, int port)
sys/dev/pci/drm/i915/display/icl_dsi.c
300
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
sys/dev/pci/drm/i915/display/intel_audio.c
600
i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
sys/dev/pci/drm/i915/display/intel_color.c
1338
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_color.c
1349
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_combo_phy.c
95
enum phy phy, i915_reg_t reg, u32 mask,
sys/dev/pci/drm/i915/display/intel_crt.c
1010
i915_reg_t adpa_reg;
sys/dev/pci/drm/i915/display/intel_crt.c
78
i915_reg_t adpa_reg;
sys/dev/pci/drm/i915/display/intel_crt.c
92
i915_reg_t adpa_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_crt.h
17
i915_reg_t adpa_reg, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_crt.h
22
i915_reg_t adpa_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_cx0_phy.c
2825
i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
sys/dev/pci/drm/i915/display/intel_ddi.c
1552
static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1568
static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1578
static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
1585
_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_ddi.c
188
static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/intel_ddi.c
2266
i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_ddi.c
2278
static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_ddi.c
2555
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_ddi.c
3057
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_ddi.c
3386
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_ddi.c
3439
i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
sys/dev/pci/drm/i915/display/intel_ddi.h
26
i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
sys/dev/pci/drm/i915/display/intel_de.h
109
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
118
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
127
intel_de_wait(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
143
intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
159
intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
178
intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
185
intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
200
intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
21
intel_de_read(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
211
intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
218
intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
224
intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
231
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
35
intel_de_read8(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
50
i915_reg_t lower_reg, i915_reg_t upper_reg)
sys/dev/pci/drm/i915/display/intel_de.h
67
intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_de.h
77
intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_de.h
87
__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_de.h
94
intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/display/intel_display.c
2573
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
sys/dev/pci/drm/i915/display/intel_display.c
2574
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
sys/dev/pci/drm/i915/display/intel_display.c
3315
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
sys/dev/pci/drm/i915/display/intel_display.c
3316
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
sys/dev/pci/drm/i915/display/intel_display.h
467
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
sys/dev/pci/drm/i915/display/intel_display.h
468
i915_reg_t link_m_reg, i915_reg_t link_n_reg);
sys/dev/pci/drm/i915/display/intel_display.h
471
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
sys/dev/pci/drm/i915/display/intel_display.h
472
i915_reg_t link_m_reg, i915_reg_t link_n_reg);
sys/dev/pci/drm/i915/display/intel_display_irq.c
1221
i915_reg_t iir_reg;
sys/dev/pci/drm/i915/display/intel_display_irq.c
326
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_display_irq.c
350
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_display_irq.c
527
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_display_irq.c
65
intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_display_power.c
1073
i915_reg_t reg = DBUF_CTL_S(slice);
sys/dev/pci/drm/i915/display/intel_display_power.c
1438
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
52
i915_reg_t bios;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
53
i915_reg_t driver;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
54
i915_reg_t kvmr;
sys/dev/pci/drm/i915/display/intel_display_power_well.c
55
i915_reg_t debug;
sys/dev/pci/drm/i915/display/intel_display_types.h
1568
i915_reg_t hdmi_reg;
sys/dev/pci/drm/i915/display/intel_display_types.h
1696
i915_reg_t output_reg;
sys/dev/pci/drm/i915/display/intel_display_types.h
1800
i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
sys/dev/pci/drm/i915/display/intel_display_types.h
1801
i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
sys/dev/pci/drm/i915/display/intel_dmc.c
1591
i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
sys/dev/pci/drm/i915/display/intel_dmc.c
1620
i915_reg_t dc3co_reg;
sys/dev/pci/drm/i915/display/intel_dmc.c
435
i915_reg_t ctl_reg, i915_reg_t htp_reg)
sys/dev/pci/drm/i915/display/intel_dmc.c
525
enum intel_dmc_id dmc_id, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc.c
535
enum intel_dmc_id dmc_id, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc.c
547
i915_reg_t reg, u32 data)
sys/dev/pci/drm/i915/display/intel_dmc.c
555
i915_reg_t reg_ctl, u32 *data_ctl,
sys/dev/pci/drm/i915/display/intel_dmc.c
556
i915_reg_t reg_htp, u32 *data_htp)
sys/dev/pci/drm/i915/display/intel_dmc.c
585
i915_reg_t reg, u32 data)
sys/dev/pci/drm/i915/display/intel_dmc.c
668
i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
sys/dev/pci/drm/i915/display/intel_dmc.c
76
i915_reg_t mmioaddr[20];
sys/dev/pci/drm/i915/display/intel_dmc.c
825
i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
228
static bool intel_dmc_wl_reg_in_range(i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
244
i915_reg_t reg,
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
435
void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc_wl.c
468
void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
36
void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
sys/dev/pci/drm/i915/display/intel_dmc_wl.h
37
void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
sys/dev/pci/drm/i915/display/intel_dp.c
4838
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_dp_aux.c
245
i915_reg_t ch_ctl, ch_data[5];
sys/dev/pci/drm/i915/display/intel_dp_aux.c
555
static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
571
static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
587
static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
60
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
sys/dev/pci/drm/i915/display/intel_dp_aux.c
603
static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
619
static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
637
static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
655
static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
674
static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
693
static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
715
static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
737
static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
sys/dev/pci/drm/i915/display/intel_dp_aux.c
757
static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1175
i915_reg_t dpll_reg;
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
282
i915_reg_t reg_single,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
283
i915_reg_t reg_group,
sys/dev/pci/drm/i915/display/intel_dpio_phy.c
515
i915_reg_t reg, u32 mask, u32 expected,
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
1336
i915_reg_t ctl, cfgcr1, cfgcr2;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
206
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
219
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3559
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3690
i915_reg_t enable_reg)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3752
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3769
i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3916
i915_reg_t enable_reg)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3931
i915_reg_t enable_reg)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3969
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4014
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4036
i915_reg_t enable_reg)
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4068
i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
4082
i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
sys/dev/pci/drm/i915/display/intel_dsb.c
289
u32 opcode, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dsb.c
307
static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg)
sys/dev/pci/drm/i915/display/intel_dsb.c
328
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
366
i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
384
i915_reg_t reg, u32 mask, u32 val)
sys/dev/pci/drm/i915/display/intel_dsb.c
514
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_dsb.h
40
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
42
i915_reg_t reg, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
44
i915_reg_t reg, u32 mask, u32 val);
sys/dev/pci/drm/i915/display/intel_dsb.h
62
i915_reg_t reg, u32 mask, u32 val,
sys/dev/pci/drm/i915/display/intel_fdi.c
1000
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
1053
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
442
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
483
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
584
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fdi.c
719
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
117
i915_reg_t reg = PIPESTAT(display, pipe);
sys/dev/pci/drm/i915/display/intel_fifo_underrun.c
97
i915_reg_t reg = PIPESTAT(display, crtc->pipe);
sys/dev/pci/drm/i915/display/intel_gmbus.c
469
intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
sys/dev/pci/drm/i915/display/intel_gmbus.c
52
i915_reg_t gpio_reg;
sys/dev/pci/drm/i915/display/intel_hdcp.c
50
i915_reg_t rekey_reg;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1010
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_hdmi.c
1059
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1117
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1166
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
1221
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
sys/dev/pci/drm/i915/display/intel_hdmi.c
1246
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
sys/dev/pci/drm/i915/display/intel_hdmi.c
163
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_hdmi.c
288
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
341
i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
363
i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
437
i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
sys/dev/pci/drm/i915/display/intel_hdmi.c
513
i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
sys/dev/pci/drm/i915/display/intel_hdmi.c
874
i915_reg_t reg = VIDEO_DIP_CTL;
sys/dev/pci/drm/i915/display/intel_hdmi.c
985
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_lvds.c
73
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_lvds.c
849
i915_reg_t lvds_reg;
sys/dev/pci/drm/i915/display/intel_lvds.c
88
i915_reg_t lvds_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_lvds.h
18
i915_reg_t lvds_reg, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_lvds.h
24
i915_reg_t lvds_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_pch_display.c
119
enum port port, i915_reg_t hdmi_reg)
sys/dev/pci/drm/i915/display/intel_pch_display.c
138
enum port port, i915_reg_t dp_reg)
sys/dev/pci/drm/i915/display/intel_pch_display.c
251
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_pch_display.c
317
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_pch_display.c
421
i915_reg_t reg = TRANS_DP_CTL(pipe);
sys/dev/pci/drm/i915/display/intel_pch_display.c
44
i915_reg_t dp_reg)
sys/dev/pci/drm/i915/display/intel_pch_display.c
63
i915_reg_t hdmi_reg)
sys/dev/pci/drm/i915/display/intel_pps.c
1042
i915_reg_t pp_ctrl_reg;
sys/dev/pci/drm/i915/display/intel_pps.c
1108
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
sys/dev/pci/drm/i915/display/intel_pps.c
1129
i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
sys/dev/pci/drm/i915/display/intel_pps.c
1174
i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe);
sys/dev/pci/drm/i915/display/intel_pps.c
1842
i915_reg_t pp_reg;
sys/dev/pci/drm/i915/display/intel_pps.c
492
i915_reg_t pp_ctrl;
sys/dev/pci/drm/i915/display/intel_pps.c
493
i915_reg_t pp_stat;
sys/dev/pci/drm/i915/display/intel_pps.c
494
i915_reg_t pp_on;
sys/dev/pci/drm/i915/display/intel_pps.c
495
i915_reg_t pp_off;
sys/dev/pci/drm/i915/display/intel_pps.c
496
i915_reg_t pp_div;
sys/dev/pci/drm/i915/display/intel_pps.c
527
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_pps.c
537
static i915_reg_t
sys/dev/pci/drm/i915/display/intel_pps.c
611
i915_reg_t pp_stat_reg, pp_ctrl_reg;
sys/dev/pci/drm/i915/display/intel_pps.c
750
i915_reg_t pp_stat_reg, pp_ctrl_reg;
sys/dev/pci/drm/i915/display/intel_pps.c
833
i915_reg_t pp_stat_reg, pp_ctrl_reg;
sys/dev/pci/drm/i915/display/intel_pps.c
967
i915_reg_t pp_ctrl_reg;
sys/dev/pci/drm/i915/display/intel_psr.c
2127
i915_reg_t psr_status;
sys/dev/pci/drm/i915/display/intel_psr.c
302
static i915_reg_t psr_ctl_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
311
static i915_reg_t psr_debug_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
3152
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_psr.c
320
static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
329
static i915_reg_t psr_status_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
338
static i915_reg_t psr_imr_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
347
static i915_reg_t psr_iir_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
356
static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_psr.c
365
static i915_reg_t psr_aux_data_reg(struct intel_display *display,
sys/dev/pci/drm/i915/display/intel_sdvo.c
104
i915_reg_t sdvo_reg;
sys/dev/pci/drm/i915/display/intel_sdvo.c
1668
i915_reg_t sdvo_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_sdvo.c
3384
i915_reg_t sdvo_reg, enum port port)
sys/dev/pci/drm/i915/display/intel_sdvo.h
19
i915_reg_t sdvo_reg, enum pipe *pipe);
sys/dev/pci/drm/i915/display/intel_sdvo.h
21
i915_reg_t reg, enum port port);
sys/dev/pci/drm/i915/display/intel_sdvo.h
24
i915_reg_t sdvo_reg, enum pipe *pipe)
sys/dev/pci/drm/i915/display/intel_sdvo.h
29
i915_reg_t reg, enum port port)
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1825
i915_reg_t enable_reg = (phy <= PHY_D ?
sys/dev/pci/drm/i915/display/intel_snps_phy.c
1882
i915_reg_t enable_reg = (phy <= PHY_D ?
sys/dev/pci/drm/i915/display/intel_tc.c
1044
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1104
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1151
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
1168
i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
sys/dev/pci/drm/i915/display/intel_tc.c
300
i915_reg_t reg;
sys/dev/pci/drm/i915/display/intel_vblank.c
484
i915_reg_t reg = PIPEDSL(display, pipe);
sys/dev/pci/drm/i915/display/intel_vdsc.c
417
i915_reg_t *dsc_reg, int dsc_reg_num)
sys/dev/pci/drm/i915/display/intel_vdsc.c
440
i915_reg_t dsc_reg[3];
sys/dev/pci/drm/i915/display/intel_vdsc.c
777
static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
sys/dev/pci/drm/i915/display/intel_vdsc.c
783
static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
sys/dev/pci/drm/i915/display/intel_vdsc.c
863
i915_reg_t dsc_reg[3];
sys/dev/pci/drm/i915/display/intel_vga.c
21
static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
sys/dev/pci/drm/i915/display/intel_vga.c
48
i915_reg_t vga_reg = intel_vga_cntrl_reg(display);
sys/dev/pci/drm/i915/display/vlv_dsi.c
103
i915_reg_t reg,
sys/dev/pci/drm/i915/display/vlv_dsi.c
119
i915_reg_t reg,
sys/dev/pci/drm/i915/display/vlv_dsi.c
142
i915_reg_t data_reg, ctrl_reg;
sys/dev/pci/drm/i915/display/vlv_dsi.c
563
static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port)
sys/dev/pci/drm/i915/display/vlv_dsi.c
578
i915_reg_t port_ctrl = display->platform.broxton ?
sys/dev/pci/drm/i915/display/vlv_dsi.c
635
i915_reg_t port_ctrl = port_ctrl_reg(display, port);
sys/dev/pci/drm/i915/display/vlv_dsi.c
670
i915_reg_t port_ctrl = port_ctrl_reg(display, port);
sys/dev/pci/drm/i915/display/vlv_dsi.c
961
i915_reg_t port_ctrl = port_ctrl_reg(display, port);
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
200
i915_reg_t hic = _MMIO(I830_HIC);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
168
static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine)
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
190
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
sys/dev/pci/drm/i915/gt/gen8_engine_cs.c
201
i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1634
const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
sys/dev/pci/drm/i915/gt/intel_engine_cs.c
1706
static const i915_reg_t _reg[I915_NUM_ENGINES] = {
sys/dev/pci/drm/i915/gt/intel_engine_types.h
354
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
140
i915_reg_t reg = FENCE_REG(fence->id);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
165
i915_reg_t reg = FENCE_REG(fence->id);
sys/dev/pci/drm/i915/gt/intel_ggtt_fencing.c
61
i915_reg_t fence_reg_lo, fence_reg_hi;
sys/dev/pci/drm/i915/gt/intel_gt.c
232
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
sys/dev/pci/drm/i915/gt/intel_gt.c
368
i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
sys/dev/pci/drm/i915/gt/intel_gt.h
148
i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
186
static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
sys/dev/pci/drm/i915/gt/intel_gt_mcr.c
188
i915_reg_t r = { .reg = mcr.reg };
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
18
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
65
i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
sys/dev/pci/drm/i915/gt/intel_gt_pm_irq.c
79
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_gt_sysfs_pm.c
512
i915_reg_t (*reg32)(struct intel_gt *gt);
sys/dev/pci/drm/i915/gt/intel_lrc.c
1717
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/intel_rc6.c
573
i915_reg_t res_reg[INTEL_RC6_RES_MAX] = {
sys/dev/pci/drm/i915/gt/intel_rc6.c
739
static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_rc6.c
789
i915_reg_t reg = rc6->res_reg[id];
sys/dev/pci/drm/i915/gt/intel_rc6.c
856
i915_reg_t reg = gt->rc6.res_reg[id];
sys/dev/pci/drm/i915/gt/intel_rc6_types.h
27
i915_reg_t res_reg[INTEL_RC6_RES_MAX];
sys/dev/pci/drm/i915/gt/intel_reset.c
365
i915_reg_t lock_reg;
sys/dev/pci/drm/i915/gt/intel_reset.c
366
i915_reg_t ack_reg;
sys/dev/pci/drm/i915/gt/intel_reset.c
367
i915_reg_t usage_reg;
sys/dev/pci/drm/i915/gt/intel_reset.c
563
const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
80
i915_reg_t hwsp;
sys/dev/pci/drm/i915/gt/intel_ring_submission.c
818
i915_reg_t last_reg = INVALID_MMIO_REG; /* keep gcc quiet */
sys/dev/pci/drm/i915/gt/intel_rps.c
2089
i915_reg_t rpstat;
sys/dev/pci/drm/i915/gt/intel_rps.c
2123
i915_reg_t r = INVALID_MMIO_REG;
sys/dev/pci/drm/i915/gt/intel_rps.c
2716
static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)
sys/dev/pci/drm/i915/gt/intel_rps.c
2729
i915_reg_t reg32, u32 mask)
sys/dev/pci/drm/i915/gt/intel_rps.c
75
static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_rps.h
63
bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
sys/dev/pci/drm/i915/gt/intel_sseu.c
202
fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1270
i915_reg_t steering_reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1861
whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
1896
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
216
static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds.c
246
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
258
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
264
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
276
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
299
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
311
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
sys/dev/pci/drm/i915/gt/intel_workarounds.c
323
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
sys/dev/pci/drm/i915/gt/intel_workarounds_types.h
17
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1007
u32 a, u32 b, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
1024
i915_reg_t reg))
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
180
i915_reg_t reg = i < engine->whitelist.count ?
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
952
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
957
i915_reg_t reg,
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
973
static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
985
u32 a, u32 b, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/selftest_workarounds.c
996
static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
sys/dev/pci/drm/i915/gt/uc/guc_capture_fwif.h
89
i915_reg_t reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc.c
57
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
sys/dev/pci/drm/i915/gt/uc/intel_guc.h
234
i915_reg_t notify_reg;
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1505
i915_reg_t reg_ipehr = RING_IPEHR(0);
sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1506
i915_reg_t reg_instdone = RING_INSTDONE(0);
sys/dev/pci/drm/i915/gt/uc/intel_huc.h
38
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/aperture_gm.c
137
i915_reg_t fence_reg_lo, fence_reg_hi;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1272
i915_reg_t stride_reg;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1273
i915_reg_t ctrl_reg;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
1274
i915_reg_t surf_reg;
sys/dev/pci/drm/i915/gvt/gvt.h
256
i915_reg_t offset;
sys/dev/pci/drm/i915/gvt/handlers.c
732
static i915_reg_t force_nonpriv_white_list[] = {
sys/dev/pci/drm/i915/gvt/handlers.c
770
i915_reg_t *array = force_nonpriv_white_list;
sys/dev/pci/drm/i915/gvt/handlers.c
853
i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
sys/dev/pci/drm/i915/gvt/handlers.c
893
static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
sys/dev/pci/drm/i915/gvt/handlers.c
894
i915_reg_t _next, i915_reg_t _end)
sys/dev/pci/drm/i915/gvt/handlers.c
919
i915_reg_t fdi_rx_iir;
sys/dev/pci/drm/i915/gvt/handlers.c
963
i915_reg_t status_reg;
sys/dev/pci/drm/i915/gvt/interrupt.c
42
i915_reg_t reg_base;
sys/dev/pci/drm/i915/gvt/mmio_context.c
182
i915_reg_t offset;
sys/dev/pci/drm/i915/gvt/mmio_context.c
371
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/mmio_context.c
420
i915_reg_t offset, l3_offset;
sys/dev/pci/drm/i915/gvt/mmio_context.c
52
i915_reg_t reg;
sys/dev/pci/drm/i915/gvt/scheduler.c
271
i915_reg_t reg;
sys/dev/pci/drm/i915/i915_cmd_parser.c
575
i915_reg_t addr;
sys/dev/pci/drm/i915/i915_gpu_error.c
1410
i915_reg_t mmio;
sys/dev/pci/drm/i915/i915_hwmon.c
100
hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr,
sys/dev/pci/drm/i915/i915_hwmon.c
142
i915_reg_t rgaddr;
sys/dev/pci/drm/i915/i915_hwmon.c
35
i915_reg_t gt_perf_status;
sys/dev/pci/drm/i915/i915_hwmon.c
36
i915_reg_t pkg_temp;
sys/dev/pci/drm/i915/i915_hwmon.c
37
i915_reg_t pkg_power_sku_unit;
sys/dev/pci/drm/i915/i915_hwmon.c
38
i915_reg_t pkg_power_sku;
sys/dev/pci/drm/i915/i915_hwmon.c
39
i915_reg_t pkg_rapl_limit;
sys/dev/pci/drm/i915/i915_hwmon.c
40
i915_reg_t energy_status_all;
sys/dev/pci/drm/i915/i915_hwmon.c
41
i915_reg_t energy_status_tile;
sys/dev/pci/drm/i915/i915_hwmon.c
42
i915_reg_t fan_speed;
sys/dev/pci/drm/i915/i915_hwmon.c
583
i915_reg_t rgaddr;
sys/dev/pci/drm/i915/i915_hwmon.c
79
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/i915_ioctl.c
23
i915_reg_t offset_ldw;
sys/dev/pci/drm/i915/i915_ioctl.c
24
i915_reg_t offset_udw;
sys/dev/pci/drm/i915/i915_irq.c
176
i915_reg_t reg;
sys/dev/pci/drm/i915/i915_irq.c
98
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/i915_irq.h
43
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
sys/dev/pci/drm/i915/i915_perf.c
1335
__store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
sys/dev/pci/drm/i915/i915_perf.c
1358
__read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset)
sys/dev/pci/drm/i915/i915_perf.c
1503
i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
sys/dev/pci/drm/i915/i915_perf.c
1934
bool save, i915_reg_t reg, u32 offset,
sys/dev/pci/drm/i915/i915_perf.c
1977
i915_reg_t mi_predicate_result = HAS_MI_SET_PREDICATE(i915) ?
sys/dev/pci/drm/i915/i915_perf.c
2441
i915_reg_t reg)
sys/dev/pci/drm/i915/i915_perf.c
2475
static const i915_reg_t flex_regs[] = {
sys/dev/pci/drm/i915/i915_perf.c
2498
i915_reg_t reg;
sys/dev/pci/drm/i915/i915_perf.c
4348
static const i915_reg_t flex_eu_regs[] = {
sys/dev/pci/drm/i915/i915_perf.c
914
i915_reg_t oaheadptr;
sys/dev/pci/drm/i915/i915_perf.c
963
i915_reg_t oastatus_reg;
sys/dev/pci/drm/i915/i915_perf_types.h
50
i915_reg_t oa_head_ptr;
sys/dev/pci/drm/i915/i915_perf_types.h
51
i915_reg_t oa_tail_ptr;
sys/dev/pci/drm/i915/i915_perf_types.h
52
i915_reg_t oa_buffer;
sys/dev/pci/drm/i915/i915_perf_types.h
53
i915_reg_t oa_ctx_ctrl;
sys/dev/pci/drm/i915/i915_perf_types.h
54
i915_reg_t oa_ctrl;
sys/dev/pci/drm/i915/i915_perf_types.h
55
i915_reg_t oa_debug;
sys/dev/pci/drm/i915/i915_perf_types.h
56
i915_reg_t oa_status;
sys/dev/pci/drm/i915/i915_perf_types.h
73
i915_reg_t addr;
sys/dev/pci/drm/i915/i915_reg_defs.h
181
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
sys/dev/pci/drm/i915/i915_reg_defs.h
197
_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
sys/dev/pci/drm/i915/i915_reg_defs.h
203
i915_reg_t imr;
sys/dev/pci/drm/i915/i915_reg_defs.h
204
i915_reg_t ier;
sys/dev/pci/drm/i915/i915_reg_defs.h
205
i915_reg_t iir;
sys/dev/pci/drm/i915/i915_reg_defs.h
212
i915_reg_t emr;
sys/dev/pci/drm/i915/i915_reg_defs.h
213
i915_reg_t eir;
sys/dev/pci/drm/i915/intel_uncore.c
1217
gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/intel_uncore.c
1797
const i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
1811
const i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
1823
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1839
const i915_reg_t reg, const bool read)
sys/dev/pci/drm/i915/intel_uncore.c
1850
vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1870
gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1878
gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1945
fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
sys/dev/pci/drm/i915/intel_uncore.c
1957
fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) {
sys/dev/pci/drm/i915/intel_uncore.c
1978
gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
1986
gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2022
gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2035
fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2046
fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
sys/dev/pci/drm/i915/intel_uncore.c
2061
vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
sys/dev/pci/drm/i915/intel_uncore.c
2098
i915_reg_t reg_set,
sys/dev/pci/drm/i915/intel_uncore.c
2099
i915_reg_t reg_ack)
sys/dev/pci/drm/i915/intel_uncore.c
2768
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
2817
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.c
2917
i915_reg_t reg, unsigned int op)
sys/dev/pci/drm/i915/intel_uncore.h
100
i915_reg_t r);
sys/dev/pci/drm/i915/intel_uncore.h
103
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
105
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
107
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
109
i915_reg_t r, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
112
i915_reg_t r, u8 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
114
i915_reg_t r, u16 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
116
i915_reg_t r, u32 val, bool trace);
sys/dev/pci/drm/i915/intel_uncore.h
261
i915_reg_t reg, unsigned int op);
sys/dev/pci/drm/i915/intel_uncore.h
287
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
295
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
305
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
313
i915_reg_t reg,
sys/dev/pci/drm/i915/intel_uncore.h
328
i915_reg_t reg) \
sys/dev/pci/drm/i915/intel_uncore.h
338
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
360
i915_reg_t reg) \
sys/dev/pci/drm/i915/intel_uncore.h
367
i915_reg_t reg, u##x__ val) \
sys/dev/pci/drm/i915/intel_uncore.h
437
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/intel_uncore.h
448
i915_reg_t reg, u32 clear, u32 set)
sys/dev/pci/drm/i915/intel_uncore.h
460
i915_reg_t lower_reg, i915_reg_t upper_reg)
sys/dev/pci/drm/i915/intel_uncore.h
489
i915_reg_t reg, u32 val,
sys/dev/pci/drm/i915/intel_uncore.h
98
i915_reg_t r);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
211
i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
sys/dev/pci/drm/i915/selftests/intel_uncore.c
305
i915_reg_t reg = { offset };
sys/dev/pci/drm/i915/selftests/intel_uncore.c
316
i915_reg_t reg = { offset };
sys/dev/pci/drm/i915/selftests/mock_uncore.c
29
nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
sys/dev/pci/drm/i915/selftests/mock_uncore.c
36
nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
sys/dev/pci/drm/i915/vlv_suspend.c
284
i915_reg_t reg = VLV_GTLC_PW_STATUS;